CN106419862B - Signal reading circuit, control method thereof and pulse detector - Google Patents

Abstract

A signal reading circuit, its control method and a pulse detector. The signal reading circuit includes a first transistor, a second transistor, an amplifier and a resistor. The first terminal of the first transistor is used to receive the first reference voltage. The second terminal of the first transistor is electrically coupled to the first node. The control terminal of the first transistor is used to receive the first reference voltage. The first terminal of the second transistor is electrically coupled to the first node. The second terminal of the second transistor is used to receive the second reference voltage. The control terminal of the second transistor is used to receive the input voltage. The amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically coupled to the first node, and the second input terminal is used to receive the second reference voltage. One end of the resistor is electrically coupled to the first input terminal of the amplifier. The other end of the resistor is electrically coupled to the output end of the amplifier. The invention also discloses a control method of the signal reading circuit and a pulse detector having the signal reading circuit.

Description

Signal reading circuit and its control method and pulse detector

technical field

The present invention relates to a signal reading circuit and a control method thereof, in particular to a signal reading circuit of a sensing element and a control method thereof, and a pulse detector having the signal reading circuit.

Background technique

With the signal reading circuit, analog signals such as optical signals, thermal signals, or biomedical signals can be appropriately gain or compensated for subsequent analysis and processing by the user. The analog signal can even be properly sampled to form a discrete signal or a digital signal, so as to facilitate the user to perform digital signal processing.

On the system, the performance of each block circuit is often regarded as consistent with the standard specification. However, in actual circuits, the components of each part of the circuit will often deteriorate to varying degrees according to their physical characteristics in extreme environments or after a long period of operation, causing circuit parameters to drift and affecting circuit performance. Taking the signal reading circuit as an example, the on-resistance value or threshold voltage value of the transistors in the circuit often deviates from the originally designed preset value, causing the output of the signal reading circuit to be inaccurate and causing errors in subsequent processing and analysis.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a signal reading circuit and a control method thereof, so as to overcome the problem that the output of the signal reading circuit is misaligned due to parameter drift caused by transistor deterioration.

In order to achieve the above object, the present invention provides a signal reading circuit, the signal reading circuit includes a first transistor, a second transistor, an amplifier and a resistor. The first end of the first transistor is used for receiving the first reference voltage. The second end of the first transistor is electrically coupled to the first node. The control terminal of the first transistor is used for receiving the first reference voltage. The first end of the second transistor is electrically coupled to the first node. The second terminal of the second transistor is used for receiving the second reference voltage. The control end of the second transistor is used for receiving the input voltage. The amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically coupled to the first node. The second input terminal is used for receiving the second reference voltage. One end of the resistor is electrically coupled to the first input end of the amplifier. The other end of the resistor is electrically coupled to the output end of the amplifier.

In order to better achieve the above objects, the present invention also provides a control method of a signal reading circuit, and the control method of the signal reading circuit is suitable for a signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input terminal, a second input terminal and an output terminal. One end of the first transistor is electrically coupled to the first input end, and the other end is used for receiving the first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is used for receiving the second reference voltage. Both ends of the resistor are electrically coupled to the first input end and the output end, respectively. The control method includes operating the first transistor and the second transistor in the linear region. And let the current value of the current flowing through the resistor be the difference between the on-current of the first transistor and the on-current of the second transistor. And, let the voltage across both ends of the first transistor be equal to the voltage across both ends of the second transistor. The voltage level of the output terminal of the amplifier is related to the resistance value of the resistor and the current flowing through the resistor.

In order to better achieve the above object, the present invention also provides a pulse detector, which includes:

A plurality of detection modules, each of the detection modules includes:

A signal reading circuit as above; and

A sensing unit is electrically coupled to the signal reading circuit, and the sensing unit is used for generating the input voltage according to a pulse of a living body.

The technical effect of the present invention is:

To sum up the above, the signal reading circuit and the control method of the present invention use the current subtraction method to reduce the influence of the electrical variation of the element on the signal readout value of the sensing element. In this way, even if the parameters of the components in the signal reading circuit are out of alignment, the signal reading circuit can still avoid being affected by the inaccurate parameters, and can still output accurate reading values, which successfully overcomes the influence of the component parameter inaccuracy on the signal reading. Take the problem of circuit accuracy.

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

Description of drawings

1 is a schematic circuit diagram of a signal reading circuit according to a first embodiment of the present invention;

2 is a schematic circuit diagram of a signal reading circuit according to a second embodiment of the present invention;

3 is a schematic circuit diagram of a signal reading circuit according to a third embodiment of the present invention;

4 is a schematic circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention;

5 is a schematic circuit diagram of a signal reading circuit according to a fifth embodiment of the present invention;

6 is a schematic circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention;

7 is a schematic circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention;

8 is a schematic circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention;

9 is a schematic circuit diagram of a subtraction module according to an embodiment of the present invention;

10 is a schematic flowchart of a control method of a signal reading circuit according to an embodiment of the present invention;

11 is a schematic diagram of a pulse detector according to an embodiment of the present invention;

FIG. 12 is a functional block diagram of one of the detection units of the pulse detector according to an embodiment of the present invention.

where the reference number

1～8 Signal reading circuit

72, 82 The first sampling module

74, 84 Second sampling module

96 Subtraction Module

962 buffer unit

964 Subtraction Unit

C1, C2 capacitors

CK first clock signal

IR, IR’, IT1, IT2, IT1’, IT2’ Current

N1 first node

Nin1 first input terminal

Nin2 second input

Nout output

OP, OPS1, OPS2 amplifiers

R, RS1~RS4 resistance

SW1, SW2 sampling switch

T1, T1' first transistor

T2, T2' second transistor

T3, T3' third transistor

T4, T4' Fourth transistor

TS1 first sampling transistor

TS2 second sampling transistor

TS3 third sampling transistor

TS4 fourth sampling transistor

V1 first reference voltage

V2 Second reference voltage

Vref1 first reference voltage

Vref2 Second reference voltage

Vref3 third reference voltage

Vref4 Fourth reference voltage

Vin input voltage

Vout, Vout’ output voltage

XCK second clock signal

Detailed ways

Below in conjunction with accompanying drawing, structure principle and working principle of the present invention are described in detail:

The detailed features and advantages of the present invention are described in detail below in the embodiments, and the content is sufficient to enable those skilled in the art to understand the technical content of the present invention and implement accordingly, and according to the contents disclosed in this specification, claims and drawings, Objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples further illustrate the point of the present invention in detail, but do not limit the scope of the present invention in any point of view.

Please refer to FIG. 1 . FIG. 1 is a schematic circuit diagram of a signal reading circuit according to a first embodiment of the present invention. As shown in FIG. 1 , the signal reading circuit 1 includes a first transistor T1 , a second transistor T2 , an amplifier OP and a resistor R. The first end of the first transistor T1 is used for receiving the first reference voltage V1. The second end of the first transistor T1 is electrically coupled to the first node N1. The control terminal of the first transistor T1 is used for receiving the first reference voltage Vref1. The first end of the second transistor T2 is electrically coupled to the first node N1. The second terminal of the second transistor T2 is used for receiving the second reference voltage V2. The control terminal of the second transistor T2 is used for receiving the input voltage Vin. The amplifier OP has a first input terminal Nin1, a second input terminal Nin2 and an output terminal Nout. The first input terminal Nin1 is electrically coupled to the first node N1. The second input terminal Nin2 is used for receiving the second reference voltage Vref2. One end of the resistor R is electrically coupled to the first input end Nin1 of the amplifier OP. The other end of the resistor R is electrically coupled to the output end Nout of the amplifier OP. The first reference voltage V1 is, for example, a relatively high voltage level, and the second reference voltage V2 is, for example, a relatively low voltage level. In one embodiment, the first reference voltage V1 is the voltage VDD in the system, the second reference voltage V2 is the voltage VSS in the system, the voltage VDD is a high-level reference voltage, and the voltage VSS is a low-level reference voltage, but the Not limited to this. In this embodiment, the first transistor T1 and the second transistor T2 are N-type metal oxide semiconductor transistors (Metal Oxide Semiconductor Field-Effect Transistor, MOSFET), but not limited thereto.

The first transistor T1 is selectively turned on under the control of the first reference voltage Vref1. The second transistor T2 is selectively turned on under the control of the input voltage Vin. According to the virtual short characteristic of the amplifier OP, the voltage level of the first input terminal Nin1 of the amplifier OP is substantially equal to the voltage level of the second input terminal Nin2, so that the voltage level of the first node N1 is equal to the second reference voltage Vref2. In addition, the voltage level of the output node Nout is the difference between the voltage level of the first input terminal Nin1 and the voltage level of the second input terminal Nin2 amplified by the amplifier OP, and the voltage level of the output node Nout is related to the voltage level of the amplifier OP. gain value. The relevant characteristics of the amplifier OP are known to those skilled in the art, and will not be repeated here. When the amplifier OP has a high open-loop gain, the current value of the current IR flowing through the resistor R1 is approximately the difference between the current IT1 flowing through the first transistor T1 and the current IT2 flowing through the second transistor T2.

In one embodiment, the first transistor T1 and the second transistor T2 are operated in the linear region (Triode Mode), so the current IT1 and the current IT2 are as follows:

VDS1 in the formula (1) is the voltage across the drain terminal and the source terminal of the first transistor T1. VDS2 in the formula (2) is the voltage across the drain terminal and the source terminal of the second transistor T2. In equations (1) and (2), Vth represents the threshold voltage value of the first transistor T1 and the second transistor T2, μn represents the carrier mobility of the first transistor T1 and the second transistor T2, Cox represents the unit capacitance of the gate oxide layers of the first transistor T1 and the second transistor T2, It represents the channel width to length ratio of the first transistor T1 and the second transistor T2. In this embodiment, the first transistor T1 and the second transistor T2 have substantially the same threshold voltage value Vth, substantially the same carrier mobility μn, substantially the same unit capacitance Cox of the gate oxide layer, and substantially the same channel width aspect ratio In practice, the above-mentioned parameter values can be adjusted freely by those skilled in the art after carefully reading this specification without departing from the spirit of the present invention, and are not limited to the above.

On the other hand, the voltage level of the second reference voltage Vref2 is set as the average value of the first reference voltage V1 and the second reference voltage V2, so that VDS1 in equation (1) is equal to VDS2 in equation (2). Here, VDS1 and VDS2 are replaced by VDS for the convenience of subsequent description. As mentioned above, due to the high input impedance characteristic of the amplifier OP, the current IR is the difference between the current IT1 and the current IT2. Based on the above conditions, the current IR is as follows:

According to equation (3), the current IR has nothing to do with the threshold voltages of the first transistor T1 and the second transistor T2.

Further, the output voltage Vout of the signal reading circuit 1 is expressed as follows:

Vout=Vref2-R×IR(4)

Therefore, the output voltage Vout of the signal reading circuit 1 is also independent of the threshold voltage values of the first transistor T1 and the second transistor T2. In other words, even if the first transistor T1 and the second transistor T2 are degraded and the threshold voltage values of the first transistor T1 and the second transistor T2 are shifted, the signal reading circuit 1 can generate a more accurate output voltage Vout according to the input voltage Vin , and the output voltage Vout can ideally not be affected by the offset threshold voltage value. In this embodiment, the output voltage Vout is related to the resistance value of the resistor R1, the current IR flowing through the resistor R1 and the second reference voltage Vref2.

Please refer to FIG. 2 , which is a schematic circuit diagram of a signal reading circuit according to a second embodiment of the present invention. Different from the embodiment shown in FIG. 1 , the signal reading circuit 2 also has a sampling switch SW1 and a sampling switch SW2 . Two ends of the sampling switch SW1 are electrically coupled to the first input end Nin1 and the output end Nout of the amplifier OP, respectively. One end of the sampling switch SW2 is electrically coupled to one end of the first transistor T1 and the second transistor T2 electrically coupled, and the other end of the sampling switch SW2 is electrically coupled to the first input end Nin1 of the amplifier OP. The sampling switch SW1 is controlled by the second clock signal XCK, and the sampling switch SW2 is controlled by the first clock signal CK.

Under such a circuit structure and signal timing, when the first clock signal CK is at a low voltage level, the sampling switch SW1 is turned on and the sampling switch SW2 is not turned on, and the output voltage Vout of the signal reading circuit 2 is the same as the second reference voltage Vref2. When the first clock signal CK is at a low voltage level, the sampling switch SW1 is turned off and the sampling switch SW2 is turned on, and the output voltage Vout of the signal reading circuit 2 is the same as the aforementioned formula (4). Thereby, sampling can be performed according to the adjusted input voltage Vin. The sampling switch SW1 and the sampling switch SW2 are, for example, bi-polar junction transistors (BJTs), thin film transistors, metal-oxide-semiconductor transistors, or switch circuits composed of multiple elements, which are not limited herein.

Please refer to FIG. 3 , which is a schematic circuit diagram of a signal reading circuit according to a third embodiment of the present invention. Compared with the embodiment shown in FIG. 2 , the signal reading circuit 3 further includes a third transistor T3 and a fourth transistor T4 . The first end of the third transistor T3 is used for receiving the first reference voltage V1. The second end of the third transistor T3 is electrically coupled to the first end of the first transistor T1. The control terminal of the third transistor T3 is used for receiving the third reference voltage Vref3. The first end of the fourth transistor T4 is electrically coupled to the second end of the second transistor T2. The second terminal of the fourth transistor T4 is electrically coupled to the second reference voltage V2. The control terminal of the fourth transistor T4 is used for receiving the fourth reference voltage Vref4. In a similar way, the first transistor T1 and the third transistor T3 are connected in series, and the second transistor T2 and the fourth transistor T4 are connected in series. Those skilled in the art can understand that the signal reading circuit can be provided with more transistors connected in series with each other, and the number of transistors is not limited to this example.

Please refer to FIG. 4 , FIG. 5 and FIG. 6 . FIG. 4 is a schematic circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention, and FIG. 5 is a signal reading circuit according to a fifth embodiment of the present invention. A schematic circuit diagram of a circuit, FIG. 6 is a schematic circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention. The embodiment corresponding to FIG. 4 is similar to the embodiment corresponding to FIG. 2 , and the embodiment corresponding to FIG. 5 and FIG. 6 is similar to the embodiment corresponding to FIG. 3 . The difference is that in the embodiment corresponding to FIG. 4 , the first transistor T1' is a P-type metal oxide semiconductor transistor. In the embodiment corresponding to FIG. 5 , the first transistor T1' and the third transistor T3' are P-type metal-oxide-semiconductor transistors. In the embodiment corresponding to FIG. 6 , the first transistor T1' to the fourth transistor T4' are P-type metal oxide semiconductor transistors. With the embodiments shown in FIG. 1 to FIG. 6 , the signal reading circuit of the present application can be applied to different processes while maintaining the core spirit, which increases the practical versatility. The above is only an example, and is not actually limited thereto.

Please refer to FIG. 7 , which is a schematic circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention. In the embodiment corresponding to FIG. 7 , compared with the embodiment shown in FIG. 1 , the signal reading circuit 7 further includes a sampling switch SW1 , a first sampling module 72 and a second sampling module 74 . Two ends of the sampling switch SW1 are electrically coupled to the first input end Nin1 of the amplifier OP and the output end Nout of the amplifier OP, respectively. The sampling switch SW1 selectively turns on the first input terminal Nin1 to the output terminal Nout according to the second clock signal XCK.

The first sampling module 72 has a first sampling transistor TS1 and a second sampling transistor TS2. The second sampling module 74 has a third sampling transistor TS3 and a fourth sampling transistor TS4. The first terminal of the first sampling transistor TS1 is used for receiving the first reference voltage Vref1. The second terminal of the first sampling transistor TS1 is electrically coupled to the control terminal of the first transistor T1. The control terminal of the first sampling transistor TS1 is used for receiving the first clock signal CK. The first terminal of the second sampling transistor TS2 is electrically coupled to the control terminal of the first transistor T1. The second terminal of the second sampling transistor TS2 is used for receiving the second reference voltage Vref2. The control terminal of the second sampling transistor TS2 is used for receiving the second clock signal XCK.

The second sampling module 74 has a third sampling transistor TS3 and a fourth sampling transistor TS4. The first terminal of the third sampling transistor TS3 is used for receiving the input voltage Vin. The second terminal of the third sampling transistor TS3 is electrically coupled to the control terminal of the second transistor T2. The control terminal of the third sampling transistor TS3 is used for receiving the first clock signal CK. The first terminal of the fourth sampling transistor TS4 is electrically coupled to the control terminal of the first transistor T1. The second end of the fourth sampling transistor TS4 is used for receiving the second reference voltage V2. The control terminal of the fourth sampling transistor TS4 is used for receiving the second clock signal XCK.

Under such a circuit structure and signal timing, when the first clock signal CK is at a low voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are turned off, the second sampling transistor TS2 and the fourth sampling transistor TS4 It is turned on with the sampling switch SW1. At this time, the second reference voltage Vref2 is supplied to the control terminal of the first transistor T1, and the second reference voltage V2 is supplied to the control terminal of the second transistor T2. The voltage level of the control terminal of the first transistor T1 is similar to the voltage level of the first node N1, and the first transistor T1 is not turned on. The voltage level of the control terminal of the second transistor T2 is similar to the voltage level of the second terminal of the second transistor T2, and the second transistor T2 is not turned on. By means of the second sampling transistor T2 and the fourth sampling transistor T4, the voltage level of the control terminal of the first transistor T1 and the voltage level of the control terminal of the second transistor T2 can be stabilized, and the first transistor T1 and the second transistor T2 are ensured at the same time. When the first clock signal CK is at a low voltage level, it is not turned on.

When the first clock signal CK is at a high voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are turned on, and the second sampling transistor TS2 , the fourth sampling transistor TS4 and the sampling switch SW1 are turned off. At this time, the first reference voltage Vref1 is supplied to the control terminal of the first transistor T1, and the input voltage Vin is supplied to the control terminal of the second transistor T2. Correspondingly, the current IT1' flowing through the first transistor T1 and the current IT2' flowing through the second transistor T2 can be expressed as the following two equations respectively:

The parameters in equations (5) and (6) are as described above, and will not be repeated here. However, ΔV is used to refer to the voltage difference caused by the on-resistance of the first sampling transistor TS1 and the on-resistance of the third sampling transistor TS3 . Similarly, in this embodiment, the voltage difference caused by the on-resistance of the first sampling transistor TS1 and the voltage difference caused by the on-resistance of the third sampling transistor TS3 are substantially the same, but not limited thereto. At this time, the current IR' is also expressed as formula (7):

In other words, the current IR' is independent of the on-resistances of the first sampling transistor TS1 and the third sampling transistor TS3, and the current IR' is independent of the threshold voltages of the first transistor T1 and the second transistor T2. As mentioned above, the output voltage Vout is related to the resistance value of the resistor R1, the current IR flowing through the resistor R1 and the second reference voltage Vref2, so the output voltage Vout has nothing to do with the first sampling transistor TS1 and the third sampling transistor TS3. and the threshold voltage of the first transistor T1 and the second transistor T2.

In the embodiment corresponding to FIG. 7 , the signal reading circuit 7 also has a capacitor C1 and a capacitor C2. The capacitor C1 is electrically coupled to the second end of the first sampling transistor TS1 and the first end of the second sampling transistor TS2 . The capacitor C2 is electrically coupled to the second end of the third sampling transistor TS3 and the first end of the fourth sampling transistor TS4 . The capacitors C1 and C2 are used for voltage stabilization and filtering to prevent the voltage level of the control terminal of the first transistor T1 and the voltage level of the control terminal of the second transistor T2 from being disturbed by noise. In one embodiment, the capacitance values of the capacitor C1 and the capacitor C2 are the same, but not limited thereto.

Please refer to FIG. 8 . FIG. 8 is a schematic circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention. The embodiment shown in FIG. 8 is similar to the embodiment corresponding to FIG. 7 , except that each transistor in FIG. 8 is a P-type metal oxide semiconductor transistor, and each voltage is adjusted accordingly. The relevant details can be inferred by those skilled in the art after reading this specification, and will not be repeated here. The embodiment shown in FIG. 8 has similar effects as the embodiment corresponding to FIG. 7 , and provides another implementation manner in the process.

On the other hand, as shown in equation (4), the output voltage Vout actually has an offset equal to the second reference voltage Vref2, so that the output voltage Vout cannot be directly the input voltage Vin through the gain. In practice, the signal reading circuit provided by the present invention may further have a subtraction module to eliminate the offset of the output voltage Vout. Please also refer to FIG. 9 . FIG. 9 is a schematic circuit diagram of a subtraction module according to an embodiment of the present invention. The subtraction module 96 has a buffer unit 962 and a subtraction unit 964 . The input end of the buffer unit 962 is used for receiving the aforementioned output voltage Vout, and the output end of the buffer unit 962 is electrically coupled to the input end of the subtraction unit 964 . The buffer unit 962 has an amplifier OPS1. The subtraction unit 964 has resistors RS1-RS4 and an amplifier OPS2. The non-inverting input terminal of the amplifier OPS1 is electrically coupled to the output terminal of the amplifier OPS2 to form a voltage follower, and the amplifier OPS2 is electrically coupled to the resistors RS1-RS4 to form a voltage subtractor. One end of the voltage subtractor is the input end of the subtracting unit 964, and the other end of the voltage subtractor is used to receive the second reference voltage Vref2. In this embodiment, the resistance values of the resistors RS1 to RS4 are the same as each other. Therefore, according to equation (4) and the subtraction module 96 shown in FIG. 9 , the subtraction module 96 generates the output voltage Vout' according to the output voltage Vout and the second reference voltage Vref2. Among them, the output voltage Vout' is expressed as follows:

Vout′=R×IR(8)

That is, by means of the subtraction module 96, the output voltage Vout' no longer has the offset as the output voltage Vout has. In another embodiment, the other end of the subtraction module is used for receiving a time-varying signal, for example. The frequency and waveform of the time-varying signal are the same as the aforementioned first clock signal CK, and its amplitude can be amplified or reduced according to actual needs. In this way, in addition to making the output voltage Vout' no longer have the offset associated with the second reference voltage Vref2, the dynamic range of the back-end processing can also be improved.

According to the above, the present invention also provides a pulse sensor. Please refer to FIG. 11 , which is a schematic diagram of a pulse detector according to an embodiment of the present invention. The pulse detector 20 has a plurality of detection modules. In this embodiment, the detection modules 202a-202p arranged in an array are taken as an example for description. However, the number and arrangement of each detection module in the pulse detector should not be limited by the example.

Please refer to FIG. 12 to further describe the pulse detector. FIG. 12 is a functional block diagram of one of the detection units of the pulse detector according to an embodiment of the present invention. FIG. 12 is formed according to the detection module 202a in FIG. 11 . As shown in FIG. 12 , the detection module 202a has a sensing unit 2022a and a signal reading circuit 2024a.

The sensing unit 2022a is electrically coupled to the signal reading circuit 2024a. In one embodiment, the sensing unit 2022a is, for example, a piezoelectric sensor, and the sensing unit 2022a is used to generate a corresponding piezoelectric signal according to the pulse of the living body as the aforementioned input signal. The piezoelectric sensor 30 has, for example, a piezoelectric film made of polyvinylidene (PVDF) material, but is not limited thereto.

The signal reading circuit 2024a is, for example, the signal reading circuit described in any one of FIGS. 1 to 9 . The relevant action details are as described above, and will not be repeated here. In this embodiment, the detection module 202a further has a modulation unit 2026a. The modulation unit 2026a is electrically coupled to the signal reading circuit 2024a. The modulation unit 2026a is used for generating a modulation signal corresponding to the specification of the subsequent circuit according to the output signal of the signal reading circuit 2024a for the subsequent circuit to use. Although the modulation unit is an optional design, each detection module does not necessarily have a modulation unit.

As mentioned above, the present invention also provides a control method for a signal reading circuit. Please refer to FIG. 10 for description. FIG. 10 is a schematic flowchart of a control method for a signal reading circuit according to an embodiment of the present invention. . The control method of the signal reading circuit shown in FIG. 10 is suitable for the signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input terminal, a second input terminal and an output terminal. One end of the first transistor is electrically coupled to the first input end, and the other end is used for receiving the first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is used for receiving the second reference voltage. Both ends of the resistor are electrically coupled to the first input end and the output end, respectively. In the control method, in step S101, the first transistor and the second transistor are operated in the linear region. In step S103 , the current value of the current flowing through the resistor is set to be the difference between the on-current of the first transistor and the on-current of the second transistor. In step S105 , the voltage across both ends of the first transistor is set equal to the voltage across both ends of the second transistor. The voltage level of the output terminal of the amplifier is related to the resistance value of the resistor and the current flowing through the resistor. It should be noted that, the above-mentioned steps S103 and S105 are not necessarily in order.

In one embodiment, in the step of making the voltage across the two ends of the first transistor equal to the voltage across the second transistor, a second reference voltage is provided to the second input terminal, and the second reference voltage is the first reference The average value of the voltage and the second reference voltage.

To sum up the above, the present invention provides a signal reading circuit and a control method thereof, which utilizes the current subtraction method to reduce the influence of the electrical variation of the element on the signal readout value of the sensing element. In this way, even if the component parameters in the signal reading circuit are out of alignment due to practical conditions, the signal reading circuit can still avoid being affected by the parameter inaccuracy, and can still output accurate readings, successfully overcoming the component parameter inaccuracies. problems that affect the accuracy of the signal reading circuit.

Of course, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (9)

1. a signal reading circuit, is characterized in that, comprises: a first transistor, a first end of the first transistor is used for receiving a first reference voltage, a second end of the first transistor is electrically coupled to a first node, a control end of the first transistor is used for to receive a first reference voltage; a second transistor, a first end of the second transistor is electrically coupled to the first node, a second end of the second transistor is used for receiving a second reference voltage, a control end of the second transistor is used for to receive an input voltage; an amplifier having a first input terminal, a second input terminal and an output terminal, the first input terminal is electrically coupled to the first node, and the second input terminal is used for receiving a second reference voltage; and a resistor, one end is electrically coupled to the first input end of the amplifier, and the other end is electrically coupled to the output end of the amplifier; Wherein, the first transistor and the second transistor operate in the linear region; the voltage value of the second reference voltage is the average value of the first reference voltage and the second reference voltage; the amplifier has a high open-loop gain, flowing through The current value of the current of the resistor is the difference between the on-current of the first transistor and the on-current of the second transistor. 2 . The signal reading circuit of claim 1 , wherein the voltage level of the output terminal of the amplifier is related to the resistance value of the resistor, the current flowing through the resistor and the second reference voltage. 3 . 3 . The signal reading circuit of claim 1 , wherein the channel width to length ratio of the first transistor is the same as the channel width to length ratio of the second transistor. 4 . 4. The signal reading circuit of claim 1, further comprising: a third transistor, a first end of the third transistor is used to receive the first reference voltage, a second end of the third transistor is electrically coupled to the first end of the first transistor, and a second end of the third transistor is electrically coupled to the first end of the first transistor; a control terminal for receiving a third reference voltage; and a fourth transistor, a first end of the fourth transistor is electrically coupled to the second end of the second transistor, a second end of the fourth transistor is electrically coupled to the second reference voltage, the fourth transistor A control terminal of the is used for receiving a fourth reference voltage. 5. The signal reading circuit according to any one of claims 1 to 4, further comprising: A first sampling module, comprising: a first sampling transistor, a first end of the first sampling transistor is used for receiving the first reference voltage, a second end of the first sampling transistor is electrically coupled to the control end of the first transistor, the first sampling transistor A control terminal of a sampling transistor is used for receiving a first clock signal; and a second sampling transistor, a first end of the second sampling transistor is electrically coupled to the control end of the first transistor, a second end of the second sampling transistor is used for receiving the second reference voltage, the first A control terminal of the two sampling transistors is used for receiving a second clock signal, and the second clock signal is inverse to the first clock signal; and A second sampling module, including: a third sampling transistor, a first end of the third sampling transistor is used for receiving the input voltage, a second end of the third sampling transistor is electrically coupled to the control end of the second transistor, the third sampling transistor a control end of the transistor is used for receiving the first clock signal; and a fourth sampling transistor, a first end of the fourth sampling transistor is electrically coupled to the control end of the first transistor, a second end of the fourth sampling transistor is used for receiving the second reference voltage, the first A control terminal of the four sampling transistors is used for receiving the second clock signal; a sampling switch, two ends of the sampling switch are respectively electrically coupled to the first input terminal of the amplifier and the output terminal of the amplifier, the sampling switch selectively selects the first input terminal according to the second clock signal connected to this output. 6 . The signal reading circuit of claim 1 , further comprising a subtraction module, an input end of the subtraction module is electrically coupled to the output end of the amplifier, and an output signal of the subtraction module is associated with the The resistance of a resistor and the current flowing through that resistor. 7. A control method for a signal reading circuit, which is suitable for a signal reading circuit, wherein the signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier, and the amplifier has a a first input end, a second input end and an output end, one end of the first transistor is electrically coupled to the first input end, the other end is used to receive a first reference voltage, and one end of the second transistor is electrically The first input end is coupled to the other end for receiving a second reference voltage. Two ends of the resistor are electrically coupled to the first input end and the output end respectively. The control method includes: operating the first transistor and the second transistor in a linear region; Let the current value of the current flowing through the resistor be the difference between the on-current of the first transistor and the on-current of the second transistor; and making the voltage across both ends of the first transistor equal to the voltage across both ends of the second transistor; Wherein, the voltage level of the output terminal of the amplifier is related to the resistance value of the resistor and the current flowing through the resistor. 8 . The control method of claim 7 , wherein the step of making the voltage across both ends of the first transistor equal to the voltage across the second transistor comprises providing a second reference voltage. 9 . To the second input terminal, the second reference voltage is an average value of the first reference voltage and the second reference voltage. 9. A pulse detector, characterized in that, comprising: A plurality of detection modules, each of the detection modules includes: The signal reading circuit of any one of claims 1 to 6; and A sensing unit is electrically coupled to the signal reading circuit, and the sensing unit is used for generating the input voltage according to a pulse of a living body.