CN106411311B - Output circuit - Google Patents

Abstract

The present invention discloses an output circuit, comprising: an output switch, including a gate, a drain and a well, the drain of the output switch being coupled to an external I/O bus; a well control circuit, having a well coupled to the well of the output switch, to maintain a well voltage of the output switch not lower than the larger of a first voltage and a second voltage; a gate control circuit, coupled to the gate and the drain of the output switch and coupled to the external I/O bus, the gate control circuit being able to cut off the output switch to prevent current from flowing through the output switch from the external I/O bus in the following situations: an operating voltage of the output circuit is not applied to the output switch; and a bus voltage from an external device is present on the external I/O bus.

Description

output circuit

technical field

The present invention relates to an output buffer circuit for an integrated semiconductor circuit device, and more particularly to an output buffer circuit that prevents current backflow when the device is powered off.

Background technique

Output buffer circuits are usually implemented in semiconductor integrated circuits, such as memory circuits and logic circuits, to transmit and amplify signals to the input buffer circuits of another device. A chip as used here may also be called a semiconductor integrated circuit. The chips can share an external I/O bus through which the chips can communicate with each other through corresponding input and output buffer circuits coupled to the I/O bus.

FIG. 1 shows a block diagram of a conventional system 100 in which chip A 102 and chip B 104 share an external I/O bus. Chip A 102 and chip B 104 include output buffer circuits 106 and 108, respectively, and input buffer circuits 110 and 112, respectively. The output buffer circuit 106 of the chip A 102 includes a pMOS transistor 114 and an nMOS transistor 116 . The pMOS transistor 114 includes a pull-up (Pull-Up, PU) gate 118 , a drain 120 , a source 122 and a well 123 . The well 123 is coupled to the source 122 , and the source 122 receives the voltage VDD. The nMOS transistor 116 includes a pull-down (Pull-Down, PD) gate 124 , a drain 126 and a source 128 . The drain 126 of the nMOS transistor 116 is coupled to the source 120 of the pMOS transistor 114 . The input buffer circuit 110 of chip A 102 includes a pMOS transistor 130 and an nMOS transistor 132 . The pMOS transistor 130 includes a gate 134 , a drain 136 , a source 138 and a well 139 . The well 139 is coupled to the source 138 , and the source 138 is coupled to receive the voltage VDD. The nMOS transistor 132 includes a gate 140 , a drain 142 and a source 148 . The drain 142 of the nMOS transistor 132 is coupled to the drain 136 of the pMOS transistor 130 .

The output buffer circuit 108 of chip B 104 includes a pMOS transistor 150 and an nMOS transistor 152 . The pMOS transistor includes a PU gate 154 , a drain 156 , a source 158 and a well 159 . The well 159 is coupled to the source 158 , and the source 158 receives the voltage VDD. The nMOS transistor 152 includes a PD gate 160 , a drain 162 and a source 164 coupled to the drain 156 of the pMOS transistor 150 . The input buffer circuit 112 of chip B 104 includes a pMOS transistor 166 and an nMOS transistor 168 . The pMOS transistor 166 includes a gate 170 , a drain 172 , a source 174 and a well 175 . The well 175 is coupled to the source 174 , and the source 174 receives the voltage VDD. nMOS transistor 168 includes a gate 176 , a drain 178 and a source 180 . Drain 178 of nMOS transistor 168 is coupled to drain 172 of pMOS transistor 166 .

The external I/O bus 182 couples chip A 102 and chip B 104 . For the chip A 102 , the external I/O bus 182 is coupled to the drain 120 of the pMOS transistor 114 , the drain 126 of the nMOS transistor 116 , the gate 134 of the pMOS transistor 130 and the gate 140 of the nMOS transistor 132 . For chip B 104 , external I/O bus 182 is coupled to drain 156 of pMOS transistor 150 , drain 162 of nMOS transistor 152 , gate 170 of pMOS transistor 166 , and gate 176 of nMOS transistor 168 . Data signals from chip A 102 can be transmitted to chip B 104 by coupling external I/O bus 182 between chip A 102 and chip B 104 . In more detail, the output buffer circuit 106 of the chip A 102 transmits the data signal to the input buffer circuit 112 of the chip B 104 via the I/O bus 182 . Similarly, data signals may be sent from chip B 104 to chip A 102 .

Contents of the invention

According to a first aspect of the present invention, an output circuit is provided, comprising: an output switch including a gate, a drain and a well, the drain of the output switch being coupled to an external I/O bus; a well control circuit having a well coupled to the well of the output switch to maintain a well voltage of the output switch not lower than the greater of a first voltage and a second voltage; and a gate control a circuit, coupled to the gate and the drain of the output switch, and coupled to the external I/O bus, the gate control circuit is operated to turn off the output switch to avoid current flow from the outside when The I/O bus flows through the output switch: an operating voltage of the output circuit is not applied to the output switch; and a bus voltage from an external device is present on the external I/O bus.

According to a second aspect of the present invention, an output circuit is provided, comprising: an output switch operated to supply a data signal to an external I/O bus when activated, the output switch comprising a gate, a drain and a well; a well control circuit having a well coupled to the well of the output switch to maintain a well voltage of the output switch not lower than the larger of a first voltage and a second voltage, wherein The first voltage is an operating voltage of the output circuit minus D1; the second voltage is the bus voltage of the external I/O bus minus D2; and D1 and D2 are each positive or zero; an input switch, coupled connected to the gate of the output switch; a gate control circuit coupled to the gate and the drain of the output switch, the external I/O bus and the input switch; a bias generator coupled to to a gate of the input switch to maintain a bias greater than the sum of the operating voltage of the output circuit and a threshold voltage of the input switch; and a voltage discharge circuit coupled to the bias generator, the well The control circuit and the gate of the input switch discharge the bias voltage generated by the bias voltage generator when the operating voltage of the output circuit decreases.

According to a third aspect of the present invention, an output circuit is provided, comprising: an output switch operated to supply a data signal to an external I/O bus when activated, the output switch comprising a gate, a source/drain and a well; a well control circuit having a well coupled to the well of the output switch to maintain a well voltage of the output switch not lower than the larger of a first voltage and a second voltage , wherein the first voltage is an operating voltage of the output circuit minus D1; the second voltage is the bus voltage of the external I/O bus minus D2; and D1 and D2 are each positive values or zero; an input switch , coupled between the source/drain of the output switch and the external I/O bus, and operated to disconnect (disconnect) from the I/O bus and the output switch; a bias generator, coupled to a gate of the input switch to maintain a bias greater than the sum of the operating voltage of the output circuit and a threshold voltage of the input switch; and a voltage discharge circuit coupled to the bias generator, the well The control circuit and the gate of the input switch discharge the bias voltage generated by the bias voltage generator when the operating voltage of the output circuit decreases.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

The accompanying drawings are incorporated by reference as a part of the description, and illustrate embodiments according to the present invention, and are shared with the description to explain the principle of the present invention.

FIG. 1 is a block diagram of a conventional system in which multiple chips share a common external I/O bus.

FIG. 2A is a schematic diagram illustrating the architecture of an output buffer circuit according to an exemplary embodiment of the present invention.

FIG. 2B is a schematic diagram illustrating another architecture of an output buffer circuit implemented in a VIO mode according to an exemplary embodiment of the present invention.

FIG. 3 shows an exemplary circuit diagram of the first embodiment.

4A-4C are circuit diagrams of a well control device according to an exemplary embodiment of the present invention.

5A-5B are schematic diagrams illustrating another structure of a well control device according to an exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating an architecture according to an exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an architecture according to an exemplary embodiment of the present invention.

【Symbol Description】

100: system

102: Chip A

104: Chip B

106, 108, 200, 300, 600, 700: output buffer circuit

110, 112: Input buffer circuit

114, 130, 150, 166, 202, 302, 320, 322, 402, 439, 440, 602, 608, 620, 640, 702, 730: pMOS transistors

116, 132, 152, 168, 318, 404, 422, 424, 606, 638, 706, 728: nMOS transistors

118, 124, 134, 140, 154, 160, 170, 176, 208, 308, 319, 324, 332, 406, 414, 426, 432, 442, 450, 614, 624, 630, 642, 648, 712, 720, 732, 738: gate

120, 126, 136, 142, 156, 162, 172, 178, 210, 310, 321, 326, 334, 408, 416, 428, 434, 444, 452, 616, 626, 632, 644, 650, 714, 722, 734, 740: drain

122, 128, 138, 148, 158, 164, 174, 180, 212, 312, 323, 328, 336, 410, 418, 430, 436, 446, 454, 618, 628, 634, 646, 652, 716, 724, 736, 742: source

123, 139, 159, 175, 214, 313, 330, 338, 412, 420, 438, 448, 456, 636, 654, 718, 744: Well electrode

182, 215, 622, 726: External I/O bus

204, 304: gate control circuit

206, 306, 400A, 400B, 400C, 500A, 500B, 500C, 604, 704: well control circuit

216: Level shift circuit

225: Internal circuit

610, 708: Bias generator

612, 710: voltage discharge circuit

Vout, VDD, VIO: voltage

Data: data signal

Detailed ways

The details will be described with reference to the embodiments of the present invention, and these implementation examples will be described with reference to the drawings. The following description will refer to the accompanying drawings, and the same or similar elements in the drawings represent the same or similar elements unless otherwise defined. The implementations presented in the following description of the exemplary embodiments do not represent all implementations of the invention, but merely represent examples of systems and methods implemented in accordance with relevant aspects of the invention within the scope of the appended claims.

In an exemplary embodiment, an output buffer circuit including an output switch, a gate control circuit and a well control circuit is provided. The output buffer circuit is coupled to the external I/O bus via the output switch.

In more detail, in an exemplary embodiment, the output buffer circuit prevents current from flowing through the output switch from the external I/O bus when the circuit operating voltage is not applied to the output switch. The output buffer circuit is such that the bus voltage from the external I/O bus is coupled to the sink control circuit and the gate control circuit.

FIG. 2A is a schematic structural diagram of an output buffer circuit 200 according to an exemplary embodiment of the present invention. The output buffer circuit 200 includes an output switch such as a pMOS transistor 202 , a gate control circuit 204 and a well control circuit 206 . Gate control circuit 204 is coupled to internal circuit 225 for receiving data. The pMOS transistor 202 includes a gate 208 , a drain 210 , a source 212 and a well 214 . The drain 210 is coupled to the gate control circuit 204 . The drain 210 is further coupled to an external I/O bus 215 . I/O bus 215 has a bus voltage. The source 212 receives the circuit operating voltage VDD (ie, the internal voltage 225 and the operating voltage of the output buffer circuit 200 ). The gate 208 of the pMOS transistor 202 is coupled to the gate control circuit 204 . Well control circuit 206 is coupled to well 214 of pMOS transistor 202 .

FIG. 2B is a schematic diagram of another architecture of the output buffer circuit 220 according to an exemplary embodiment of the present invention. The components of the output buffer circuit 220 are the same as those of the output buffer circuit 200 and denoted by the same reference numerals, and the description of the components will not be repeated. The source 212 of the output buffer circuit 220 receives the voltage VIO. The voltage VIO is the operating voltage of the output buffer circuit 220 . The voltage VIO may be different from the internal circuit operating voltage VDD. The source 212 is coupled to the gate control circuit 204 and the level shift circuit 216 . The level shift circuit 216 receives a data signal whose level is the internal circuit operating voltage VDD, and changes the level from VDD to VIO, so that VIO provides the data signal to the external I/O bus 215 . In this manner, the internal circuit operating voltage VDD is isolated from the output buffer operating voltage VIO. In one embodiment, the level shift circuit 216 lowers the voltage of the data signal, so as to reduce the power consumption of the external I/O bus 215 when VDD>VIO.

The embodiment circuits described with respect to FIGS. 3-7 have a structure similar to that of the output buffer circuit of FIG. 2A, wherein only the internal circuit operating voltage VDD is provided to the pMOS transistor 202, the gate control circuit 204, and the well control of the output buffer circuit 200. circuit 206. However, those with ordinary knowledge should know that the embodiment circuits described in FIG. 3-FIG. 7 have a structure similar to FIG. VIO (not VDD) is provided to the pMOS transistor 202 of the output buffer circuit 220 , the gate control circuit 204 and the well control circuit 206 . When the circuit of the embodiment described in relation to FIGS. 3-7 has a structure similar to that of FIG. 2B , when the device is powered off (that is, the circuit is off mode), VDD and VIO are also off.

The driving source of the external I/O bus 215 is changed dynamically. Sometimes external I/O bus 215 is driven by the output of pMOS transistor 202 . Sometimes the external I/O bus 215 is driven by the output of other chips coupled to the external I/O bus 215 . Sometimes the external I/O bus 215 is not driven, that is, the external I/O bus 215 is floating. Regardless of the driving source of the external I/O bus 215, there is always a finite voltage level on the external I/O bus 215, such as zero voltage. Accordingly, the voltage appearing on the external I/O bus 215 is referred to as the "bus voltage."

Referring again to FIG. 2A , when the power of the chip is turned off, the output buffer circuit 200 prevents current from flowing back into the chip from the external I/O bus 215 . The drain 210 of the pMOS transistor 202 is coupled to the external I/O bus 215 to provide the bus voltage of the external I/O bus 215 to the drain 210 of the pMOS transistor 202 . The external I/O bus 215 is further coupled to the gate control circuit 204 . The gate control circuit 204 operates corresponding to the bus voltage of the external I/O bus 215 . An exemplary architecture of the gate control circuit 204 is as follows. The well control circuit 206 coupled to the well 214 of the pMOS transistor 202 maintains the voltage on the well 214 not lower than the larger of a first voltage and a second voltage, so as to avoid leakage in the pMOS transistor 202 current. The first voltage is the internal circuit operating voltage VDD minus D1, wherein D1 is a positive value or zero. The second voltage is the bus voltage of the external I/O bus 215 minus D2, each of which is a positive value or zero. D1 and D2 can be equal or different. In this architecture, the pMOS transistor 202 can be completely turned off when the chip is powered off (VDD=0) and when the chip is powered on (VDD=1.8V). Therefore, turning off pMOS transistor 202 and maintaining the well voltage prevents current backflow.

Please refer to FIG. 2B, the output buffer circuit 220 is configured to prevent current from flowing back into the chip from the external I/O bus 215 when the chip power is turned off, and is configured to convert the circuit operating voltage VDD of the chip to the voltage of the external I/O bus 215 . The drain 210 of the pMOS transistor 202 is coupled to the external I/O bus 215 to provide the bus voltage of the external I/O bus 215 to the drain 210 of the pMOS transistor 202 . External I/O bus 215 is coupled to gate control circuit 204 . The gate control circuit 204 operates corresponding to the bus voltage of the external I/O bus 215 . The well control circuit 206 coupled to the well 214 of the pMOS transistor 202 maintains the voltage on the well 214 not lower than the larger of a second voltage and a third voltage, so as to avoid leakage in the pMOS transistor 202 current. The second voltage is the bus voltage of the external I/O bus 215 minus D2, each of which is a positive value or zero. The third voltage is the operating voltage VIO of the output buffer circuit 220 minus D3, wherein D3 is a positive value or zero. D2 and D3 can be equal or different. Moreover, the level shift circuit 216 of the output buffer circuit 220 reduces the voltage of the data signal VDD to the I/O voltage of VIO, thereby reducing the voltage of the external I/O bus 215 . In this way, the output buffer circuit 220 prevents the current backflow of the external I/O bus 215 in the power-off mode of the chip, and isolates the internal circuit operating voltage VDD from the output buffer operating voltage VIO in the power-on mode.

FIG. 3 is an exemplary circuit diagram of the output buffer circuit 300 of the foregoing embodiment. The output buffer circuit 300 is an exemplary implementation of the output buffer circuit 200 . Please refer to FIG. 3 , the output buffer circuit 300 includes an output switch (such as a pMOS transistor MP 302 ), a gate control circuit 304 and a well control circuit 306, respectively corresponding to the pMOS transistor 202 and the gate control circuit of the output buffer circuit 200 ( FIG. 2A ). 204 and well control circuit 206. The pMOS transistor MP 302 includes a pull-up (Pull-Up, PU) gate 308 , a drain 310 , a source 312 and a well 313 . The drain 310 is coupled to an external I/O bus 314 having a bus voltage Vout. The PU gate 308 , drain 310 , source 312 and well 313 of the pMOS transistor MP 302 correspond to the gate 208 , drain 210 , source 212 and well 214 of the pMOS transistor 202 ( FIG. 2A ), respectively. Source 312 is coupled to receive VDD. Gate control circuit 304 is coupled to PU gate 308 of pMOS transistor 302 . The gate control circuit 304 includes input switches such as nMOS transistor MN1 318 coupled to the PU gate 308 of the pMOS transistor MP 302 , a first pMOS transistor MP1 320 and a second pMOS transistor MP2 322 to prevent current backflow into the chip. The nMOS transistor MN1 318 includes a gate 319 , a drain 321 and a source 323 . Gate 319 is coupled to receive VDD. The drain 321 is coupled to receive a data signal 0 or 1. The first pMOS transistor MP1 320 includes a gate 324 , a drain 326 , a source 328 and a well 330 . The gate 324 is coupled to receive the bus voltage Vout. The drain 326 is coupled to the PU gate 308 of the pMOS transistor MP 302 and the source 323 of the nMOS transistor MN1 318 . The source 328 of the first pMOS transistor MP1 320 is coupled to receive the voltage VDD. The second pMOS transistor 322 includes a gate 332 , a drain 334 , a source 336 and a well 338 . Gate 332 is coupled to receive VDD. The drain 334 is coupled to the PU gate 308 of the pMOS transistor MP 302 , the drain 326 of the first pMOS transistor MP1 320 and the source 323 of the nMOS transistor MN1 318 . The source 336 of the second pMOS transistor MP2 322 is coupled to receive the bus voltage Vout. The wells 330 and 338 of the first pMOS transistor MP1 320 and the second pMOS transistor MP2 322 are coupled together. The well control circuit 306 is coupled to the well 313 of the pMOS transistor MP 302 . The well electrodes 330 and 338 of the first pMOS transistor MP1 and the second pMOS transistor MP2 are also coupled to the well control circuit 306 . In some embodiments, the well 313 of the pMOS transistor 302 , the wells 330 and 338 of the first pMOS transistor MP1 320 and the second pMOS transistor MP2 322 can be respectively coupled to different well control circuits. An exemplary architecture of the well control circuit 306 is described below.

As shown in FIGS. 2A and 2B , the well control circuit 206 is coupled to control the voltage of the well 214 of the pMOS transistor 202 . In FIG. 3 , the well control circuit is coupled to control the voltages of the wells 313 , 330 and 338 of the pMOS transistors 302 , 320 and 322 , respectively. 4A-4C illustrate circuit diagrams of well control circuits 400A- 400C according to exemplary embodiments of the present invention. In FIGS. 4A-4C , each exemplary well control circuit is configured to control the well voltage so that the pMOS transistor coupled to the well control circuit can be effectively turned off at an appropriate time. In order to effectively turn off each pMOS transistor, when the gate of the pMOS transistor receives voltage VDD, the well voltage should not be less than the maximum value of the voltage on the drain and source. If the well voltage is less than the maximum value of the voltage on the drain and source, the pMOS transistor may generate a leakage current.

Referring to FIG. 4A , well control circuit 400A includes a first pMOS transistor 402 and a second pMOS transistor 404 coupled in series. The first pMOS transistor 402 includes a gate 406 , a drain 408 , a source 410 and a well 412 . The second pMOS transistor 404 includes a gate 414 , a drain 416 , a source 418 and a well 420 . The gate 406 of the first pMOS transistor 402 is coupled to receive the bus voltage Vout. The drain 408 of the first pMOS transistor 402 is coupled to the drain 416 of the second pMOS transistor 404 . The source 410 is coupled to receive VDD. The well 412 of the first pMOS transistor 402 is coupled to the well 420 of the second pMOS transistor 404 and is coupled to the drains 408 and 416 . The gate 414 of the second pMOS transistor 404 is coupled to receive VDD, and the source 418 is coupled to receive Vout.

For convenience of illustration, when VDD is high, VDD is provided as a circuit operating voltage (eg, 1.8V or 3.0V). When VDD is low, VDD is supplied as 0V. Similarly, when Vout is high, Vout is provided as VDD or VIO, respectively representing the circuit operating voltage or a reduced voltage as provided by the level shift circuit 216 . When Vout is low, Vout is provided as 0V.

During operation of the well control circuit 400A, when VDD and Vout are high, the voltage on the wells 412 and 420 is VDD-Vdiode, where Vdiode is the PN formed in the source and drain of each pMOS transistor 402, 404 junction turn-on voltage. When Vout is low and VDD is high, the voltage on wells 412 and 420 is VDD. When Vout is high and VDD is low, the voltage on wells 412 and 420 is Vout. When both Vout and VDD are low, the voltage on wells 412 and 420 is floating ground, which is high relative to low Vout and low VDD. With this structure, when VDD≠Vout, the pMOS transistors (such as pMOS transistors 202 , 302 , 320 , 322 ) coupled to the well control circuit will not leak current, so they can be completely turned off. When VDD=Vout, the well voltage is VDD-Vdiode, which is sufficient to suppress the leakage current.

Referring to FIG. 4B , the well control circuit 400B includes a first nMOS transistor 422 and a second nMOS transistor 424 coupled in series. The first nMOS transistor 422 includes a gate 426 , a drain 428 and a source 430 . The second nMOS transistor 424 includes a gate 432 , a drain 434 and a source 436 . Gates 426 and 432 are coupled to drains 428 and 434, respectively. Sources 430 and 436 are coupled together and to well 438 . The drain 428 of the first nMOS transistor 422 is coupled to receive VDD, and the drain 434 of the second nMOS transistor 424 is coupled to receive Vout.

During operation of the well control circuit 400B, when VDD and Vout are high, the voltage on the well 438 is equal to the maximum of the following two voltages: VDD minus the threshold voltage Vt422 of the first nMOS transistor 422 (ie, VDD−Vt422) and VDD minus the threshold voltage Vt424 of the second nMOS transistor 424 (ie, VDD−Vt424). A voltage drop Vtn across the first nMOS transistor 422 or the second nMOS transistor 424 occurs when current flows through the first nMOS transistor 422 or the second nMOS transistor 424 and results in a well voltage VDD-Vtn. When Vout is low and VDD is high, the voltage on the sources 430 and 436 is VDD-Vt422. When Vout is high and VDD is low, the voltage on the sources 430 and 436 is VDD-Vt424. When both Vout and VDD are low, the voltage on sources 430 and 436 is floating ground, which is higher than the low Vout and low VDD. With this structure, when VDD=Vout, the pMOS transistors (such as pMOS transistors 202 , 302 , 320 , 322 ) coupled to the well control circuit will not leak current, so they can be completely turned off. When VDD≠Vout, the well voltage is VDD-Vtn, which is sufficient to suppress the leakage current.

Referring to FIG. 4C , the well control circuit 400C includes a first pMOS transistor 439 and a second pMOS transistor 440 coupled in series. The first pMOS transistor 439 includes a gate 442 , a drain 444 , a source 446 and a well 448 . The second pMOS transistor 440 includes a gate 450 , a drain 452 , a source 454 and a well 456 . The drain 444 of the first pMOS transistor 439 is coupled to the drain 452 of the second pMOS transistor 440 . The gates 442 and 450 of the first pMOS transistor 439 and the second pMOS transistor 440 are coupled to each other, to the drains 444 and 452 and to the wells 448 and 456 . The source 446 of the first pMOS transistor 439 is coupled to receive VDD, and the source 454 of the second pMOS transistor 440 is coupled to receive Vout.

During operation of well control circuit 400C, when VDD and Vout are high, the voltage on drains 428 and 434 is the higher of VDD-Vtp or VDD-Vdiode. When the current flows through the first pMOS transistor 439 or the second pMOS transistor 440 , the well voltage is VDD−Vtp, and a voltage drop Vtp equal to the first pMOS transistor 439 and the second pMOS transistor 440 is generated. When Vout is low and VDD is high, the voltage on drains 444 and 454 is the higher of VDD-Vtp or VDD-Vdiode. When Vout is high and VDD is low, the voltage on sources 444 and 454 is the higher of VDD-Vtp or VDD-Vdioe. When both Vout and VDD are low, the voltage on sources 444 and 454 is floating ground, which is high relative to low Vout and low VDD. With this structure, when VDD=Vout, the pMOS transistors (such as pMOS transistors 202 , 302 , 320 , 322 ) coupled to the well control circuit will not leak current, so they can be completely turned off. When VDD≠Vout, the well voltage is VDD-Vtp or VDD-Vdiode, which is sufficient to suppress the leakage current.

5A-5B illustrate various alternative architecture diagrams of the well control circuit 206 or 306 according to an exemplary embodiment of the present invention. 5A and 5B illustrate a plurality of well control circuits 400A, 400B and 400C combined in parallel. Configuring such well control circuits 400A, 400B, and 400C in parallel (FIGS. 4A-4C) allows control of the well voltage when VDD=Vout and VDD≠Vout. The well control circuit 500A of FIG. 5A is formed by coupling the well control circuits 400A and 400B in parallel. The drain 428 of the first nMOS transistor 422 is coupled to the source 410 of the first pMOS transistor 402 . The drain 434 of the second nMOS transistor 424 is coupled to the source 418 of the second pMOS transistor 524 . The source 430 of the first nMOS transistor 422 is coupled to the source 436 of the second nMOS transistor 424, and the source 436 is coupled to the drain 408 and the well 412 of the first pMOS transistor 402 and the drain of the second pMOS transistor 404. electrode 416 and well electrode 420 .

FIG. 5B shows a well control circuit 500B formed by coupling well control circuits 400A, 400B, and 400C in parallel. The drain 428 of the first nMOS transistor 422 is coupled to the source 410 of the first pMOS transistor 402 . The drain 434 of the second nMOS transistor 424 is coupled to the source 418 of the second pMOS transistor 404 . The source 430 of the first nMOS transistor 422 is coupled to the source 436 of the second nMOS transistor 424, and the source 436 is coupled to the drain 408 and the well 412 of the first pMOS transistor 402 and the drain of the second pMOS transistor 404. pole 416 and well pole 420 . The gate 422 of the first pMOS transistor 439 and the gate 450 of the second pMOS transistor 440 are respectively coupled to the wells 448 and 456 and the drains 444 and 452 of the first pMOS transistor 439 and the second pMOS transistor 440, the first The source 430 of the nMOS transistor 422 and the source 436 of the second nMOS transistor 424 are coupled to the drains 408 and 416 and the wells 412 and 420 of the first pMOS transistor 402 and the second pMOS transistor 404 . The source 446 of the first pMOS transistor 439 is coupled to the drain 428 of the first nMOS transistor 422 and the source 410 of the first pMOS transistor 402 . The source 454 of the second pMOS transistor 402 is coupled to the drain 434 of the second nMOS transistor 424 and the source 418 of the second pMOS transistor 404 .

Please refer to FIG. 3 again. In an exemplary embodiment, the output buffer circuit 300 is configured to prevent current from flowing back into the chip when the chip power is turned off. A number of different operational examples of the output buffer circuit 300 are considered below. In the first example, the circuit operating voltage VDD is 1.8V, the data signal (Data) is 1.8V, and the voltage Vout on the I/O bus 314 is 1.8V. In this example, when the bus voltage Vout on the external I/O bus 314 is 1.8V, the well control circuit 306 maintains a voltage of 1.8V between the well 313 of the pMOS transistor MP 302 and the first pMOS transistor of the gate control circuit 304. Wells 330 and 338 of MP1 320 and second pMOS transistor MP2 322 respectively. Both the first pMOS transistor MP1 320 and the second pMOS transistor MP2 322 are turned off, so that neither VDD nor Vout provided on the sources 328 and 336 respectively can be applied to the drains 326 and 334 respectively. Therefore, neither VDD nor Vout on sources 328 and 336 can be applied to PU gate 308 . On the contrary, the gate PU 308 receives the data signal VDD minus the threshold voltage Vtn of the nMOS transistor MN1 318 , VDD−Vtn. Since VDD-Vtn is less than the larger of the circuit operating voltages VDD and Vout, the pMOS transistor MP 302 may have a leakage current. However, this leakage current terminates over time. Thus, the pMOS transistor MP 302 is turned off.

In the second example, the circuit operating voltage VDD is 1.8V, the data signal (Data) is 1.8V, and the voltage Vout on the I/O bus 314 is 0V. In this example, when the bus voltage Vout on the external I/O bus 314 is 0V, the first pMOS transistor MP1 320 is turned on because the voltage on the gate 324 is 0V, so that the PU gate 308 receives The voltage VDD of the source 328 of the transistor MP1 320 . The second pMOS transistor MP2 322 is turned off, so that the Vout on the source 336 cannot be sent to the source 334 and thus will not be received by the PU gate 308 of the pMOS transistor MP 302 . Therefore, after passing through the nMOS transistor MN1318, the voltage value of the data signal VDD will decrease the threshold voltage Vtn of the nMOS transistor 318 to become VDD-Vtn, and then be charged to VDD, because VDD is obtained from the first pMOS transistor MP1 320 Source 328 is received. When the PU gate 308 of the pMOS transistor 302 receives VDD, the pMOS transistor 302 is off.

In the third example, the circuit operating voltage VDD is 1.8V, the data signal (Data) is 0V, and the voltage Vout on the I/O bus 314 increases from 0V to 1.8V. In this example, when the voltage on I/O bus 314 is 0V, the voltage applied to PU gate 308 of pMOS transistor MP 302 is 0V. The second pMOS transistor MP2 322 is turned off. The first pMOS transistor MP1 320 is initially turned on when Vout is equal to 0V. In this way, the voltage VDD on the source 328 of the first pMOS transistor MP1 320 "conflicts" with the 0V of the data signal received by the nMOS transistor MN1 318 . However, compared with the nMOS transistor MN1 318 , the pMOS transistor MP1 320 is smaller in size and has a lower driving current to ensure that the voltage received by the PU gate 308 is the data signal 0V from the nMOS transistor MN1 318 . After Vout increases to 1.8V, the first pMOS transistor MP1 320 is turned off, and the voltage of 0V is received by the PU gate 308 , thereby turning on the pMOS transistor MP 302 . VDD on source 312 of pMOS transistor MP 302 is then applied to external I/O bus 314 .

Therefore, in the exemplary embodiment of FIG. 3, when VDD is 1.8V and the data signal is 1.8V, the pMOS transistor MP302 is turned off. When VDD is 1.8V and the data signal is 0V, the pMOS transistor MP 302 is turned on. In this way, when the chip starts up (VDD is 1.8V), the high data signal turns off the pMOS transistor MP 302 to avoid current backflow. Well control circuit 306 maintains well control that suppresses leakage current and allows such pMOS transistors to be turned off.

In the fourth example, the circuit operating voltage VDD is 0V and the voltage Vout on the I/O bus 314 is 1.8V. In this example, when the bus voltage Vout is 1.8V, the well 313 receives 1.8V of Vout from the well control circuit 306 . The respective wells 330 and 338 of the first and second pMOS transistors 320 and 322 of the gate control circuit 304 also receive 1.8V of Vout. The first pMOS transistor 320MP1 is off because its gate 324 receives 1.8V of Vout. The second pMOS transistor 322MP2 is turned on because its gate 332 receives VDD of 0V. The second pMOS transistor 322MP2 is larger than MP1 to provide a higher driving force. For example, MP1 has a larger width/length ratio than MP2. Thus, 1.8V from Vout of source 336 of pMOS transistor 322 is applied to PU gate 308 of pMOS transistor MP 302 . The 1.8V of Vout on PU gate 308 turns off pMOS transistor MP 302 , thus preventing current flow from external I/O bus 314 into output buffer circuit 300 .

In the fifth example, the circuit operating voltage VDD is 0V and the voltage Vout on the I/O bus 314 is 0V. In this example, VDD is equal to 0V when the bus voltage is 0V. Applying 0V of Vout to the gate 324 of the first pMOS transistor MP1 320 and 0V of VDD to the gate 332 of the second pMOS transistor MP2 322 turns on both transistors. The second pMOS transistor MP2 322 is large enough to allow the voltage on the PU gate 308 to track Vout. PU gate 308 receives VDD from source 328 and Vout from source 336 . In this example, the PU gate 308, drain 310, and source 312 of pMOS transistor MP 302 are at 0V. The well 313 is floating grounded above 0V. Therefore, the pMOS transistor MP 302 is turned off, preventing leakage current from flowing in the pMOS transistor MP 302 . Furthermore, the nMOS transistor MN1 318 avoids current backflow when the chip power is turned off, because the nMOS transistor MN1 318 will be turned off when VDD is low.

Therefore, in the exemplary embodiment of FIG. 3, when VDD is 0V and Vout is 1.8V, the pMOS transistor MP 302 is off. Similarly, when VDD is 0V and Vout is 0V, pMOS transistor MP 302 is off. In this way, when chip power is turned off, well control circuit 306 maintains the well voltage to suppress leakage current and allow such pMOS transistors to be turned off.

In an exemplary embodiment, as shown in FIG. 6 , the output buffer circuit 600 is configured to allow the data signal Data to reach the output switch 602 without voltage drop. 6, the output buffer circuit 600 includes an output switch such as a pMOS transistor MP 602, a well control circuit 604 and an input switch such as an nMOS transistor MN1 606, a gate control circuit such as a pMOS transistor MP2 608, a bias generator 610 and a voltage discharge circuit 612. The pMOS transistor MP 602 includes a PU gate 614 , a drain 616 , a source 618 and a well 620 . The drain 616 of the pMOS transistor MP 602 is coupled to the external I/O bus 622 . The source 618 is coupled to the circuit operating voltage VDD. The well control circuit 604 is coupled to the well 620 of the pMOS transistor MP 602 . The well control circuit 604 can be configured in any of the ways described in FIGS. 4A-4C and FIGS. 5A and 5B .

The nMOS transistor MN1 606 is coupled to the PU gate 614 of the pMOS transistor MP 602 . nMOS transistor MN1606 includes a gate 624 , a drain 626 and a source 628 . The pMOS transistor MP2 608 includes a gate 630 , a drain 632 , a source 634 and a well 636 . The drain 632 of pMOS transistor MP2 608 is coupled to the PU gate 614 of pMOS transistor MP 602 and to the source 628 of nMOS transistor MNI 606 . The source 634 is coupled to receive Vout. The well 636 of the pMOS transistor MP2 608 is coupled to the well control circuit 604 . In some embodiments, the well 636 of pMOS transistor MP2 608 and the well 620 of pMOS transistor 602 are coupled to different well control circuits.

The voltage discharge circuit 612 includes an nMOS transistor 638 and a pMOS transistor 640 coupled in series. The nMOS transistor 638 includes a gate 642 , a drain 644 and a source 646 . Gate 642 is coupled to external I/O bus 622 and receives Vout. The pMOS transistor 640 includes a gate 648 , a drain 650 , a source 652 and a well 654 . The gate 648 and the drain 650 are coupled to receive the circuit operating voltage VDD. The voltage discharge circuit 612 is coupled to the bias generator 610 and the gate 624 of the nMOS transistor MN1 606 . The well 620 of pMOS transistor MP 602 , the well 636 of pMOS transistor MP2 608 and the well 654 of pMOS transistor 640 are coupled to the well control circuit 604 . In some embodiments, the well 620 of pMOS transistor MP 602 , the well 636 of pMOS transistor MP2 608 and the well 654 of pMOS transistor 640 are coupled to different control circuits.

In an exemplary embodiment, the output buffer circuit 600 ( FIG. 6 ) prevents current from flowing back into the chip when the chip is powered off. Please refer to Figure 6, when the chip power is off, VDD is 0V. When the bus voltage Vout on the external I/O bus 622 is 1.8V, Vout is applied to the drain 616 of the pMOS transistor 602 and coupled to the source 634 of the pMOS transistor MP2 608 . VDD on the gate of pMOS transistor MP2 608 is 0V, making pMOS transistor MP2 608 on, while Vout on source 634 is applied to PU gate 614 of pMOS transistor 602 . Vout applied to PU gate 614 turns off pMOS transistor MP602. Therefore, current from the external I/O bus 622 does not flow into the external buffer circuit. Similarly, when the bus voltage Vout on the external I/O bus 622 is low (eg, 0V) and the chip power is off, VDD is equal to 0V. Applying 0V of VDD to the gate 630 turns on the pMOS transistor MP2 608 such that the voltage on the source 634 of the pMOS transistor MP2 608 is applied to the PU gate 614 of the pMOS transistor MP 602 . In this example, the voltage on the gate 614, drain 616 and source 618 of pMOS transistor MP 602 is equal to 0V. The well 620 is a floating ground. Since the voltage on the well 620 (floating ground) is received from the well control circuit 604 and is higher than the voltages on the drain 616 and source 618 , leakage current is prevented from flowing through the pMOS transistor 602 . Therefore, current does not flow into the output buffer circuit 600 from the external I/O bus 622 . Furthermore, when VDD is 0V, the nMOS transistor MN1 606 is turned off, so the nMOS transistor MN1 606 prevents current from flowing back into the chip when the chip power is turned off. On the other hand, when VDD is 1.8V, the bias voltage Vbias supplied by the bias generator 610 is greater than the sum of VDD and the threshold voltage Vtn of the nMOS transistor 606 . This allows the full scale data signal (VDD) to pass through the nMOS transistor without voltage drop. The voltage discharge circuit 612 includes an nMOS transistor 638 and a pMOS transistor 640 coupled in series to discharge the voltage when there is a voltage drop in the bias voltage generator 610 due to the chip being powered off.

In an exemplary embodiment, as shown in FIG. 7 , the output buffer circuit 700 is configured to prevent the current from the external I/O bus from flowing into the chip. Referring to FIG. 7 , the output buffer circuit 700 includes an output switch such as a pMOS transistor MP702 , a well control circuit 704 , an input switch such as an nMOS transistor MN2 706 , a bias voltage generator 708 and a voltage discharge circuit 710 . The pMOS transistor MP 702 includes a PU gate 712 , a drain 714 , a source 716 and a well 718 . The source 716 is coupled to receive the circuit operating voltage VDD. Well control circuit 704 is coupled to well 718 . The well control circuit 704 can be configured in any of the ways described in FIGS. 4A-4C and FIGS. 5A and 5B . nMOS transistor MN2 706 includes a gate 720 , a drain 722 and a source 724 . The nMOS transistor MN2 706 is coupled between the drain 714 of the pMOS transistor MP 702 and the external I/O bus 726 . The bias voltage generator 708 is coupled to the gate 720 of the nMOS transistor MN2 706 . The voltage discharge circuit 710 includes an nMOS transistor 728 and a pMOS transistor 730 coupled in series. The nMOS transistor 728 includes a gate 732 , a drain 734 and a source 736 . Gate 732 is coupled to external I/O bus 726 . The pMOS transistor 730 includes a gate 738 , a drain 740 , a source 742 and a well 744 . Gate 738 and source 742 receive VDD. Well 744 of pMOS transistor 730 and well 718 of pMOS transistor 702 are coupled to well control circuit 704 . The well control circuit 704 can be configured in any of the ways described in FIGS. 4A-4C and FIGS. 5A and 5B . The voltage discharge circuit 710 is coupled to the bias voltage generator 708 and the gate 720 of the nMOS transistor 706 .

In an exemplary embodiment, the output buffer circuit 700 is configured to prevent current from flowing into the chip when the chip is powered off. Please refer to Figure 7, when the chip power is off, VDD is 0V. Well control circuit 704 avoids leakage current in such nMOS transistors and allows pMOS transistors 702, 730 to be turned off. When the bus voltage Vout on the external I/O bus 726 is 1.8V, the bus voltage Vout is applied to the source 724 of the nMOS transistor MN2 706 . When the chip power is turned off, the bias voltage generator 708 is turned off. Therefore, the voltage on the gate 720 of nMOS transistor MN2 706 is 0V, so nMOS transistor 706MN2 is off. Therefore, current from the external I/O bus 726 does not flow into the output buffer circuit. When the voltage on the external I/O bus 726 is 0V and the chip power is off, the nMOS transistor MN2 706 is turned off. Therefore, current does not flow into the output buffer circuit 700 from the external I/O bus 726 . When the chip is powered on (VDD is 1.8V), the bias voltage Vbias supplied by the bias generator 708 is greater than the sum of VDD and the threshold voltage Vtn of the nMOS transistor 706 . This allows the full scale voltage from external I/O bus 726 to pass through nMOS transistor MN2 706 without voltage drop. The voltage discharge circuit 710 includes an nMOS transistor 728 and a pMOS transistor 730 coupled in series to discharge the voltage when the voltage drop occurs in the bias voltage generator 708 due to the chip being powered off.

For those who have ordinary knowledge of the embodiments of the present invention, other embodiments can be conceived with reference to the implementation content of the present invention disclosed herein. This application is intended to cover any variations, uses, and adaptations of the invention pertaining to the general principles, including departures from the invention which come to be known or customary in the art. The specification and examples are only for exemplary illustrations, and the protection scope of the present invention should be defined by the scope of the appended claims.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (15)

1. a kind of output circuit, comprising:

One output switch, comprising a grid, a drain electrode and a trap pole, it is total that the drain electrode of output switch is coupled to one exterior I/O Line；

One trap control circuit, has a first transistor, a second transistor and a trap pole, which is coupled to output switch The trap pole, the greater with the trap voltage that maintains the output to switch not less than a first voltage and a second voltage；And

One gate control circuit, is coupled to the grid and the drain electrode of output switch, and is coupled to the exterior I/O bus, the grid Control circuit is operable to end output switch, to avoid electric current to flow through the output from exterior I/O bus in following situations Switch:

One operation voltage of the output circuit is not applied to output switch；And

A bus voltage from an external device (ED) occurs from the exterior I/O bus.

2. output circuit according to claim 1, wherein output switch is to be configured to one data signals of supply extremely should Exterior I/O bus；

The first voltage is that an operation voltage of the output circuit subtracts D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

3. output circuit according to claim 1, in the trap control circuit,

The first transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain, one second Source/drain is to receive operation voltage and the trap pole of the output circuit；And

The second transistor coupled in series the first transistor, the second transistor have a grid to receive the output circuit Operation voltage, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole and this first and the second transistor These first source/drains, using the trap pole as the trap control circuit.

4. output circuit according to claim 1, in the trap control circuit,

The first transistor there is a grid with receive operation voltage, one first source/drain and one second source of the output circuit/ Drain electrode is coupled to the grid of the first transistor；

The second transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain is coupled to this The source/drain of the first transistor and one second source/drain are coupled to the grid of the second transistor；And

The trap pole of the trap control circuit be coupled to this first and the second transistor these first source/drains, using as this The trap pole of trap control circuit.

5. output circuit according to claim 1, in the trap control circuit,

The first transistor has a grid, one first source/drain, one second source/drain to receive the operation of the output circuit Voltage and a trap pole；And

The second transistor have a grid be coupled to the first transistor the grid and the first transistor first source/ Drain electrode, one first source/drain are coupled to the first drain electrode, one second source/drain of the first transistor to receive the exterior I/O The bus voltage of bus and a trap pole be coupled to the first transistor the trap pole, this first and the second transistor these One source/drain and this first and the second transistor these grids, using the trap pole as the trap control circuit.

6. a kind of output circuit, comprising:

One output switch, when Yu Qidong, are operable for answering a data signals to one exterior I/O bus, and the exterior I/O bus has One bus voltage, output switch include a grid, a drain electrode and a trap pole；

One trap control circuit is coupled to the trap pole of output switch with a trap pole, with the trap electricity for maintaining the output to switch The greater of pressure not less than a first voltage and a second voltage；

One input switch is coupled to the grid of output switch；

One grid control circuit, the grid and the drain electrode, the exterior I/O bus and the input for being coupled to output switch are opened It closes；

One bias generator is coupled to a grid of the input switch, to maintain a bias to be greater than an operation of the output circuit The sum of voltage and a threshold voltage of the input switch；And

One voltage discharge circuit is coupled to the grid of the bias generator, the trap control circuit and the input switch, at this When the operation voltage of output circuit reduces, discharge the bias caused by the bias generator.

7. output circuit according to claim 6, wherein the first voltage is that an operation voltage of the output circuit subtracts D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

8. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain, one second Source/drain is to receive operation voltage and the trap pole of the output circuit；And

One second transistor, the coupled in series the first transistor, the second transistor have a grid to receive the output circuit Operation voltage, one first source/drain be coupled to first source/drain of the first transistor, one second source/drain to receive The exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole and this first and second crystal These first source/drains of pipe, using the trap pole as the trap control circuit.

9. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor receives operation voltage, one first source/drain and one second of the output circuit with a grid Source/drain is coupled to the grid of the first transistor；

One second transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain is coupled to The source/drain of the first transistor and one second source/drain are coupled to the grid of the second transistor；And

One trap pole, be coupled to this first and the second transistor these first source/drains, using the trap as the trap control circuit Pole.

10. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor receives the operation of the output circuit with a grid, one first source/drain, one second source/drain Voltage and a trap pole；And

One second transistor, with a grid be coupled to the first transistor the grid and the first transistor this first Source/drain, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the external transistor the trap pole, this first and the second transistor These first source/drains and this first and the second transistor these grids, using the trap pole as the trap control circuit.

11. a kind of output circuit, comprising:

One output switch, when Yu Qidong, are operable for answering a data signals to one exterior I/O bus, and the exterior I/O bus has One bus voltage, output switch include a grid, a source/drain and a trap pole；

One trap control circuit is coupled to the trap pole of output switch with a trap pole, with the trap electricity for maintaining the output to switch The greater of pressure not less than a first voltage and a second voltage；

One input switch is coupled between source/drain and the exterior I/O bus of output switch, and operation is with from the I/O Bus and output switch disconnect；

One bias generator is coupled to a grid of the input switch, to maintain a bias to be greater than an operation of the output circuit The sum of voltage and a threshold voltage of the input switch；And

One voltage discharge circuit is coupled to the grid of the bias generator, the trap control circuit and the input switch, at this When the operation voltage of output circuit reduces, discharge the bias caused by the bias generator.

12. output circuit according to claim 11, wherein the first voltage is that an operation voltage of the output circuit subtracts Remove D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

13. output circuit according to claim 11, wherein the trap control circuit includes:

One the first transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain, one second Source/drain is to receive operation voltage and the trap pole of the output circuit；And

One second transistor, the coupled in series the first transistor, the second transistor have a grid to receive the output circuit Operation voltage, one first source/drain be coupled to first source/drain of the first transistor, one second source/drain to receive The exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole and this first and second crystal These first source/drains of pipe, using the trap pole as the trap control circuit.

14. output circuit according to claim 11, wherein the trap control circuit includes:

One the first transistor receives operation voltage, one first source/drain and one second of the output circuit with a grid Source/drain is coupled to the grid of the first transistor；

One second transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain is coupled to The source/drain of the first transistor and one second source/drain are coupled to the grid of the second transistor；And

One trap pole, be coupled to this first and the second transistor these first source/drains, using the trap as the trap control circuit Pole.

15. output circuit according to claim 11, wherein the trap control circuit includes:

One the first transistor receives the operation of the output circuit with a grid, one first source/drain, one second source/drain Voltage and a trap pole；And

One second transistor, with a grid be coupled to the first transistor the grid and the first transistor this first Source/drain, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole, this first and the second transistor These first source/drains and this first and the second transistor these grids, using the trap pole as the trap control circuit.