CN106409997A - LED chip and formation method thereof - Google Patents

Abstract

An LED chip and its forming method, the method includes: providing a first substrate, on the first substrate there is a front-end structure including a first semiconductor layer, an active layer and a second semiconductor layer from bottom to top, the front-end structure has a first The first area and the second area; forming a groove through the second semiconductor layer and the active layer in the first area; forming a connecting conductive layer on the top surface of the second semiconductor layer in the first area around the groove; forming a covering connecting conductive layer and a concave groove side wall and expose the first semiconductor layer at the bottom of the groove and the insulating layer on the top surface of the second semiconductor layer in the second region; perform bonding treatment to make the insulating layer, the first semiconductor layer at the bottom of the groove and the second region second The semiconductor layer is combined with the second substrate through the bonding body; then the first substrate is removed; the front-end structure of the second region and part of the first region is etched, corresponding to the exposed part of the bonding body and the connecting conductive layer; after connecting the conductive layer and An electrode layer is formed on the surface of the bonding body. The method can reduce the complexity of LED chip on-board chip packaging.

Description

LED chip and its forming method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to an LED chip and a forming method thereof.

Background technique

A light emitting diode (Light Emitting Diode, referred to as LED) is a semiconductor light emitting device. Light-emitting diodes have photoelectric properties such as low energy consumption, small size, long life, good stability, fast response, and stable emission wavelength. At present, light-emitting diodes are widely used in the fields of lighting, home appliances, display screens, and indicator lights.

The structure of the LED chip includes a positive structure, a flip structure and a vertical structure.

The light emitted by the active area of the front-mounted structure LED exits through the P-type GaN layer and the transparent electrode. However, there are two obvious disadvantages in front-mount LEDs: the current flows laterally through the N-type GaN layer, resulting in current congestion and high local heat generation, which limits the driving current; front-mount LEDs use sapphire substrates, which have poor thermal conductivity. Seriously hinder heat dissipation.

Flip-chip structure LEDs use eutectic bonding to weld large-size LED chips and silicon substrates together. The heat dissipation effect of the flip-chip LED has been greatly improved, but the current of the usual flip-chip LED still flows laterally through the N-type GaN layer, and the phenomenon of current crowding still exists.

The vertical structure LED can effectively solve the two shortcomings of the vertical structure LED. Specifically, the vertical structure LED uses a high thermal conductivity substrate, such as silicon, germanium or Cu to replace the sapphire substrate, which greatly improves the heat dissipation capability; the two electrodes of the vertical structure LED are respectively on both sides of the LED chip, through the N Type electrodes, so that almost all the current flows vertically through the LED chip, and the lateral current is very small, so it can effectively avoid the current crowding problem of the front-mounted structure LED.

However, the LED chips formed in the prior art increase the process complexity of chip-on-board (COB) packaging of the LED chips.

Contents of the invention

The problem to be solved by the present invention is to provide an LED chip and a forming method thereof, so as to reduce the process complexity of chip-on-board packaging of the LED chip.

In order to solve the above problems, the present invention provides a method for forming an LED chip, comprising: providing a first substrate with a front-end structure on the first substrate, and the front-end structure includes a first semiconductor layer and is located on the first semiconductor layer. The active layer on the active layer and the second semiconductor layer on the active layer, the front-end structure has a first region and a second region; a groove penetrating through the second semiconductor layer and the active layer is formed in the first region; The top surface of the first region and the second semiconductor layer around the groove forms a connecting conductive layer; an insulating layer covering the connecting conductive layer and the sidewall of the groove is formed, and the insulating layer exposes the first semiconductor layer and the second semiconductor layer at the bottom of the groove. The top surface of the second semiconductor layer in the region; performing the bonding process, so that the insulating layer, the first semiconductor layer at the bottom of the groove, and the second semiconductor layer in the second region are combined with the second substrate through the bonding body, and the bond The composite fills the groove and covers the insulating layer and the top surface of the second semiconductor layer in the second region; after performing bonding treatment, removing the first substrate; after removing the first substrate, etching part of the front-end structure of the first region, exposing part of the connecting conductive layer, etching the front-end structure of the second region, exposing part of the bonding body; forming electrode layers on the exposed connecting conductive layer surface and the bonding body surface respectively.

Optionally, the connecting conductive layer includes one or more stacked stacked layers, and the stacked stack includes a first material layer and a second material layer located on the surface of the first material layer, the first The material layer is located on the top surface of the second semiconductor layer in the first region around the groove.

Optionally, the material of the first material layer is TiW; the material of the second material layer is Pt or Ti.

Optionally, the method for performing the bonding treatment includes: forming a first bonding layer on the surface of the insulating layer, the surface of the first semiconductor layer at the bottom of the groove, and the top surface of the second semiconductor layer in the second region; providing a second substrate; forming a second bonding layer on the surface of the second substrate; bonding the first bonding layer and the second bonding layer so that the first bonding layer and the second bonding layer form the bond fit.

Optionally, the second substrate is an insulating and thermally conductive substrate, and the thermal conductivity of the insulating and thermally conductive substrate is above 45W/(m·K); or the second substrate is a conductive substrate; when the When the second substrate is a conductive substrate, the method for forming the LED chip further includes: during the bonding process, combining the bonding body with the second substrate through an isolation layer.

Optionally, the material of the insulating and heat-conducting substrate is SiC or AlN.

Optionally, it also includes: before forming the connecting conductive layer, forming a reflective layer on a part of the top surface of the second semiconductor layer in the first region around the groove; the connecting conductive layer covers the reflective layer and the reflective layer. The first region of the layer surrounds the top surface of the second semiconductor layer.

Optionally, it also includes: before forming the reflective layer, forming an ohmic contact layer on a part of the top surface of the second semiconductor layer in the first region around the groove, the conductivity of the ohmic contact layer is greater than that of the second semiconductor layer. The electrical conductivity of the layer is smaller than the electrical conductivity of the reflective layer; the reflective layer covers the ohmic contact layer.

Optionally, it also includes: after removing the first substrate and before etching the second region and part of the front-end structure of the first region, roughening the surface of the first semiconductor layer; etching the second After the front-end structure of the region and part of the first region, a passivation layer is formed on the surface of the front-end structure, the surface of the insulating layer, and the surface of a part of the bonding body that is partially exposed, and the passivation layer exposes a part of the surface of the connecting conductive layer; forming the After the passivation layer, the electrode layer is formed.

The present invention also provides an LED chip, comprising: a second substrate; a bonding body on the second substrate, the bonding body includes a base on the surface of the second substrate and a protrusion on the surface of the base; The insulating layer on the side wall and part of the surface of the substrate; the connecting conductive layer on the surface of part of the insulating layer, and the connecting conductive layer is located on the substrate; the second semiconductor layer on the part of the connecting conductive layer and the connecting conductive layer on the surface of the second semiconductor layer Active layer, the insulating layer of the protrusion and the protrusion sidewall runs through the second semiconductor layer and the active layer; The first semiconductor layer; the electrode layer respectively located on the exposed surface of the connecting conductive layer and the surface of the bonding body.

Optionally, the connecting conductive layer includes one or more laminated layer groups, the layer layer includes a second material layer and a first material layer located on the surface of the second material layer, the second material layer The material layer is located on part of the surface of the insulating layer, and the second material layer is located on the base.

Optionally, the material of the first material layer is TiW; the material of the second material layer is Pt or Ti.

Optionally, the second substrate is an insulating and thermally conductive substrate, and the thermal conductivity of the insulating and thermally conductive substrate is above 45W/(m·K); or the second substrate is a conductive substrate; when the When the second substrate is a conductive substrate, the LED chip further includes: an isolation layer between the second substrate and the bonding body.

Optionally, the material of the insulating and heat-conducting substrate is SiC or AlN.

Optionally, it further includes: a reflective layer located between the second semiconductor layer and the connecting conductive layer.

Optionally, it further includes: an ohmic contact layer located between the reflective layer and the second semiconductor layer, the electrical conductivity of the ohmic contact layer is greater than the electrical conductivity of the second semiconductor layer and lower than the electrical conductivity of the reflective layer.

Optionally, the material of the ohmic contact layer is a transparent conductive material.

Optionally, the transparent conductive material is indium tin oxide, fluorine-doped tin oxide or aluminum-doped zinc oxide.

Optionally, the material of the bonding body is any one or a combination of Au, Cu, In, Ti, Pt, Cr, Ge, Ni.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming the LED chip provided by the technical solution of the present invention, an insulating layer covering the connecting conductive layer and the sidewall of the groove is formed, and the insulating layer exposes the first semiconductor layer at the bottom of the groove and the second semiconductor layer in the second region. The top surface; after removing the first substrate and etching the second region and part of the front-end structure of the first region, a part of the bonding body and a part of the connecting conductive layer are respectively exposed; on the exposed connecting conductive layer surface and the bonding body surface respectively An electrode layer is formed for connection to an external voltage source. The electrode layer on the surface of the connecting conductive layer is electrically connected to the second semiconductor layer through the connecting conductive layer, the electrode layer on the surface of the bonding body is electrically connected to the first semiconductor layer through the bonding body, and the first semiconductor layer is electrically connected to the second semiconductor layer through the active layer . Therefore, the current in the LED chip flows sequentially through the electrode layer connected to the surface of the conductive layer, the connected conductive layer, the second semiconductor layer, the active layer, the first semiconductor layer, the bonding body, and the electrode layer on the surface of the bonding body. Since the external voltage source does not need to apply voltage to the first semiconductor layer through the second substrate and the bonding body, the current in the LED chip does not need to flow through the second substrate, and the first semiconductor layer does not need to pass through the bonding body and the second substrate. Make electrical connections. The material requirements for the second substrate are no longer limited to conductive materials, which is beneficial to reduce the process complexity of LED chip-on-chip packaging.

In the LED chip provided by the technical solution of the present invention, the insulating layer is located on the raised side wall and part of the substrate surface; the connecting conductive layer is located on part of the insulating layer surface, and the connecting conductive layer is located on the substrate, and the electrode layers are respectively located on the exposed connection The surface of the conductive layer and the surface of the bonding body, the electrode layer is used to connect to an external voltage source. The electrode layer on the surface of the connecting conductive layer is electrically connected to the second semiconductor layer through the connecting conductive layer, the electrode layer on the surface of the bonding body is electrically connected to the first semiconductor layer through the bonding body, and the first semiconductor layer is electrically connected to the second semiconductor layer through the active layer . Therefore, the current in the LED chip flows sequentially through the electrode layer connected to the surface of the conductive layer, the connected conductive layer, the second semiconductor layer, the active layer, the first semiconductor layer, the bonding body, and the electrode layer on the surface of the bonding body. Since the external voltage source does not need to apply voltage to the first semiconductor layer through the second substrate and the bonding body, the current in the LED chip does not need to flow through the second substrate, and the first semiconductor layer does not need to pass through the bonding body and the second substrate. Make electrical connections. The material requirements for the second substrate are no longer limited to conductive materials, which is beneficial to reduce the process complexity of LED chip-on-chip packaging.

Description of drawings

Fig. 1 is a structural schematic diagram of an LED chip;

2 to 16 are structural schematic diagrams of the LED chip formation process in an embodiment of the present invention.

detailed description

As mentioned in the background art, the electrical performance of LED chips formed in the prior art needs to be improved.

Fig. 1 is a structural diagram of an LED chip, the LED chip includes: a bonding substrate 100; a bonding layer 110 located on the bonding substrate 100; a first electrode layer 120 located on the bonding layer 110; The sidewall of the electrode layer 120, and the insulating layer 130 on the bonding layer 110; the first semiconductor layer 140 on the insulating layer 130, the active layer 150 on the first semiconductor layer 140, the first electrode layer 120 and The insulating layer 130 on the sidewall of the first electrode layer 120 runs through the first semiconductor layer 140 and the active layer 150; the second semiconductor layer 160 located on the active layer 150, the insulating layer 130 and the first electrode layer 120; The second semiconductor layer 160 , the active layer 150 and the second electrode layer 170 of the first electrode layer 120 are described above, and the second electrode layer 170 is electrically connected to the first semiconductor layer 140 .

However, the electrical performance of the above-mentioned LED chip is poor, and it is found through research that the reasons are:

The second electrode layer 170 is electrically connected to the first semiconductor layer 140 , and both ends of the first electrode layer 120 are electrically connected to the second semiconductor layer 160 and the bonding layer 110 respectively. Therefore, the current in the LED chip flows through the second electrode layer 170 , the first semiconductor layer 140 , the active layer 150 , the second semiconductor layer 160 , the first electrode layer 120 and the bonding layer 110 in sequence. When the LED chip works, the first electrode layer 120 needs to be electrically connected to the bonding substrate 100 through the bonding body 110 , so that the first electrode layer 120 can be electrically connected to an external voltage source applied on the bonding substrate 100 . Therefore, the material of the bonding substrate 100 needs to be a conductive material. As a result, the process complexity of chip-on-chip packaging of LED chips is increased. Specifically, when the material of the bonding substrate 100 needs to be a conductive material, solder joints need to be provided in the area where the bonding substrate 100 and the packaging substrate are in contact. , and the solder joints need to be electrically connected to the bus in the packaging substrate, so circuit wiring needs to be performed between the solder joints and the bus. As a result, the wiring complexity of the packaging substrate for the chip-on-chip packaging of the LED chip is increased.

On this basis, the present invention provides a method for forming an LED chip, comprising: providing a first substrate, on which there is a front-end structure, and the front-end structure includes a first semiconductor layer, located on the first semiconductor layer The active layer on the active layer and the second semiconductor layer on the active layer, the front-end structure has a first region and a second region; a groove penetrating through the second semiconductor layer and the active layer is formed in the first region; The top surface of the first region and the second semiconductor layer around the groove forms a connecting conductive layer; an insulating layer covering the connecting conductive layer and the sidewall of the groove is formed, and the insulating layer exposes the first semiconductor layer and the second semiconductor layer at the bottom of the groove. The top surface of the second semiconductor layer in the region; performing the bonding process, so that the insulating layer, the first semiconductor layer at the bottom of the groove, and the second semiconductor layer in the second region are combined with the second substrate through the bonding body, and the bond The composite fills the groove and covers the insulating layer and the top surface of the second semiconductor layer in the second region; after performing bonding treatment, removing the first substrate; after removing the first substrate, etching part of the front-end structure of the first region, exposing part of the connecting conductive layer, etching the front-end structure of the second region, exposing part of the bonding body; forming electrode layers on the exposed connecting conductive layer surface and the bonding body surface respectively.

In the method, an insulating layer covering the connecting conductive layer and the sidewall of the groove is formed, and the insulating layer exposes the first semiconductor layer at the bottom of the groove and the top surface of the second semiconductor layer in the second region; the first substrate is removed And after etching the front-end structure of the second area and part of the first area, a part of the bonding body and a part of the connecting conductive layer are respectively exposed; electrode layers are respectively formed on the exposed connecting conductive layer surface and the bonding body surface, and the electrode layer For connection to an external voltage source. The electrode layer on the surface of the connecting conductive layer is electrically connected to the second semiconductor layer through the connecting conductive layer, the electrode layer on the surface of the bonding body is electrically connected to the first semiconductor layer through the bonding body, and the first semiconductor layer is electrically connected to the second semiconductor layer through the active layer . Therefore, the current in the LED chip flows sequentially through the electrode layer connected to the surface of the conductive layer, the connected conductive layer, the second semiconductor layer, the active layer, the first semiconductor layer, the bonding body, and the electrode layer on the surface of the bonding body. Since the external voltage source does not need to apply voltage to the first semiconductor layer through the second substrate and the bonding body, the current in the LED chip does not need to flow through the second substrate, and the first semiconductor layer does not need to pass through the bonding body and the second substrate. Make electrical connections. The material requirements for the second substrate are no longer limited to conductive materials, which is beneficial to reduce the process complexity of LED chip-on-chip packaging.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 15 are schematic structural views of the LED chip formation process in an embodiment of the present invention.

Referring to FIG. 2 , a first substrate 200 is provided, and a front-end structure is provided on the first substrate 200, and the front-end structure includes a first semiconductor layer 201, an active layer 202 on the first semiconductor layer 201, and an active layer on the first semiconductor layer 201. The second semiconductor layer 203 on the source layer 202, the front-end structure has a first region and a second region.

In this embodiment, the material of the first substrate 200 is sapphire. In other embodiments, the material of the first substrate is gallium nitride, silicon, or silicon carbide.

The conductivity type of the first semiconductor layer 201 is opposite to that of the second semiconductor layer 203 .

In this embodiment, description is made by taking an example in which the conductivity type of the first semiconductor layer 201 is N type and the conductivity type of the second semiconductor layer 203 is P type.

In this embodiment, the material of the first semiconductor layer 201 is N-type GaN, and the material of the second semiconductor layer 203 is P-type GaN. In this embodiment, the active layer 202 is a quantum well layer. The function of the quantum well layer includes: improving the recombination efficiency of electrons and holes, so as to improve the luminous efficiency of the LED chip.

The quantum well layer is a multiple quantum well layer or a single quantum well layer.

The process of forming the first semiconductor layer 201 , the active layer 202 and the second semiconductor layer 203 includes an epitaxial growth process.

In this embodiment, a buffer layer is further formed between the first semiconductor layer 201 and the first substrate 200 . The material of the buffer layer includes undoped GaN. The function of the buffer layer includes: avoiding large distortion of the crystal lattice of the first semiconductor layer 201 . In other embodiments, no buffer layer is formed.

Referring to FIG. 3 and FIG. 4 together, FIG. 4 is a top view towards the second semiconductor layer 203 on the basis of FIG. 3 , and FIG. 3 is a cross-sectional view along the cutting line A-A1 in FIG. 4 , forming a penetrating second semiconductor layer in the first region. layer 203 and the groove 210 of the active layer 202 .

The method for forming the groove 210 includes: forming a patterned mask layer on the second semiconductor layer 203, the patterned mask layer defines the position of the groove 210; The second semiconductor layer 203 and the active layer 202 in the first region are etched using an anisotropic etching process until the first semiconductor layer 201 is exposed, thereby forming The groove 210 of the active layer 202 .

The number of the grooves 210 is one or more. In this embodiment, the number of the grooves 210 is 7 as an example for illustration.

In this embodiment, the distances between adjacent grooves 210 are equal, which has the advantage of making the current spread in the LED chip more uniform. In other embodiments, the distance between adjacent grooves 210 is not equal.

In an actual process, the specific arrangement of the grooves 210 is set according to actual needs.

Next, a connecting conductive layer is formed on the top surface of the second semiconductor layer 203 in the first region around the groove 210 .

In this embodiment, before forming the connecting conductive layer, it also includes: forming an ohmic contact layer on a part of the top surface of the second semiconductor layer 203 in the first region around the groove 210; forming an ohmic contact layer on the surface of the ohmic contact layer. A reflective layer, the electrical conductivity of the ohmic contact layer is greater than the electrical conductivity of the second semiconductor layer and lower than the electrical conductivity of the reflective layer. After the connection conductive layer is formed, the connection conductive layer covers the reflective layer and the top surface of the second semiconductor layer 203 in the first region around the reflective layer. In other embodiments, no ohmic contact layer and reflective layer are formed.

The methods for forming the ohmic contact layer, the reflective layer and the connection conduction are described in detail below with reference to FIGS. 5 to 8 .

Referring to FIG. 5 and FIG. 6 in conjunction, FIG. 5 is a schematic diagram based on FIG. 3, and FIG. 6 is a schematic diagram based on FIG. Forming an ohmic contact layer 220 ; forming a reflective layer 221 on the surface of the ohmic contact layer 220 , the electrical conductivity of the ohmic contact layer 220 is greater than that of the second semiconductor layer 203 and less than that of the reflective layer 221 .

The function of the reflective layer 221 includes: reflecting the light emitted from the active layer 202 to the second semiconductor layer 203 , and the reflected light is emitted from the first semiconductor layer 201 to improve the light extraction rate of the LED chip.

The reflective layer 221 is made of any one or a combination of Ni, Ag, and Al.

The method of forming the reflective layer 221 includes evaporation process or sputtering process.

The method of forming the ohmic contact layer 220 includes evaporation process or sputtering process.

The functions of the ohmic contact layer 220 include:

The ohmic contact layer 220 serves as an intermediate layer between the reflective layer 221 and the second semiconductor layer 203, so that the bonding force between the reflective layer 221 and the second semiconductor layer 203 is enhanced;

The conductivity of the ohmic contact layer 220 is greater than the conductivity of the second semiconductor layer 203 and smaller than the conductivity of the reflective layer 221, so that the contact barrier between the reflective layer 221 and the second semiconductor layer 203 is reduced;

The refractive index of the ohmic contact layer 220 is smaller than that of the second semiconductor layer 203, and the interface between the ohmic contact layer 220 and the second semiconductor layer 203 forms a total reflection interface of light; after the light emitted from the active layer 202 enters the second semiconductor layer 203 , more light is totally reflected at the interface between the ohmic contact layer 220 and the second semiconductor layer 203 , and only less light enters the ohmic contact layer 220 and then reaches the reflective layer 221 . Further, the light absorption rate of the reflection layer 221 is reduced, thereby increasing the total light reflection rate of the ohmic contact layer 220 and the reflection layer 221 .

In this embodiment, the material of the ohmic contact layer 220 is a transparent conductive material, and the transparent conductive material is indium tin oxide, fluorine-doped tin oxide or aluminum-doped zinc oxide.

In this embodiment, the thickness of the ohmic contact layer 220 is 1 nm˜500 nm, and the thickness of the reflective layer 221 is 10 nm˜500 nm. In other embodiments, the thicknesses of the ohmic contact layer and the reflective layer can be set according to process requirements.

Referring to FIG. 7 and FIG. 8 in conjunction, FIG. 7 is a schematic diagram based on FIG. 5, and FIG. 8 is a schematic diagram based on FIG. Layer 222.

In this embodiment, since the ohmic contact layer 220 and the reflective layer 221 are formed, the connecting conductive layer 222 covers the reflective layer 221 and a part of the top surface of the second semiconductor layer 203 in the first region around the reflective layer 221 .

The method of forming the connecting conductive layer 222 includes evaporation process or sputtering process.

In this embodiment, the material of the connecting conductive layer 222 is metal, and the connecting conductive layer 222 electrically connects the subsequently formed electrode layer and the second semiconductor layer 203 .

In this embodiment, the function of the connecting conductive layer 222 includes: blocking the diffusion of metal atoms in the reflective layer 221 , thereby avoiding leakage of LED chips and ensuring the reliability of the LED chips.

In this embodiment, the connecting conductive layer 222 is a stacked layer structure, and the connecting conductive layer 222 includes one or more stacked stacked layers, and the stacked layer includes a first material layer and a layer located at the first A second material layer on the surface of the material layer, the first material layer is located on a part of the top surface of the second semiconductor layer 203 in the first region around the groove 210 .

Specifically, the first material layer covers the reflective layer 221 and the top surface of the second semiconductor layer 203 in the first region around the reflective layer 221 .

In this embodiment, the material of the first material layer is TiW; the material of the second material layer is Pt or Ti.

The thickness of the first material layer is 50nm-200nm; the thickness of the second material layer is 20nm-100nm. In an actual process, the thicknesses of the first material layer and the second material layer can be selected according to actual conditions.

When the connecting conductive layer 222 is a laminated structure, the barrier ability to the diffusion of metal atoms in the reflective layer 221 is better, and the stress of the film layer is improved, thereby improving the connection between the conductive layer 222 and the reflective layer 221, and the connection between the conductive layer 222 and the reflective layer 221. The bonding quality of the second semiconductor layer 203 .

The number of layers of the laminated group is 1-3 layers, so that the cost of forming the laminated structure is low, and the performance of the laminated structure is better.

In other embodiments, the connecting conductive layer is a single-layer structure, and correspondingly, the material of the connecting conductive layer is TiW, Pt or Ti.

Referring to FIG. 9 and FIG. 10 in conjunction, FIG. 9 is a schematic diagram based on FIG. 7, and FIG. 10 is a schematic diagram based on FIG. The layer 230 exposes the top surfaces of the first semiconductor layer 201 and the second region second semiconductor layer 203 at the bottom of the groove 210 .

The functions of the insulating layer 230 include: electrically isolating the subsequently formed bonding body from the second semiconductor layer 203 , the bonding body and the active layer 202 , and the bonding body and the connecting conductive layer 222 .

The insulating layer 230 is made of silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

The method for forming the insulating layer 230 includes: forming an insulating material layer on the connecting conductive layer 222, the exposed surface of the second semiconductor layer 203, and the sidewall and bottom of the groove 210; removing the second semiconductor layer in the second region The surface of the layer 203 and the connecting conductive layer 222 at the bottom of the groove 210 form an insulating layer 230 .

The process for forming the insulating material layer is a deposition process, such as plasma chemical vapor deposition process, atomic layer deposition process, sub-atmospheric pressure chemical vapor deposition process or low pressure chemical vapor deposition process.

The process of removing the surface of the second semiconductor layer 203 in the second region and the connecting conductive layer 222 at the bottom of the groove 210 includes a dry etching process or a wet etching process.

11 and FIG. 12 in combination, FIG. 11 is a schematic diagram based on FIG. 9, and FIG. 12 is a schematic diagram based on FIG. , and the second semiconductor layer 203 in the second region is combined with the second substrate 250 through the bonding body 240, and the bonding body 240 fills the groove 210 (see FIGS. 9 and 10) and covers the insulating layer 230 and the second region. The top surface of the second semiconductor layer 203 .

The method for performing the bonding treatment includes: forming a first bonding layer (not shown) on the surface of the insulating layer 230, the surface of the first semiconductor layer 201 at the bottom of the groove 210, and the top surface of the second semiconductor layer 203 in the second region. ); providing a second substrate 250; forming a second bonding layer (not shown) on the surface of the second substrate 250; bonding the first bonding layer and the second bonding layer so that the first bond The bonding layer and the second bonding layer form the bonding body 240.

The material of the first bonding layer and the second bonding layer is metal, such as any one or a combination of Au, Cu, In, Ti, Pt, Cr, Ge, Ni.

The process of bonding the first bonding layer and the second bonding layer is low temperature eutectic bonding or metal diffusion (eutectic) bonding.

In this embodiment, during the process of bonding the first bonding layer and the second bonding layer, the first bonding layer and the second bonding layer form a molten state, and the first bonding layer in the molten state and the second bonding layer fill the groove 210 . After the first bonding layer and the second bonding layer are bonded, the first bonding layer and the second bonding layer form a bonding body 240 .

Correspondingly, the material of the bonding body 240 is metal, such as any one or a combination of Au, Cu, In, Ti, Pt, Cr, Ge, Ni.

In this embodiment, the second substrate 250 is an insulating and thermally conductive substrate, and the thermal conductivity of the insulating and thermally conductive substrate is above 45W/(m·K), such as 60W/(m·K), 80W/( m·K), 100W/(m·K), 300W/(m·K) or 500W/(m·K). The material of the insulating and heat-conducting substrate is SiC or AlN.

The thermal conductivity of SiC or AlN is greater than that of sapphire. When the material of the insulating and thermally conductive substrate is SiC or AlN, the thermal conductivity of the second substrate 250 is relatively high, so the heat dissipation performance of the LED chip can be improved.

In other embodiments, the second substrate 250 is a conductive substrate; when the second substrate 250 is a conductive substrate, the method for forming the LED chip further includes: during the bonding process , making the bonding body 240 bond with the second substrate 250 through the isolation layer.

The method for performing the bonding treatment includes: forming a first bonding layer (not shown) on the surface of the insulating layer 230, the surface of the first semiconductor layer 201 at the bottom of the groove 210, and the top surface of the second semiconductor layer 203 in the second region. ); providing a second substrate 250; forming an isolation layer on the surface of the second substrate 250; forming a second bonding layer (not shown) on the surface of the isolation layer; The bonding layer is bonded, so that the first bonding layer and the second bonding layer form the bonding body 240 .

In this embodiment, the material of the second substrate 250 can be a conductive substrate, or an insulating and heat-conductive substrate. Therefore, the second substrate 250 can be selected in a wide range, and can be flexibly selected according to actual conditions.

The function of the isolation layer is to electrically isolate the second substrate 250 and the bonding body 240 so that the current in the LED chip does not flow through the second substrate 250 .

The material of the isolation layer is silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

Referring to FIG. 13 , FIG. 13 is a schematic diagram based on FIG. 11 , after the bonding process, the first substrate 200 is removed (refer to FIGS. 11 and 12 ).

The process of removing the first substrate 200 includes a laser lift-off process.

Next, etching part of the front-end structure of the first region to expose part of the connecting conductive layer, and etching the front-end structure of the second region to expose part of the bonding body.

In this embodiment, it further includes: roughening the surface of the first semiconductor layer 201 after removing the first substrate 200 and before etching the second region and part of the front-end structure of the first region.

Referring to FIG. 14 , the surface of the first semiconductor layer 201 is roughened.

The roughening method includes: using a roughening solution to etch the surface of the first semiconductor layer 201 .

The roughening solution is potassium hydroxide solution or sodium hydroxide solution.

The effect of the roughening treatment includes: avoiding the total reflection of the light emitted from the active layer 202 to the first semiconductor layer 201 on the surface of the first semiconductor layer 201 , thereby improving the light extraction rate.

It should be noted that, in this embodiment, the buffer layer is formed, which further includes: before performing the roughening treatment, removing at least part of the thickness of the buffer layer; if all the buffer layer is removed, after the first semiconductor layer 201 During the process of roughening the surface, the buffer layer is also roughened.

The effect of removing at least part of the thickness of the buffer layer includes: removing a portion of the buffer layer that was damaged during the removal of the first substrate 200 .

Next, referring to FIG. 15 , a portion of the front-end structure of the first region is etched to expose a portion of the connecting conductive layer 260 , and the front-end structure of the second region is etched to expose a portion of the bonding body 240 .

In this embodiment, the front-end structure of the second region and part of the front-end structure of the first region are etched simultaneously.

The method for etching the front-end structure of the second region and part of the front-end structure of the first region includes an anisotropic dry etching process.

Next, referring to FIG. 16 , a passivation layer 260 is formed on the surface of the front end structure, the surface of the insulating layer 230 , and the surface of the part of the bonding body 240 that is partially exposed, and the passivation layer 260 exposes a part of the surface of the connecting conductive layer 222; After the passivation layer 260 is formed, an electrode layer 270 is respectively formed on the exposed surface of the connection conductive layer 222 and the surface of the bonding body 240 .

The material of the passivation layer 260 is silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

The method for forming the passivation layer 250 includes: forming a passivation material layer on the surface of the front end structure, the surface of the insulating layer 230, and the exposed surface of the connecting conductive layer 222 and the surface of the bonding body 240; patterning the passivation material layer to form the passivation layer 250 .

The electrode layer 270 is used to connect to an external voltage source.

The material of the electrode layer 270 is metal, such as one or any combination of Cr, Pt, Au, Al, Ti.

The electrode layer 270 is a single-layer structure or a multi-layer structure.

In this embodiment, the electrode layer 270 is planar. In other embodiments, the electrode layer 270 is a conductive plug.

In this embodiment, the expansion of the current in the LED chip does not depend on the electrode layer 270, so the design of the area of the electrode layer 270 does not need to consider the influence on the expansion of the current in the LED chip. The selection range of the area of the electrode layer 270 is relatively large.

The electrode layer 270 on the surface of the connecting conductive layer 222 is electrically connected to the second semiconductor layer 203 through the connecting conductive layer 222, and the electrode layer 270 on the surface of the bonding body 240 is electrically connected to the first semiconductor layer 201 through the bonding body 240, and the first semiconductor layer 201 is electrically connected to the first semiconductor layer 201 through the bonding body 240. The source layer 202 and the second semiconductor layer 203 are electrically connected. Therefore, the current in the LED chip flows through the electrode layer 270 connecting the conductive layer 222, connecting the conductive layer 222, the second semiconductor layer 203, the active layer 202, the first semiconductor layer 201, the bonding body 240, and the electrode on the surface of the bonding body 240. Layer 270. Since the external voltage source does not need to apply voltage to the first semiconductor layer 201 through the second substrate 250 and the bonding body 240, the current in the LED chip does not need to flow through the second substrate 250, and the first semiconductor layer 201 does not need to pass through the bonding body. 240 and the second substrate 250 are electrically connected. The requirements for the material of the second substrate 250 are no longer limited to conductive materials, which is beneficial to reduce the process complexity of LED chip-on-chip packaging.

It is beneficial to reduce the process complexity of LED chip-on-chip packaging: when the material of the second substrate 250 can be an insulating and heat-conducting material, there is no need to set a bus in the contact area between the second substrate 250 and the packaging substrate. For solder joints for electrical connection, the second substrate 250 only needs to be fixed on the area that is in contact with the packaging substrate. Different LED chips are electrically connected through the electrode layer 270 . In this way, the wiring complexity of the packaging substrate for the chip-on-chip packaging of the LED chip can be reduced.

Correspondingly, this embodiment also provides an LED chip formed by the above method, please continue to refer to FIG. 16 , including: a second substrate 250; a bonding body 240 located on the second substrate 250, and the bonding body 240 includes The base on the surface of the second substrate 250 and the protrusion on the surface of the base; the insulating layer 230 located on the side wall of the protrusion and part of the surface of the base; the connecting conductive layer 222 located on the surface of part of the insulating layer 230, and the connecting conductive layer 222 is located on the substrate; the second semiconductor layer 203 located on part of the connecting conductive layer 222 and the active layer 202 located on the surface of the second semiconductor layer 203, the insulating layer 230 of the protrusion and the protrusion sidewall penetrates the second The semiconductor layer 203 and the active layer 202; the first semiconductor layer 201 located on the surface of the second semiconductor layer 203, the active layer 202, the protrusion and the insulating layer 230 of the protrusion sidewall; respectively located on the surface of the exposed connecting conductive layer 222 and the electrode layer 270 on the surface of the bonding body 240 .

The second substrate 250 is an insulating and thermally conductive substrate, and the thermal conductivity of the insulating and thermally conductive substrate is above 45W/(m·K), such as 60W/(m·K), 80W/(m·K), 100W/(m·K), 300W/(m·K) or 500W/(m·K); or the second substrate 250 is a conductive substrate; when the second substrate 250 is a conductive substrate , the LED chip further includes: an isolation layer (not shown) located between the second substrate 250 and the bonding body 240 .

The material of the isolation layer is silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

The material of the insulating and heat-conducting substrate is SiC or AlN.

The material of the bonding body 240 is any one or a combination of Au, Cu, In, Ti, Pt, Cr, Ge, Ni.

The insulating layer 230 is made of silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

The insulating layer 230 is used to electrically isolate the bonding body 240 from the second semiconductor layer 203 , the bonding body 240 from the active layer 202 , and the bonding body 240 from the connecting conductive layer 222 .

The material of the connecting conductive layer 222 is metal, and the connecting conductive layer 222 electrically connects the electrode layer 270 and the second semiconductor layer 203 .

In this embodiment, the connecting conductive layer 222 is a stacked layer structure; the connecting conductive layer 222 includes one or more stacked stacked layers, and the stacked layer includes a second material layer and is located on the second The first material layer on the surface of the material layer, the second material layer is located on a part of the surface of the insulating layer 230, and the second material layer is located on the base.

The material of the first material layer is TiW; the material of the second material layer is Pt or Ti.

The thickness of the first material layer is 50nm-200nm; the thickness of the second material layer is 20nm-100nm. In an actual process, the thicknesses of the first material layer and the second material layer can be selected according to actual conditions.

In other embodiments, the connecting conductive layer has a single-layer structure, and correspondingly, the material of the connecting conductive layer is TiW, Pt or Ti.

The LED chip also includes: a reflective layer 221 located between the second semiconductor layer 203 and the connecting conductive layer 222; an ohmic contact layer 220 located between the reflective layer 221 and the second semiconductor layer 203, the ohmic contact layer 220 The conductivity is greater than that of the second semiconductor layer 203 and smaller than that of the reflective layer 221 .

The reflective layer 221 is made of any one or a combination of Ni, Ag, and Al.

In this embodiment, the material of the ohmic contact layer 220 is a transparent conductive material, and the transparent conductive material is indium tin oxide, fluorine-doped tin oxide or aluminum-doped zinc oxide.

The material of the first semiconductor layer 201 is N-type GaN; the material of the second semiconductor layer 203 is P-type GaN; the active layer 202 is a quantum well layer.

The material of the electrode layer 270 is metal, such as one or any combination of Cr, Pt, Au, Al, Ti. The electrode layer 270 is used to connect to an external voltage source.

In the LED chip provided in this embodiment, the electrode layer 270 connected to the conductive layer surface 222 is electrically connected to the second semiconductor layer 203 through the connected conductive layer 222, and the electrode layer 270 on the surface of the bonding body 240 is electrically connected to the first semiconductor layer 201 through the bonding body 240. The first semiconductor layer 201 is electrically connected to the second semiconductor layer 203 through the active layer 202 . Therefore, the current in the LED chip flows through the electrode layer 270 connected to the surface of the conductive layer 222, the connected conductive layer 222, the second semiconductor layer 203, the active layer 202, the first semiconductor layer 201, the bonding body 240, and the surface of the bonding body 240. electrode layer 270 . Since the external voltage source does not need to apply voltage to the first semiconductor layer 201 through the second substrate 250 and the bonding body 240, the current in the LED chip does not need to flow through the second substrate 250, and the first semiconductor layer 201 does not need to pass through the bonding body. 240 and the second substrate 250 are electrically connected. The requirements for the material of the second substrate 250 are no longer limited to conductive materials, which is beneficial to reduce the process complexity of LED chip-on-chip packaging.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (19)

1. A method for forming an LED chip, comprising: providing a first substrate having a front-end structure on the first substrate, the front-end structure comprising a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer, The front end structure has a first zone and a second zone; forming a groove penetrating through the second semiconductor layer and the active layer in the first region; forming a connecting conductive layer on the top surface of the second semiconductor layer in the first region around the groove; forming an insulating layer covering the connecting conductive layer and the sidewall of the groove, the insulating layer exposing the first semiconductor layer at the bottom of the groove and the top surface of the second semiconductor layer in the second region; performing a bonding process, so that the insulating layer, the first semiconductor layer at the bottom of the groove, and the second semiconductor layer in the second region are combined with the second substrate through a bonding body, and the bonding body fills the groove and covers the insulating layer and the first semiconductor layer the top surface of the second semiconductor layer in the second region; After performing the bonding treatment, removing the first substrate; After removing the first substrate, etch part of the front-end structure of the first region to expose part of the connecting conductive layer, etch the front-end structure of the second region to expose part of the bonding body; Electrode layers are respectively formed on the exposed surface of the connecting conductive layer and the surface of the bonding body. 2. The method for forming an LED chip according to claim 1, wherein the connecting conductive layer comprises one or more stacked stacked layers, and the stacked stacked layer includes a first material layer and a A second material layer on the surface of the first material layer, the first material layer is located on the top surface of the second semiconductor layer in the first region around the groove. 3. The method for forming an LED chip according to claim 2, wherein the material of the first material layer is TiW; the material of the second material layer is Pt or Ti. 4. The method for forming an LED chip according to claim 1, wherein the method for performing the bonding treatment comprises: on the surface of the insulating layer, on the surface of the first semiconductor layer at the bottom of the groove, and on the second surface of the second region. A first bonding layer is formed on the top surface of the semiconductor layer; a second substrate is provided; a second bonding layer is formed on the surface of the second substrate; the first bonding layer and the second bonding layer are bonded, so that The first bonding layer and the second bonding layer form the bonded body. 5. The method for forming an LED chip according to claim 1, wherein the second substrate is an insulating and heat-conducting substrate, and the thermal conductivity of the insulating and heat-conducting substrate is above 45W/(m·K) or the second substrate is a conductive substrate; when the second substrate is a conductive substrate, the method for forming the LED chip further includes: during the bonding process, making the The bonding body is combined with the second substrate through the isolation layer. 6 . The method for forming an LED chip according to claim 5 , wherein the insulating and heat-conducting substrate is made of SiC or AlN. 7. The method for forming an LED chip according to claim 1, further comprising: before forming the connecting conductive layer, forming a part of the top surface of the second semiconductor layer in the first region around the groove A reflective layer; the connecting conductive layer covers the reflective layer and the top surface of part of the second semiconductor layer in the first region around the reflective layer. 8. The method for forming an LED chip according to claim 7, further comprising: before forming the reflective layer, forming an ohmic layer on a part of the top surface of the second semiconductor layer in the first region around the groove. A contact layer, the conductivity of the ohmic contact layer is greater than that of the second semiconductor layer and smaller than that of the reflective layer; the reflective layer covers the ohmic contact layer. 9. The method for forming an LED chip according to claim 1, further comprising: after removing the first substrate and before etching the second region and part of the front-end structure of the first region, The surface of the first semiconductor layer is roughened; after etching the front-end structure of the second region and part of the first region, a passivation layer is formed on the surface of the front-end structure, the surface of the insulating layer and the partially exposed surface of the bonding body, and the obtained The passivation layer exposes part of the surface of the connecting conductive layer; after the passivation layer is formed, the electrode layer is formed. 10. An LED chip, characterized in that it comprises: second substrate; A bonding body on the second substrate, the bonding body comprising a base on the surface of the second substrate and a protrusion on the surface of the base; an insulating layer located on the raised sidewall and part of the surface of the substrate; a connecting conductive layer located on the surface of part of the insulating layer, and the connecting conductive layer is located on the substrate; a second semiconductor layer located on part of the connecting conductive layer and an active layer located on the surface of the second semiconductor layer, the protrusion and the insulating layer of the protrusion sidewall penetrate through the second semiconductor layer and the active layer; The first semiconductor layer located on the surface of the insulating layer of the second semiconductor layer, the active layer, the protrusion and the side wall of the protrusion; The electrode layers are respectively located on the exposed surface of the connecting conductive layer and the surface of the bonding body. 11. The LED chip according to claim 10, wherein the connecting conductive layer comprises one or more laminated stacked layers, and the stacked stacked layer includes a second material layer and is located in the second material The first material layer on the surface of the layer, the second material layer is located on a part of the surface of the insulating layer, and the second material layer is located on the substrate. 12. The LED chip according to claim 11, wherein the material of the first material layer is TiW; the material of the second material layer is Pt or Ti. 13. The LED chip according to claim 10, wherein the second substrate is an insulating and heat-conducting substrate, and the thermal conductivity of the insulating and heat-conducting substrate is above 45W/(m·K); or the The second substrate is a conductive substrate; when the second substrate is a conductive substrate, the LED chip further includes: an isolation layer between the second substrate and the bonding body. 14. The LED chip according to claim 13, wherein the material of the insulating and heat-conducting substrate is SiC or AlN. 15. The LED chip according to claim 10, further comprising: a reflective layer located between the second semiconductor layer and the connecting conductive layer. 16. The LED chip according to claim 15, further comprising: an ohmic contact layer located between the reflective layer and the second semiconductor layer, the electrical conductivity of the ohmic contact layer being greater than that of the second semiconductor layer And less than the conductivity of the reflective layer. 17. The LED chip according to claim 16, wherein the material of the ohmic contact layer is a transparent conductive material. 18. The LED chip according to claim 17, wherein the transparent conductive material is indium tin oxide, fluorine-doped tin oxide or aluminum-doped zinc oxide. 19. The LED chip according to claim 10, wherein the material of the bonding body is any one or a combination of Au, Cu, In, Ti, Pt, Cr, Ge, Ni.