CN106409907B - Stack for semiconductor device and method of forming the same - Google Patents
Stack for semiconductor device and method of forming the same Download PDFInfo
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Abstract
公开了用于半导体装置的堆叠件和用于形成所述堆叠件的方法。所述堆叠件包括：多个牺牲层，每个牺牲层包括第一晶格参数；至少一个沟道层，包括与第一晶格参数不同的第二晶格参数，每个沟道层设置在两个牺牲层之间并与所述两个牺牲层接触。堆叠件形成在下层上，牺牲层与下层接触。下层包括第三晶格参数，所述第三晶格参数与在所述多个牺牲层和所述至少一个沟道层被允许连贯地弛豫时所述多个牺牲层和所述至少一个沟道层将具有的晶格参数基本上相匹配。
Stacks for semiconductor devices and methods for forming the stacks are disclosed. The stack includes: a plurality of sacrificial layers, each sacrificial layer including a first lattice parameter; at least one channel layer including a second lattice parameter different from the first lattice parameter, each channel layer disposed at between and in contact with the two sacrificial layers. The stack is formed on the lower layer, and the sacrificial layer is in contact with the lower layer. The lower layer includes a third lattice parameter that is related to the plurality of sacrificial layers and the at least one channel layer when the plurality of sacrificial layers and the at least one channel layer are allowed to relax coherently The track layers will have lattice parameters that are substantially matched.
Description
This patent application claims priority to U.S. provisional patent application No. 62/200,335 filed on 3/8/2015 and U.S. non-provisional patent application No. 15/086,015 filed on 30/3/2016, the disclosures of which are incorporated herein by reference in their entirety.
Technical Field
The present disclosure relates to semiconductor devices. More particularly, the present disclosure relates to a stack of nanowires and/or nanoplates formed on an underlying layer having a lattice parameter that substantially matches a lattice parameter that the stack of nanoplates and/or nanowires would have if allowed to coherently relax.
Background
The strained semiconductor material may provide improved current transfer characteristics in semiconductor devices such as Field Effect Transistors (FETs). Compressive strain in the channel of the FET may provide improved hole mobility for a p-channel FET, while tensile strain in the channel of the FET may provide improved electron mobility for an n-channel FET.
Disclosure of Invention
An exemplary embodiment provides a stack for a semiconductor device, the stack including: a plurality of sacrificial layers, each sacrificial layer comprising a first lattice parameter; at least one channel layer comprising a second lattice parameter different from the first lattice parameter, each channel layer disposed between and in contact with two sacrificial layers; a lower layer on which the plurality of sacrificial layers and the at least one channel layer are disposed, the sacrificial layers in contact with the lower layer, the lower layer comprising a third lattice parameter that substantially matches a lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were allowed to coherently relax. The lower layer does not substantially generate any defects in the plurality of sacrificial layers and the at least one channel layer, except for any propagation of defects present in the lower layer toward the stack.
Another exemplary embodiment provides a stack for a semiconductor device, the stack including: a plurality of sacrificial layers, each sacrificial layer comprising a first lattice parameter, a first end, a second end, and a cross-sectional area, the cross-sectional area being positioned in a direction substantially perpendicular to a direction between the first end and the second end of each sacrificial layer, the cross-sectional area of each sacrificial layer comprising a first thickness and a first width substantially perpendicular to the first thickness, the first thickness of each sacrificial layer being less than a metastable critical thickness of a sacrificial layer material; at least one channel layer comprising a second lattice parameter, a first end, a second end, and a cross-sectional area, the cross-sectional area being positioned in a direction substantially perpendicular to a direction between the first end and the second end of the at least one channel layer, the second lattice parameter being different from the first lattice parameter, each channel layer being disposed between and in contact with two sacrificial layers, the cross-sectional area of each channel layer comprising a second thickness and a second width substantially perpendicular to the second thickness, the second thickness of each channel layer being less than a metastable critical thickness of a channel layer material; an underlying layer, on which the plurality of sacrificial layers and the at least one channel layer are disposed, the sacrificial layers being in contact with the underlying layer, the underlying layer being substantially free of any defects in the plurality of sacrificial layers and the at least one channel layer, except for any propagation of defects present in the underlying layer prior to deposition of the stack.
Yet another exemplary embodiment provides a method of forming a stack for a semiconductor device, the method including: providing a lower layer; forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlying layer, the sacrificial layers in contact with the underlying layer, each sacrificial layer comprising a first lattice parameter, the at least one channel layer comprising a second lattice parameter different from the first lattice parameter, each channel layer disposed between and in contact with two sacrificial layers, the underlying layer comprising a third lattice parameter that substantially matches a lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were allowed to consecutively relax.
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In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the drawings, in which:
1A-1D respectively depict an exemplary stack of strained channel nanosheets at selected stages of formation as described by the method of FIG. 2 according to the subject matter disclosed herein;
fig. 2 depicts a flow diagram of an exemplary method of forming a stack of strained channel nanoplates that includes substantially no stacking-induced defects in the nanoplates according to the subject matter disclosed herein;
fig. 3 depicts an electronic device comprising one or more integrated circuits (chips) comprising one or more stacks of nanowires and/or nanoplates formed in accordance with exemplary embodiments disclosed herein; and
fig. 4 depicts a memory system that may include one or more integrated circuits (chips) containing one or more stacks of nanowires and/or nanoplates formed in accordance with the exemplary embodiments disclosed herein.
Detailed Description
The subject matter disclosed herein relates to a stack of nanowires and/or nanoplates formed on an underlying layer having a lattice parameter that substantially matches the lattice parameter that the stack of nanoplates and/or nanowires would have if allowed to coherently relax (relax coherent). As used herein, the phrase "substantially matched with … …" generally means a lattice parameter mismatch of about 0.2% or less, and in some embodiments the phrase "substantially matched with … …" may mean a lattice parameter mismatch of about 0.5% or less. As used herein, the term "mismatch" means a lattice parameter mismatch between the underlying lattice parameter and the lattice parameter that the stack would have if the stack were allowed to relax coherently. The role of the underlying layer is not to directly strain the layers of the stack, since the strain induced in the stack is mainly determined by the stack itself (i.e., the sacrificial and channel layers of the stack) and not by the underlying layers of the stack. One function of the lower layer may be to inhibit plastic relaxation of the stack by introducing new defects in the stack.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment disclosed herein. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases having similar meanings) in various places throughout this specification are not necessarily all referring to the same embodiment. As used herein, the word "exemplary" means "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context discussed herein, singular terms may include the corresponding plural form, and plural terms may include the corresponding singular form. It is also noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Likewise, the various waveform diagrams and timing diagrams are for illustrative purposes only.
As used herein, the terms "first," "second," and the like are used as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly so defined. Furthermore, the same reference numbers may be used across two or more drawings to refer to components, assemblies, blocks, circuits, units, or modules having the same or similar functionality. Such usage is merely for simplicity of illustration and ease of discussion; it is not intended to imply that the structural or architectural details of such components or units are the same throughout all embodiments, or that such commonly referenced parts/modules are the only means of implementing the teachings of the specific embodiments disclosed herein.
The subject matter disclosed herein relates to devices, such as, but not limited to, Field Effect Transistors (FETs), that contain one or more stacks of Nanowires (NWs) and/or one or more stacks of Nanoplates (NS). As used herein, the term "nanowire" means a conductive structure having a cross-sectional area of: which is substantially perpendicular to the direction of current transport through the nanowire and in which the right angle cross-sectional dimensions are similar and small. For example, the nanowires may comprise conductive structures having cross-sectional areas in which the right angle cross-sectional dimensions may range from a few nanometers to about 20 nm. Also as used herein, the term "nanoplatelets" means conductive structures having a cross-sectional area of: which is substantially perpendicular to the direction of current transmission through the nanoplatelets and in which one of the orthogonal cross-sectional dimensions is significantly smaller than the other. For example, the nanoplatelets may comprise conductive structures having a cross-sectional area with one right angle cross-sectional dimension in the range from a few nanometers to about 20nm and another right angle cross-sectional dimension in the range from about 15nm to about 70 nm. As used herein, the terms "nanowire" and "nanosheet" may be used interchangeably. Furthermore, the terms "nanowire" and "nanosheet" may refer herein to a plurality of layers. With respect to the term "stack", the term "stack" as used herein may denote a plurality of sacrificial layers and a plurality of channel layers having dimensions consistent with one of the nanowires and/or nanosheets and formed in a stack of alternating sequences of sacrificial layers and channel layers.
The subject matter disclosed herein more particularly relates to stacks of nanowires and/or nanoplates formed on an underlayer having a lattice parameter that substantially matches the lattice parameter that the stacks of nanoplates and/or nanowires would have if allowed to coherently relax. Such underlayers may include, but are not limited to, strain-relaxed buffers (SRBs), elastically strained buffers, or any underlaying material that includes a lattice parameter that the stack of nanoplates and/or nanowires will have when the stack is allowed to relax coherently. According to the subject matter disclosed herein, the role of the underlying layer is not to directly strain the layers of the stack. The strain induced in the stack is determined primarily by the stack itself (i.e., the sacrificial and channel layers of the stack) rather than by the underlying layers of the stack. One function of the underlayer may be to inhibit plastic relaxation of the stack by introducing defects into the stack from the underlayer.
Fig. 1A-1D respectively depict an exemplary stack 100 of strained channel nanosheets at selected stages of formation as described by the method of fig. 2 according to the subject matter disclosed herein. Fig. 2 depicts a flow diagram of an exemplary method 200 of forming a stack of strained channel nanoplates that includes substantially no stacking-induced defects in the nanoplates according to the subject matter disclosed herein. The stack of strained channel nanoplates according to the subject matter disclosed herein may be used in a semiconductor device such as, but not limited to, a FET.
Referring to fig. 1A-1D and fig. 2, at operation 201 in fig. 2, an underlying material is selected that includes a lattice parameter that substantially matches a lattice parameter that a stack of nanoplatelets to be formed would have if the stack were allowed to relax coherently in an isolated state. As used herein, the term "underlayer" means a Strain Relaxed Buffer (SRB), an elastically strained buffer, or any underlayer material that includes a lattice parameter that substantially matches the lattice parameter that a stack to be formed would have if the stack were allowed to relax coherently in isolation. Examples of underlying layers include, but are not limited to, strained silicon on insulator (sSOI), SiGeOI, or a layer of group IV or non-group IV atoms or of a group III-V material or of a group II-VI material. The underlying layer may be on an insulator or grown from a substrate (with possibly other layers between the underlying layer and the substrate). Typically, the underlying layer is substantially monocrystalline.
At operation 202, an underlayer 101 is formed on, for example, a substrate (not shown) using well-known deposition techniques. The lower layer 101 is formed from the material selected in operation 201.
At operation 203, stack 100 of sacrificial layer 102 and channel layer 103 is epitaxially formed on underlying layer 101 using well-known deposition techniques. The sacrificial layer 102 and the channel layer 103 are formed in an alternating order in which the sacrificial layer 102 is directly formed on the lower layer 101. In one exemplary embodiment, stack 100 includes a top sacrificial layer 102 formed on a channel layer 103.
The sacrificial layer material and the channel layer material are selected based on the amount and type of strain to be imparted to the channel layer. If the channel layer is to have tensile strain, then the material selected for the sacrificial layer will have a lattice parameter (in its relaxed state) that is greater than the lattice parameter (in its relaxed state) of the material selected for the channel layer. Conversely, if the channel layer is to have a compressive strain, the material selected for the sacrificial layer will have a lattice parameter (in its relaxed state) that is less than the lattice parameter (in its relaxed state) of the material selected for the channel layer. The composition and lattice parameters of the sacrificial layer material and the channel layer material may also be based on engineering constraints such as, but not limited to, etch selectivity, ability to grow epitaxial layers, and desired stress (greater strain is induced by a larger lattice parameter mismatch between the channel layer and the sacrificial layer (in their relaxed state)).
The respective thicknesses and the respective lattice parameters of the sacrificial layer and the channel layer will be physically combined in the stack such that the stack will have an overall lattice parameter based on a weighted average of the lattice parameters of the sacrificial layer and the channel layer. The weighted average of the lattice parameter will be the lattice parameter that a stack of nanoplates will have if an isolated stack is allowed to relax coherently. Thus, the materials and embodiments selected for the underlying layer should ideally result in a lattice parameter that is: which is substantially equal to the lattice parameter that a stack of nanoplatelets would have if an isolated stack were allowed to relax coherently. For example, if the stack to be formed is for an nMOS device, the channel layer may include Si and the sacrificial layer may include SiGe. As another example, if the formed stack is used for a pMOS device, the channel layer may include SiGe and the sacrificial layer may include Si. For pMOS devices comprising a SiGe channel layer and a Si sacrificial layer, the stack is dominated by the Si sacrificial layer, which is in their lowest strain energy state by maintaining the lattice parameter of the substrate (Si). These structures with SiGe channel layers of 5nm are very robust (in most cases thermodynamically stable) against defect generation. In practice, the limitation of Ge content in the SiGe channel layer is based on band-to-band tunneling (BTBT) and Parasitic Bipolar Effect (PBE) considerations, rather than from defect generation.
Fig. 1A depicts stack 100 formed on lower layer 101 after operation 203 in fig. 2. The stack 100 includes a stack of sacrificial layers and channel layers alternately formed on each other. In one exemplary embodiment, stack 100 includes a top sacrificial layer 102 formed on a channel layer 103.
At operation 204, source/drain recesses (or structural cutouts) are formed in stack 100 using known techniques to form spaces 104 for source/drain regions. It should be understood that only one of the spaces 104 for the source/drain regions is indicated in fig. 1B. A space 104 for source/drain regions extends through stack 100 to about lower layer 101.
The regions of the stacked material left between the spaces 104 for the source/drain regions are short (e.g., less than about 100nm) so that the remaining regions of the stacked material are substantially fully elastically relaxed. The strain in the channel layer in the areas of the remaining stacked material is primarily determined by the elastic deformation of the stack at the point where the source/drain recess (or structural kerf) is formed (i.e., operation 204). In particular, the strain in the channel layer is a function of the respective thicknesses of the sacrificial layer and the channel layer and their respective compositions. The strain state (or a desired portion of the strain state) of the remaining regions of the stacked material may be maintained throughout the remainder of the fabrication flow.
The large difference in lattice parameter between the sacrificial layer and the channel layer causes a higher level of strain to be generated in the channel. Such as a Si/SiGe stack, the larger difference in Ge content between the sacrificial material and the channel material results in a larger final channel strain. For example, for a substrate comprising a 5nm thick channel layer and a 15nm thick sacrificial layer and |. DELTA.GeContent (wt.)With | ≈ 25% of the stack, the peak strain in the channel layer is-0.76%. In contrast, for a channel layer and a sacrificial layer comprising the same thickness and |. DELTA.GeContent (wt.)With | ≈ 40% of the stack, the peak strain in the channel layer is-1.2%.
In operation 205, the edges of sacrificial layer 102 exposed when forming spaces 104 for source/drain regions are etched or undercut (undercut) using well-known techniques to removeExcept for portions 105 of each sacrificial layer 102 between adjacent channel layers 103 to subsequently form the inner spacers. It should be understood that only one undercut portion 105 of the sacrificial layer 102 is indicated in fig. 1C. The etch depth of the sacrificial layer is selected to optimize Cpara(parasitic capacitance), Rpara(parasitic resistance) and the desired strain in the channel layer. That is, as the sacrificial layer 102 is etched back from the exposed edges of the stack, the ends of the channel layer will elastically relax to the natural lattice parameter of the material selected for the channel layer, because the portions of the sacrificial layer that have been etched away no longer impart the lattice parameter (and strain) of the sacrificial layer to the channel layer.
For exemplary embodiments in which the channel layer length is about 20nm or less, the width of the internal spacers (i.e., the amount of sacrificial material that is undercut) should be limited to, for example, less than about 8 nm. As the length of the channel material decreases from about 20nm, the undercut of the sacrificial layer should be limited to less than about 5 nm. In some embodiments with shorter channels, the undercut of the sacrificial layer should be limited to less than 3 nm. The strain in the channel layer is controlled by the relaxed state of the entire stack itself (before release), which in turn is controlled by the thickness and composition of the channel layer and the sacrificial layer. Note that because the final strain in the channel is controlled by the stack itself, the effect of the underlying layers in directly determining the final channel strain is essentially negligible.
Referring back to fig. 1A-1D and fig. 2, at operation 206, the inner spacers 106 are formed in the recesses 105 (fig. 1C) of the sacrificial layer 102 and the spaces 104 (fig. 1B) of the source/drain regions are filled with a semiconductor material 107 using well-known epitaxial regrowth techniques. The interior spacers may include, but are not limited to, for example, silicon nitride or a low-k dielectric material such as, but not limited to, SiOCH, SiOCN, or SiBCN. Formation of the source and drain regions may be accomplished in a manner that maintains the source/drain regions in a substantially relaxed state and does not substantially change the state of strain in the channel.
The filled source/drain regions 107 are physically bonded to the ends of the channel layer 103, and the physical presence of the filled source/drain regions 107 maintains strain in the channel layer 103. As mentioned, the strain induced in the channel layer 103 is a function of the thickness of the respective layers of the sacrificial layer and the channel layer and their respective compositions. The larger difference in lattice parameter between the sacrificial layer and the channel layer causes a higher level of strain to be generated in the channel layer 103.
The channel layer 103 is released by removing the sacrificial layer 102 using well-known techniques. In releasing the channel layer, it is important that the geometry and boundary conditions are such that the strain is maintained in the channel layer. For a process flow where the source/drain structure 107 is epitaxially grown prior to releasing the channel layer, the source/drain structure 107 helps maintain strain in the channel after release. For example, if the tall source/drain columnar structure 107 is bonded to the channel layer 103 on only one side of the channel layer, the source/drain columnar structure 107 may be bent under the influence of channel stress when releasing the channel layer. However, if the channel layer structure 103 is formed substantially symmetrically on both sides of the source/drain columnar structure, such as depicted in figure 1D for the source/drain structure 107, then the source/drain columnar structure will be substantially balanced and will not substantially bend upon release of the channel layer.
At operation 207, the sacrificial layer 102 is removed (i.e., channel layer release), which is part of, for example, a well-known replacement gate process. After removal of sacrificial layer 102, the strain in channel layers 103 is redistributed such that the strain in each channel layer 103 becomes substantially uniform. That is, because the force along the length of the channel layer 103 is balanced, the stress, which is the force per unit area, is inversely proportional to the cross-sectional area of the channel layer. Therefore, as long as the cross-sectional area of the channel layer is uniform, the strain in the channel layer will be uniform. Otherwise, the strain in the channel layer will be inversely proportional to the cross-sectional area of the channel layer. Thus, selective adjustment of the cross-sectional area of the channel layer may be utilized to increase the channel strain after channel layer release (i.e., the channel strain is inversely proportional to the cross-sectional area of the channel layer).
Fig. 3 depicts an electronic device 300, the electronic device 300 including one or more integrated circuits (chips) comprising one or more stacks of nanowires and/or nanoplates formed in accordance with the exemplary embodiments disclosed herein. The electronic device 300 may be used in, but is not limited to, a computing device, a Personal Digital Assistant (PDA), a laptop computer, a mobile computer, a web tablet, a wireless telephone, a cellular telephone, a smart phone, a digital music player, or a wired or wireless electronic device. Electronic device 300 may include a controller 310, an input/output device 320 (such as but not limited to a keypad, keyboard, display, or touch screen display), a memory 330, and a wireless interface 340, coupled to each other by a bus 350. The controller 310 may include, for example, at least one microprocessor, at least one digital signal processor, at least one microcontroller, or the like. The memory 330 may be configured to store command codes or user data to be used by the controller 310. The electronic device 300 and various system components included in the electronic device 300 may include one or more stacks of nanowires and/or nanoplates formed in accordance with the exemplary embodiments disclosed herein. The electronic device 300 may use a wireless interface 340, the wireless interface 340 being configured to transmit data to or receive data from a wireless communication network using RF signals. Wireless interface 340 may include, for example, an antenna, a wireless transceiver, and the like. Electronic system 300 may be used in a communication interface protocol of a communication system such as, but not limited to, Code Division Multiple Access (CDMA), global system for mobile communications (GSM), North American Digital Communication (NADC), extended time division multiple access (E-TDMA), wideband CDMA (wcdma), CDMA2000, Wi-Fi, municipal Wi-Fi (muniw-Fi), bluetooth, Digital Enhanced Cordless Telecommunications (DECT), wireless universal serial bus (wireless USB), fast low latency access with seamless handover orthogonal frequency division multiplexing (Flash-OFDM), IEEE 802.20, General Packet Radio Service (GPRS), iBurst, wireless broadband (WiBro), WiMAX upgrades, universal mobile telecommunications system-time division duplex (UMTS-TDD), High Speed Packet Access (HSPA), evolution-data optimized (EVDO), long term evolution upgrade (LTE upgrade), multi-channel multi-point distribution service (MMDS), and the like.
Fig. 4 depicts a memory system 400, which memory system 400 may include one or more integrated circuits (chips) comprising one or more stacks of nanowires and/or nanoplates formed in accordance with the exemplary embodiments disclosed herein. Memory system 400 may include a memory device 410 and a memory controller 420 for storing large amounts of data. The memory controller 420 controls the memory device 410 to read data stored in the memory device 410 or write data to the memory device 410 in response to a read/write request of the host 430. Memory controller 420 may include an address mapping table for mapping addresses provided by host 430 (e.g., a mobile device or computer system) to physical addresses of memory device 410. The memory device 410 may include one or more semiconductor devices according to example embodiments disclosed herein.
As will be recognized by those skilled in the art, the inventive concepts described herein can be modified and varied over a wide range of applications. Accordingly, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the claims.
Claims (17)
1. A stack for a semiconductor device, the stack comprising:
a plurality of sacrificial layers, each sacrificial layer comprising a first lattice parameter;
at least one channel layer comprising a second lattice parameter different from the first lattice parameter, each channel layer disposed between and in contact with two sacrificial layers; and
a lower layer on which the plurality of sacrificial layers and the at least one channel layer are disposed, the sacrificial layers in contact with the lower layer, the lower layer comprising a third lattice parameter that substantially matches a lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were allowed to coherently relax,
wherein the at least one channel layer includes a first end and a second end in a first direction, the stack further includes a source/drain structure disposed at and contacting each of the first end and the second end of the at least one channel layer, the plurality of sacrificial layers and the at least one channel layer are alternately stacked in a second direction, the first direction crossing the second direction,
wherein each sacrificial layer includes a first end and a second end in the first direction, and the stack further includes a plurality of internal spacers disposed between the first end of each sacrificial layer and the source/drain structure and between the second end of each sacrificial layer and the source/drain structure.
2. The stack for a semiconductor device according to claim 1, wherein the lower layer does not substantially generate any defect in the plurality of sacrificial layers and the at least one channel layer except for any spread of defects existing in the lower layer toward the stack.
3. The stack for a semiconductor device according to claim 1, wherein the first lattice parameter is larger than the second lattice parameter.
4. The stack for a semiconductor device according to claim 1, wherein the first lattice parameter is smaller than the second lattice parameter.
5. The stack for a semiconductor device according to claim 1, wherein each sacrificial layer further comprises a first thickness, the first thickness being substantially perpendicular to a direction between the first end and the second end of the sacrificial layer, the first thickness of each sacrificial layer being less than a metastable critical thickness of the sacrificial layer material,
wherein each channel layer further comprises a second thickness substantially perpendicular to a direction between the first end and the second end of the channel layer, the second thickness of each channel layer being less than the metastable critical thickness of the channel layer material.
6. The stack for a semiconductor device according to claim 5, wherein a first distance between a first end and a second end of at least one of the plurality of sacrificial layers is smaller than a second distance between the first end and the second end of the at least one channel layer.
7. The stack for a semiconductor device according to claim 1, wherein the plurality of sacrificial layers include at least one nanosheet,
wherein the at least one channel layer comprises at least one nanoplate.
8. The stack for a semiconductor device according to claim 1, wherein the plurality of sacrificial layers comprise at least one nanowire,
wherein the at least one channel layer comprises at least one nanowire.
9. A stack for a semiconductor device, the stack comprising:
a plurality of sacrificial layers, each sacrificial layer comprising a first lattice parameter, a first end, a second end, and a cross-sectional area, the cross-sectional area being positioned in a direction substantially perpendicular to a direction between the first end and the second end of each sacrificial layer, the cross-sectional area of each sacrificial layer comprising a first thickness and a first width substantially perpendicular to the first thickness, the first thickness of each sacrificial layer being less than a metastable critical thickness of a sacrificial layer material, wherein the first end and the second end of each sacrificial layer are opposite each other in the first direction;
at least one channel layer comprising a second lattice parameter, a first end, a second end, and a cross-sectional area, the cross-sectional area being positioned in a direction substantially perpendicular to a direction between the first end and the second end of the at least one channel layer, the second lattice parameter being different from the first lattice parameter, each channel layer being disposed between and in contact with two sacrificial layers, the cross-sectional area of each channel layer comprising a second thickness and a second width substantially perpendicular to the second thickness, the second thickness of each channel layer being less than a metastable critical thickness of a channel layer material, wherein the first end and the second end of each channel layer are opposite each other in the first direction; and
an underlying layer, on which the plurality of sacrificial layers and the at least one channel layer are disposed, the sacrificial layers being in contact with the underlying layer, the underlying layer producing substantially no defects in the plurality of sacrificial layers and the at least one channel layer other than defects present in the underlying layer extending toward any of the stack,
wherein the stack further includes a source/drain structure disposed at and contacting each of the first and second ends of the at least one channel layer, the plurality of sacrificial layers and the at least one channel layer being alternately stacked in a second direction, the first direction crossing the second direction,
wherein the stack further includes a plurality of internal spacers disposed between the first end of each sacrificial layer and the source/drain structure and between the second end of each sacrificial layer and the source/drain structure.
10. The stack for a semiconductor device according to claim 9, wherein the lower layer further comprises a third lattice parameter that substantially matches a lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were allowed to relax coherently.
11. The stack for a semiconductor device according to claim 9, wherein the first lattice parameter is larger than the second lattice parameter.
12. The stack for a semiconductor device according to claim 9, wherein the first lattice parameter is smaller than the second lattice parameter.
13. The stack for a semiconductor device according to claim 9, wherein the plurality of sacrificial layers include at least one nanosheet,
wherein the at least one channel layer comprises at least one nanoplate.
14. The stack for a semiconductor device according to claim 9, wherein the plurality of sacrificial layers comprises at least one nanowire,
wherein the at least one channel layer comprises at least one nanowire.
15. The stack for a semiconductor device according to claim 9, wherein a first distance between a first end and a second end of at least one of the plurality of sacrificial layers is smaller than a second distance between the first end and the second end of the at least one channel layer.
16. A method of forming a stack for a semiconductor device, the method comprising:
providing a lower layer;
forming a stack of a plurality of sacrificial layers and at least one channel layer on the lower layer, the sacrificial layers being in contact with the lower layer, each sacrificial layer comprising a first lattice parameter, the at least one channel layer comprising a second lattice parameter different from the first lattice parameter, each channel layer being disposed between and in contact with two sacrificial layers, wherein the plurality of sacrificial layers and the at least one channel layer are alternately stacked in a first direction;
forming a first patterned stack and a second patterned stack by patterning the stacks with a space therebetween, wherein each of the first and second patterned stacks includes a plurality of sacrificial patterns and at least one channel pattern;
forming a plurality of undercut portions and a plurality of recessed sacrificial patterns by partially removing the plurality of sacrificial patterns through the space;
forming a plurality of internal spacers to fill the plurality of undercut portions,
forming a source/drain structure in the space after forming the plurality of internal spacers,
wherein each of the plurality of internal spacers is formed between the source/drain structure and the sacrificial pattern of each recess, and
wherein the underlying layer includes a third lattice parameter that substantially matches a lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were allowed to consecutively relax.
17. The method of claim 16, wherein an underlying layer produces substantially no defects in the plurality of sacrificial layers and the at least one channel layer other than any propagation of defects present in the underlying layer into the stack.
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| US201562200335P | 2015-08-03 | 2015-08-03 | |
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| US15/086,015 US10283638B2 (en) | 2015-08-03 | 2016-03-30 | Structure and method to achieve large strain in NS without addition of stack-generated defects |
| US15/086,015 | 2016-03-30 |
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