CN106409890B - The forming method of fin bipolar junction transistor - Google Patents

Abstract

A method for forming a fin bipolar junction transistor, comprising: providing a semiconductor substrate; forming a collector fin, a base fin and an emitter fin on the surface of the semiconductor substrate, and the base fin is located between the collector fin and the emitter fin the collector fin, the base fin and the emitter fin are parallel to each other; a base epitaxial layer is formed on the surface of the base fin; a collector epitaxial layer is formed on the surface of the collector fin; and base fin ions are doped in the base epitaxial layer; collector fin ions are doped in the collector fin and collector epitaxial layer; first emitter ions and second emitter ions are doped in the emitter fin ion, the second emitter ion is located at the top of the emitter fin, the first emitter ion is located at the bottom of the second emitter ion, and the concentration of the second emitter ion is greater than that of the first emitter ion concentration. The method for forming the fin bipolar junction transistor improves the performance of the fin bipolar junction transistor.

Description

Method for forming fin bipolar junction transistor

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a fin bipolar junction transistor.

Background technique

Bipolar junction transistor (Bipolar Junction Transistor, BJT), also known as semiconductor triode, is composed of two PN junctions adjacent to each other and back-to-back, and is divided into two combined structures of PNP and NPN. Bipolar junction transistors have three poles: collector, emitter and base. The bipolar junction transistor has the function of amplifying the signal, which is mainly realized by the fact that the emitter current can be transmitted through the base region to the collector region. Bipolar transistors are widely used because of their ability to amplify signals, better power control, high-speed operation, and durability.

MOS transistors are one of the most important components in modern integrated circuits. MOS transistors generate switching signals by applying a voltage to adjust the current through the channel.

Generally, a bipolar junction transistor and a MOS transistor are integrated together to constitute a semiconductor device.

With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current is weakened, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering part of the top and sidewalls of the fin, and a gate structure located at the gate. The source region in the fin on one side of the electrode structure and the drain region in the fin on the other side of the gate structure. Fin-type field effect transistors can replace planar MOS transistors because they can greatly improve the circuit and reduce leakage current.

In order to make the process of preparing the bipolar junction transistor compatible with the process of preparing the fin field effect transistor, in the prior art, the fin bipolar junction transistor is prepared by combining the fin bipolar junction transistor and the fin field effect transistor. integrated together.

However, as the feature size is further reduced, the fin bipolar junction transistors formed in the prior art have poor performance.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a method for forming a fin bipolar junction transistor to improve the performance of the fin bipolar junction transistor.

In order to solve the above problems, the present invention provides a method for forming a fin bipolar junction transistor, including: providing a semiconductor substrate; forming a collector fin, a base fin and an emitter fin on the surface of the semiconductor substrate, and the base The fin is located between the collector fin and the emitter fin, and the collector fin, the base fin and the emitter fin are parallel to each other; a base epitaxial layer is formed on the surface of the base fin; a collector fin is formed on the surface of the collector fin Electrode epitaxial layer; doping base fin ions in the base fin and base epitaxial layer; doping collector fin ions in the collector fin and collector epitaxial layer; doping in the emitter fin mix a first emitter ion and a second emitter ion, the second emitter ion on top of the emitter fin, the first emitter ion on the bottom of the second emitter ion, and the second emitter ion The concentration of the ions is greater than the concentration of the first emitter ions.

Optionally, the base fin surrounds the emitter fin, and the collector fin surrounds the base fin.

Optionally, when the number of the base fins is multiple, the multiple base fins are parallel to each other; when the number of the collector fins is multiple, the multiple collector fins are parallel to each other; When the number of the emitter fins is plural, the plural emitter fins are parallel to each other.

Optionally, the fin bipolar junction transistor is a PNP fin bipolar junction transistor.

Optionally, the concentration of the second emitter ion is 1E15 atom/cm ² to 3E15 atom/cm ² ; the concentration of the first emitter ion is 3E14 atom/cm ² to 1E15 atom/cm ² .

Optionally, the first emitter ions and the second emitter ions are P-type ions.

Optionally, the process of doping the emitter fin with the first emitter ions is a first emitter ion implantation process; the process of doping the emitter fin with the second emitter ions is the second emitter ion implantation craft.

Optionally, the ions used in the first emitter ion implantation process are B ions, the implantation energy is 3KeV˜5KeV, the implantation dose is 3E14atom/cm ² ˜1E15atom/cm ² , and the implantation angle is 0°˜7°.

Optionally, the ions used in the first emitter ion implantation process are BF ₂ ions, the implantation energy is 8KeV˜15KeV, the implantation dose is 3E14atom/cm ² ˜1E15atom/cm ² , and the implantation angle is 0°˜7°.

Optionally, the ions used in the second emitter ion implantation process are B ions, the implantation energy is 1KeV˜3KeV, the implantation dose is 1E15atom/cm ² ˜3E15atom/cm ² , and the implantation angle is 0°˜7°.

Optionally, the ions used in the second emitter ion implantation process are BF ₂ ions, the implantation energy is 4KeV˜7KeV, the implantation dose is 1E15atom/cm ² ˜3E15atom/cm ² , and the implantation angle is 0°˜7°.

Optionally, the material of the collector epitaxial layer is silicon germanium; the material of the base epitaxial layer is silicon carbide.

Optionally, the base fin ions are N-type ions; the collector fin ions are P-type ions.

Optionally, the concentration of the base fin ions is 5E14 atoms/cm ² to 1E15 atoms/cm ² ; the concentration of the collector fin ions is 3E14 atoms/cm ² to 1E15 atoms/cm ² .

Optionally, the process of doping the base fin and the base epitaxial layer with base fin ions is a base fin ion implantation process; the process of doping the collector fin and the collector epitaxial layer with collector fin ions For the collector fin ion implantation process.

Optionally, the ions used in the base fin ion implantation process are P ions, the implantation energy is 6KeV-10KeV, the implantation dose is 5E14atom/ ^cm2-1E15atom / ^cm2 , and the implantation angle is 0-7 degrees Celsius.

Optionally, the ions used in the collector fin ion implantation process are B ions, the implantation energy is 3KeV˜5KeV, the implantation dose is 3E14atom/cm ² ˜1E15atom/cm ² , and the implantation angle is 0°C to 7°C.

Optionally, the semiconductor substrate includes a first well region and a second well region connected to the first well region in a horizontal direction, the second well region and the first well region are doped with opposite types of ions, The collector fin is located on the surface of the first well region, and the ions of the collector fin are of the same type as the ions doped in the first well region, and the base fin and the emitter fin are located on the surface of the second well region.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a fin bipolar junction transistor provided by the present invention, a first emitter ion and a second emitter ion are formed in an emitter fin, and the second emitter ion is located on the top of the emitter fin and the second emitter ion is formed. The concentration of the emitter ions is greater than the concentration of the first emitter ions, and the second emitter ions can reduce the contact barrier between the electrode and the emitter fin subsequently formed on the top surface of the emitter fin.

Further, when the number of the emitter fins is multiple, since there is no need to form an emitter epitaxial layer on the surface of the emitter fin, the adjacent emitter epitaxial layers can be effectively avoided due to the need to form an emitter epitaxial layer. The phenomenon of connection between them can effectively avoid the reduction of the total current through the emitter fin and the degradation of the stability of the fin bipolar junction transistor.

Description of drawings

1 to 3 are schematic diagrams illustrating a process of forming a fin bipolar junction transistor according to an embodiment of the present invention;

4 to 9 are schematic diagrams illustrating a process of forming a fin bipolar junction transistor according to another embodiment of the present invention.

Detailed ways

As the feature size is further reduced, the fin bipolar junction transistors formed by the prior art have poor performance.

An embodiment of the present invention provides a method for forming a fin bipolar junction transistor. Referring to FIGS. 1 to 3 , FIG. 2 is a cross-sectional view along the axis Y1-Y2 in FIG. 1 , and FIG. 3 is based on FIG. 2 . The schematic diagram of formation includes: providing a semiconductor substrate 100; forming a plurality of parallel emitter fins 110, a plurality of parallel base fins 120 and a plurality of parallel collector fins 130 on the surface of the semiconductor substrate 100, the The plurality of base fins 120 surround the plurality of emitter fins 110 , the plurality of collector fins 130 surround the plurality of base fins 120 , and the emitter fins 110 , the base fins 120 and the collector fins 130 are each other Parallel; an emitter epitaxial layer 111 is formed on the surface of the emitter fin 110 ; a base epitaxial layer 121 is formed on the surface of the base fin 120 ; a collector epitaxial layer 131 is formed on the surface of the collector fin 130 .

The semiconductor substrate 100 includes a well region 101, the well region 101 includes a first well region 1011 and a second well region 1012 connected to the first well region 1011 in the horizontal direction, and the collector fin 130 is located on the The surface of a well region 1011 , the base fin 120 and the emitter fin 110 are located on the surface of the second well region 1012 . The surface of the semiconductor substrate 100 also has an isolation structure 102 , the surface of the isolation structure 102 is lower than the top surfaces of the emitter fin 110 , the base fin 120 and the collector fin 130 , and the isolation structure 102 is used to electrically isolate the emitter fin 110 , the base fin 120 and the collector fin 130 . Base fin 120 and collector fin 130 .

Due to the large area of the emitter epitaxial layer 111 , the emitter epitaxial layer 111 can reduce the resistance between the electrodes formed on the top surface of the emitter epitaxial layer 111 and the emitter fins 110 subsequently. When the fin bipolar junction transistor is a PNP fin bipolar junction transistor, the material of the emitter epitaxial layer 111 is silicon germanium.

The study found that the reasons for the poor performance and reliability of the fin bipolar junction transistor formed by the above method are:

The emitter fin is located in the central region of the semiconductor substrate, and the base fin and the collector fin are located in the peripheral region of the semiconductor substrate relative to the position of the emitter fin in the semiconductor substrate. In the process of forming the emitter epitaxial layer, base epitaxial layer and collector epitaxial layer, the distribution of each precursor gas used to form the emitter epitaxial layer, base epitaxial layer and collector epitaxial layer has common characteristics: The density of the precursor gas above the central region of the semiconductor substrate is greater than that of the precursor gas above the peripheral region of the semiconductor substrate, so the rate of formation of the emitter epitaxial layer is higher, and the adjacent emitter epitaxial layers are easily connected to each other. On the other hand, due to the large number of emitter fins in the cross section through the Y1-Y2 axis in FIG. 1, the probability of connecting adjacent emitter epitaxial layers is high, as long as the adjacent emitter epitaxial layers occur at one place The phenomenon of connection will accelerate the rate of formation of the emitter epitaxial layer, which may lead to the connection of the entire emitter epitaxial layer. On the other hand, when the fin bipolar junction transistor is a PNP fin bipolar junction transistor, the material of the emitter epitaxial layer is silicon germanium, the growth rate of silicon germanium in different directions is different, and the emission rate is different. The cross-sectional shape of the epitaxial layer in the direction perpendicular to the sidewall of the emitter fin is hexagonal, so that adjacent emitter epitaxial layers are easily connected to each other. Adjacent emitter epitaxial layer connections lead to the following disadvantages: the total current through the emitter fin is reduced; the condition of the emitter epitaxial layer connection in different fin bipolar junction transistors cannot be controlled, resulting in the performance of fin bipolar junction transistors stability deteriorates.

On this basis, another embodiment of the present invention provides a method for forming a fin bipolar junction transistor, including: providing a semiconductor substrate; forming a collector fin, a base fin and a plurality of parallel emitter fins, the base fin is located between the collector fin and the plurality of emitter fins, the collector fin, the base fin and the emitter fin are parallel to each other; the base fin is formed on the surface of the base fin an epitaxial layer; forming a collector epitaxial layer on the surface of the collector fin; doping the base fin ions in the base fin and the base epitaxial layer; doping the collector fin and the collector epitaxial layer Electrode fin ions; first emitter ions and second emitter ions are doped in the emitter fins, the second emitter ions are located on the top of the emitter fins, and the first emitter ions are located in the second emitter ions The bottom of the electrode ions, and the concentration of the second emitter ions is greater than the concentration of the first emitter ions.

Compared with the previous embodiment, since the first emitter ions and the second emitter ions are formed in the emitter fin, the second emitter ions are located on the top of the emitter fin and the concentration of the second emitter ions is greater than that of the first emitter ions. The concentration of the emitter ions, the second emitter ions can lower the contact barrier between the electrodes subsequently formed on the top surfaces of the emitter fins and the emitter fins. In addition, since there is no need to form an emitter epitaxial layer on the surface of the emitter fin, the phenomenon of connection between adjacent emitter epitaxial layers due to the need to form an emitter epitaxial layer can be effectively avoided, thereby effectively avoiding the need to pass through the emitter. The total current of the fin is reduced and the stability of the fin bipolar junction transistor is degraded.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 4 and FIG. 5 in combination, FIG. 5 is a cross-sectional view along the Y3-Y4 axis in FIG. 4 , providing a semiconductor substrate 200 ; a collector fin 230 and a base fin 220 are formed on the surface of the semiconductor substrate 200 And the emitter fin 210, the base fin 220 is located between the collector fin 230 and the emitter fin 210, and the emitter fin 210, the base fin 220 and the collector fin 230 are parallel to each other.

The number of the base fins 220 is one or more; the number of the collector fins 230 is one or more, and the number of the emitter fins 210 is one or more. When the number of the base fins 220 is multiple, the respective base fins 220 are parallel to each other; when the number of the collector fins 230 is multiple, the respective collector fins 230 are parallel to each other, when the emitter fins 230 are multiple When the number of the emitter fins 210 is plural, the respective emitter fins 210 are parallel to each other.

In this embodiment, the arrangement of the emitter fins 210, the base fins 220 and the collector fins 230 is as follows: the base fins 220 surround the emitter fins 210, and the collector fins 230 surround the base fins 220. The method enables the collector fin 210 to collect current from all directions, the total current passing through the collector fin 210 is larger, and the leakage current is reduced; in another embodiment, the emitter fin 210, the base fin 220 and the collector The arrangement of the fins 230 is as follows: the base fin 220 is located only on one side of the emitter fin 210 , the collector fin 230 is located only on one side of the base fin 220 , and the base fin 220 is located between the emitter fin 210 and the emitter fin 210 between.

In this embodiment, the formation of a PNP type fin bipolar transistor is taken as an example for description. In other embodiments, an NPN type fin type bipolar transistor may also be formed.

The semiconductor substrate 200 provides a process platform for the subsequent formation of fin bipolar junction transistors.

The semiconductor substrate 200 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 can also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide; the semiconductor substrate 200 can be a bulk material , can also be a composite structure, such as silicon-on-insulator; the semiconductor substrate 200 can also be other semiconductor materials, which will not be exemplified here. In this embodiment, the material of the semiconductor substrate 200 is silicon.

The semiconductor substrate 200 has a well region 201, the well region 201 includes a first well region 2011 and a second well region 2012 connected to the first well region 2011 in the horizontal direction, the second well region 2012 and The types of ions doped in the first well region 2011 are opposite.

The functions of the first well region 2011 and the second well region 2012 are as follows: the first well region 2011 is connected with the collector fins formed subsequently to form a collector region; the second well region 2012 is connected with the base fins and the subsequently formed electrode fins. The emitter fins are connected, and the second well region 2012 and the base fin together constitute a base region.

In this embodiment, since the type of the fin bipolar junction transistor is PNP, the first well region 2011 is a P well, and the second well region 2012 is an N well.

In this embodiment, the first well region 2011 and the second well region 2012 are doped with ions.

The first well region 2011 is doped with P-type ions, such as B ions or In ions. In this embodiment, the P-type ions doped in the first well region 2011 are B ions. The concentration of the doped P-type ions in the first well region 2011 is 1E13 atom/cm ² to 1E14 atom/cm ² .

The second well region 2012 is doped with N-type ions, such as P (phosphorus) ions or As ions. In this embodiment, the N-type ions doped in the second well region 2012 are P ions. The concentration of N-type ions doped in the second well region 2012 is 1E13 atom/cm ² to 1E14 atom/cm ² .

The functions of forming the emitter fin 210 , the base fin 220 and the collector fin 230 are: the emitter fin 210 is used to form a part of the subsequent emitter region, and the base fin 220 is used to form a part of the subsequent base region , the collector fin 230 is used to form the collector region, and the process of forming the fin bipolar junction transistor can be compatible with the process of the fin field effect transistor.

In this embodiment, the material of the emitter fins 210 , the base fins 220 and the collector fins 230 is silicon; in other embodiments, the emitter fins 210 , the base fins 220 and the collector fins 230 can be selected from other semiconductor materials.

The emitter fins 210 and the base fins 220 are both located on the surface of the second well region 2012, so that both the emitter fins 210 and the base fins 220 are electrically connected to the second well region 2012; the collector fins 230 are located in the first well region the surface of the region 2011 so that the collector fin 230 is electrically connected to the first well region 2011 .

The steps of forming the emitter fin 210 , the base fin 220 and the collector fin 230 are: forming a fin material layer (not shown) on the surface of the semiconductor substrate 200 ; forming a patterned fin material layer on the surface of the fin material layer photoresist, the patterned photoresist defines the positions of the emitter fin 210, the base fin 220 and the collector fin 230; using the patterned photoresist as a mask, the fins are etched The material layer is until the surface of the semiconductor substrate 200 is exposed to form the emitter fin 210 , the base fin 220 and the collector fin 230 .

In this embodiment, in the cross section through the Y3-Y4 axis in FIG. 4 , the number of the emitter fins 210 is 7, the number of the base fins 220 is 3, and the number of the collector fins 230 is 3 As an example, it does not represent the number of emitter fins 210 , base fins 220 and collector fins 230 passing through the Y3-Y4 axis in the actual process. In the actual process, in the cross section through the Y3-Y4 axis, an appropriate number of emitter fins 210 , base fins 220 and collector fins 230 can be selected according to the situation.

It should be noted that the magnification of the fin bipolar junction transistor is the ratio of the total current passing through the emitter fin 210 to the total current passing through the base fin 220 , in order to make the magnification of the fin bipolar junction transistor larger , in the cross section through the Y3-Y4 axis, the number of emitter fins 210 is greater than the number of base fins 220 . And for the distribution of the collector fins 230, it is necessary to ensure that the area of the collector region is large, so the collector fins 230 are distributed in the peripheral area of the semiconductor substrate 200, and the number of the collector fins 230 is considered to reduce the manufacturing cost. For this reason, the number of collector fins 230 is chosen to be smaller than the number of emitter fins 210 in the cross section through the Y3-Y4 axis.

The surface of the semiconductor substrate 200 also has an isolation structure 202, the surface of the isolation structure 202 is lower than the top surfaces of the emitter fin 210, the base fin 220 and the collector fin 230, and the isolation structure 202 is used for electrically isolating the emitter fin 210, Base fin 220 and collector fin 230 .

Referring to FIG. 6 , a base epitaxial layer 221 is formed on the surface of the base fin 220 ; a collector epitaxial layer 231 is formed on the surface of the collector fin 230 .

The function of forming the base epitaxial layer 221 is: due to the large area of the base epitaxial layer 221 , the base epitaxial layer 221 can reduce the gap between the base fin 220 and the electrodes formed on the surface of the base epitaxial layer 221 subsequently. The resistance.

The function of forming the collector epitaxial layer 231 is: due to the large area of the collector epitaxial layer 231 , the base epitaxial layer 221 can reduce the gap between the collector fins 230 and the electrodes subsequently formed on the surface of the collector epitaxial layer 231 The resistance.

In this embodiment, since the type of the fin bipolar junction transistor used for forming is PNP type, the material of the base epitaxial layer 221 is selected to be silicon carbide, and the material of the collector epitaxial layer 231 is germanium Silicone. In other embodiments, the material of the base epitaxial layer 221 may be other materials, and the material of the collector epitaxial layer 231 may be other materials.

The base epitaxial layer 221 may be formed first, and then the collector epitaxial layer 231 may be formed; or the collector epitaxial layer 231 may be formed first, and then the base epitaxial layer 221 may be formed. In this embodiment, the base epitaxial layer 221 is formed first, and then the collector epitaxial layer 231 is formed.

When forming the base epitaxial layer 221, a first barrier layer (not shown) needs to be formed, the first barrier layer exposes the entire number of the base fins 220, and for each base fin 220, the first barrier layer The layer may expose part of the area of each base fin 220, or may expose the entire area of each base fin 220. In this embodiment, for each base fin 220, the first barrier layer exposes each base fin 220. Part of the area of the fin 220 . In addition, the first barrier layer covers the collector fins 230 and the emitter fins 210 . The first barrier layer is used to protect the collector fins 230 and the emitter fins 210 when the base epitaxial layer 221 is formed. After the base epitaxial layer 221 is formed, the first barrier layer is removed.

In this embodiment, the material of the first barrier layer is silicon nitride, and in other embodiments, the material of the first barrier layer may be other materials.

The method for forming the base epitaxial layer 221 is an epitaxial growth process.

In this embodiment, the material of the base epitaxial layer 221 is silicon carbide, and the specific process parameters of the epitaxial growth of the base epitaxial layer 221 are as follows: the gases used are SiH ₄ , CH ₄ and H ₂ , and the flow rate of SiH ₄ is 800sccm ~1000sccm, the flow rate of _CH4 is 800sccm~1000sccm, the flow rate of _H2 is 50sccm~1000sccm, the chamber pressure is 5mtorr~50mtorr, and the temperature is 500~800 degree Celsius.

When forming the collector epitaxial layer 231, a second barrier layer (not shown) needs to be formed, the second barrier layer exposes the entire number of collector fins 230, and for each collector fin 230, the second barrier layer The layer may expose part of the area of each collector fin 230, or may expose the entire area of each collector fin 230. In this embodiment, for each collector fin 230, the second barrier layer exposes each collector fin 230. the entire area of the fins 230 . In addition, the second barrier layer covers the base fin 220 and the emitter fin 210 . The second barrier layer is used to protect the base fin 220 and the emitter fin 210 when the collector epitaxial layer 231 is formed. After the collector epitaxial layer 231 is formed, the second barrier layer is removed.

In this embodiment, the material of the second barrier layer is silicon nitride, and in other embodiments, the material of the second barrier layer may be other materials.

The method for forming the collector epitaxial layer 231 is an epitaxial growth process.

In this embodiment, the material of the collector epitaxial layer 231 is silicon germanium, and the specific process parameters of the epitaxial growth of the collector epitaxial layer 231 are: the gases used are GeH ₄ , SiH ₄ and H ₂ , and the flow rate of GeH ₄ is 800sccm～1000sccm, the flow rate of _SiH4 is 800sccm～1000sccm, the flow rate of _H2 is 50sccm～1000sccm, the chamber pressure is 5mtorr～50mtorr, and the temperature is 500℃～800℃.

Referring to FIG. 7 , the base fins 220 and the base epitaxial layer 221 are doped with base fin ions 222 , and the collector fins 230 and the collector epitaxial layer 231 are doped with collector fin ions 232 .

The function of the base fin ions 222 is to reduce the resistance of the base fin 220 and the base epitaxial layer 221 ; the function of the collector fin ions 232 is to reduce the resistance of the collector fin 230 and the collector epitaxial layer 231 .

The concentration of the base fin ions 222 is 5E14 atom/cm ² -1E15 atom/cm ² ; the concentration of the collector fin ions 232 is 3E14 atom/cm ² -1E15 atom/cm ² .

In this embodiment, the base fins 220 and the base epitaxial layer 221 are first doped with base fin ions 222 , and then the collector fins 230 and the collector epitaxial layer 231 are doped with collector fin ions 232 . In other embodiments, the collector fins 230 and the collector epitaxial layer 231 may be doped with collector fin ions 232 first, and then the base fins 220 and the base epitaxial layer 221 may be doped with base fins Ion 222. In this embodiment, the base fin 220 and the base epitaxial layer 221 are doped with base fin ions 222 by a base fin ion implantation process, and the base fin ions 222 are N-type ions, such as P or As . In a specific embodiment, the process parameters of the base fin ion implantation process are: the ions used are P ions, the implantation energy is 6KeV-10KeV, the implantation dose is 5E14atom/cm ² ～1E15atom/cm ² , and the implantation angle is It is 0 degree Celsius to 7 degree Celsius, and the implantation angle is the angle between the injection angle and the normal direction of the semiconductor substrate 200 .

It should be noted that, in this embodiment, the base fin ions 222 are implanted into the entire base fin 220 and the base epitaxial layer 221; in other embodiments, the base fin ions 222 may be implanted into a part of the base In the fin 220 and the base epitaxial layer 221 , during the subsequent annealing process, the base fin ions 222 are diffused and distributed throughout the base fin 220 and the base epitaxial layer 221 .

In other embodiments, the base fin ions 222 may be doped in-situ while the base epitaxial layer 221 is epitaxially grown. During the subsequent annealing process, the base fin ions 222 diffuse into the entire base. in the pole fin 220 .

In this embodiment, the collector fin 230 and the collector epitaxial layer 231 are doped with collector fin ions 232 by using a collector fin ion implantation process, and the collector fin ions 232 are P-type ions, such as B or In . In a specific embodiment, the process parameters of the collector fin ion implantation process are: the ions used are B ions, the implantation energy is 3KeV-5KeV, the implantation dose is 3E14atom/cm ² ～1E15atom/cm ² , and the implantation angle is It is 0 degree Celsius to 7 degree Celsius, and the implantation angle is the angle between the injection angle and the normal direction of the semiconductor substrate 200 .

It should be noted that, in this embodiment, the collector fin ions 232 are implanted into the entire collector fin 230 and the collector epitaxial layer 231; in other embodiments, the collector fin ions 232 may be implanted in part of the In the collector fin 230 and part of the collector epitaxial layer 231 , in the subsequent annealing process, the collector fin ions 232 are diffused and distributed in the entire collector fin 230 and the collector epitaxial layer 231 .

In other embodiments, the collector fin ions 232 may be in-situ doped while the collector epitaxial layer 231 is epitaxially grown. During the subsequent annealing process, the collector fin ions 232 diffuse into the entire collector. in the electrode fins 230 .

It should be noted that the fin bipolar junction transistor has a base region and a collector region. In this embodiment, the second well region 2012 , the base fin 220 doped with the base fin ions 222 and the base epitaxy The layer 221 constitutes the base region of the fin bipolar junction transistor, and the first well region 2011 , the collector fin 230 doped with collector fin ions 232 and the collector epitaxial layer 231 constitute the fin bipolar junction transistor. the collector area.

It should be noted that, in the present invention, the base epitaxial layer 221 may not be formed on the surface of the base fin 220, but the base fin 220 may be doped with the first base fin ions and the second base fin ions. The second base fin ions are located at the top of the base fin 220 , the first base fin ions are located at the bottom of the second base fin ions, and the concentration of the second base fin ions is greater than that of the first base fin ions. In a specific embodiment, the concentration of the second base fin ions is 1E15 atom/cm ² to 3E15 atom/cm ² , and the concentration of the first base fin ions is 5E14 atom/cm ² to 1E15 atom/cm ² . The functions of the second base fin ions and the first base fin ions are: reducing the resistance of the base fin 220 and forming a concentration gradient in the base fin 220 to reduce the base fin 220 and the subsequent The contact barrier between electrodes formed on the surface.

In the present invention, the collector epitaxial layer 231 may not be formed on the surface of the collector fins 230 , but the collector fins 230 are doped with first collector fin ions and second collector fin ions, and the second collector fin ions Located on top of the collector fin 230, the first collector fin ions are located at the bottom of the second collector fin ions, and the concentration of the second collector fin ions is greater than that of the first collector fin ions. In a specific embodiment, the concentration of the second collector fin ions is 1E15 atom/cm ² to 3E15 atom/cm ² , and the concentration of the first collector fin ions is 3E14 atom/cm ² to 1E15 atom/cm ² . The functions of the second collector fin ions and the first collector fin ions are to reduce the resistance of the collector fins 230 and form a concentration gradient in the collector fins 230 to reduce the collector fins 230 and subsequently the collector fins 230 The contact barrier between electrodes formed on the surface.

Referring to FIG. 8 , the emitter fin 210 is doped with first emitter ions to form a first emitter ion region 211 ; the emitter fin 210 is doped with second emitter ions to form a second emitter The ion region 212, the second emitter ion region 212 is located at the top of the emitter fin 210, the first emitter ion region 211 is located at the bottom of the second emitter ion region 212, the concentration of the second emitter ion greater than the concentration of the first emitter ions.

The function of the first emitter ions is to form a PN junction between the emitter fins 210 doped with the first emitter ions and the second well region 2012 . The role of the second emitter ions is to form a concentration gradient in the emitter fins 210 and reduce the contact barrier between the emitter fins 210 and the electrodes formed on the surface of the emitter fins 210 subsequently.

In this embodiment, since the emitter epitaxial layer does not need to be formed on the surface of the emitter fin 210, the phenomenon of connection between the emitter epitaxial layers caused by the need to form the emitter epitaxial layer can be effectively avoided, and the emitter fin can be effectively avoided. The reduction of the current in the fin bipolar junction transistor and the degradation of the stability of the fin bipolar junction transistor.

In addition, a first emitter ion and a second emitter ion are formed in the emitter fin 210, the second emitter ion is located on the top of the emitter fin 210 and the concentration of the second emitter ion is greater than that of the first emitter ion Since the concentration gradient is formed in the emitter fin 210 , the contact barrier between the electrode formed on the top surface of the emitter fin 210 and the emitter fin 210 can be lowered.

The emitter fins 210 are doped with first emitter ions by a first emitter ion implantation process, and the second emitter ions are doped in the emitter fins 210 by a second emitter ion implantation process. The second emitter ion implantation process is performed, and then the first emitter ion implantation process is performed; in other embodiments, the first emitter ion implantation process may be performed first, and then the second emitter ion implantation process is performed.

In this embodiment, since the type of the fin bipolar junction transistor used for forming is PNP type, the first emitter ions and the second emitter ions are P-type ions, such as B or In. The concentration of the emitter ions is 3E14 atom/cm ² to 1E15 atoms/cm ² , and the concentration of the second emitter ions is 1E15 atoms/cm ² to 3E15 atoms/cm ² .

In a specific embodiment, the process parameters of the first emitter ion implantation process are: the used ions are B ions, the implantation energy is 3KeV～5KeV, the implantation dose is 3E14atom/cm ² ～1E15atom/cm ² , the implantation The angle is 0 degrees Celsius to 7 degrees Celsius; in another specific embodiment, the process parameters of the first emitter ion implantation process are: the ions used are BF ₂ ions, the implantation energy is 8KeV～15KeV, and the implantation dose is 3E14atom /cm ² ～1E15atom/cm ² , and the injection angle is 0 degrees Celsius to 7 degrees Celsius. The implantation angle is the included angle with the normal line of the semiconductor substrate 200 .

In a specific embodiment, the process parameters of the second emitter ion implantation process are: the used ions are B ions, the implantation energy is 1KeV～3KeV, the implantation dose is 1E15atom/cm ² ～3E15atom/cm ² , the implantation The angle is 0 degrees Celsius to 7 degrees Celsius; in another specific embodiment, the process parameters of the second emitter ion implantation process are: the ions used are BF ₂ ions, the implantation energy is 4KeV～7KeV, 1E15atom/cm ² ～3E15atom/cm ² , the injection angle is 0℃～7℃. The implantation angle is the included angle with the normal line of the semiconductor substrate 200 .

In this embodiment, the first emitter ions are implanted into the entire volume of the emitter fin 210 at the bottom of the second emitter ion region 212; in other embodiments, the first emitter ions are implanted into the second emitter ion region 212. Part of the volume of the emitter fin 210 region at the bottom of the emitter ion region 212 . When the first emitter ions are implanted into the partial volume of the emitter fin 210 region at the bottom of the second emitter ion region 212, after subsequent annealing treatment, the first emitter ions will diffuse, and the second emitter ions will The emitter fins 210 at the bottom of the region 212 are all distributed.

It should be noted that the fin bipolar junction transistor has an emitter region. In this embodiment, the emitter fin 210 doped with the first emitter ions and the second emitter ions constitutes the emitter region of the fin bipolar junction transistor. .

It should be noted that, in this embodiment, the base fin 220 and the base epitaxial layer 221 are first doped with base fin ions, and the collector fin 230 and the collector epitaxial layer 231 are doped with collector ions fin ions, and then the emitter fins 210 are doped with first emitter ions and second emitter ions; in other embodiments, the emitter fins 210 can be doped with first emitter ions and second emitter ions first; For the second emitter ions, the base fins 220 and the base epitaxial layer 221 are then doped with base fin ions, and the collector fins 230 and the collector epitaxial layer 231 are doped with collector fin ions. Alternatively, when the concentration of the collector fin ions and the first emitter ions are the same, the collector fin ions and the first emitter ions may be doped simultaneously. Alternatively, when the concentration of the first collector fin ions and the first emitter ions are the same, the first collector fin ions and the first emitter ions may be doped at the same time; when the second collector fin ions have the same concentration When the concentration is the same as that of the second emitter ions, the second collector fin ions and the second emitter ions can be doped simultaneously.

In this embodiment, the method further includes: after doping the base fin ions, the collector fin ions, the first emitter ions and the second emitter ions, annealing the doped ions together to activate the doping ion. In other embodiments, annealing is performed after doping the base fin ions, annealing is performed after doping the collector fin ions, and annealing is performed after the first emitter ions and the second emitter ions are completed deal with.

Referring to FIG. 9, electrodes 240 are formed on the top surface of the emitter fin 210, the top surface of the base epitaxial layer 221 and the top surface of the collector epitaxial layer 231;

The electrodes 240 are used to transmit electrical signals.

The material of the electrode 240 is metal, such as copper, aluminum or tungsten. In this embodiment, the material of the electrode 240 is tungsten.

The formation process of the electrode 240 is a deposition process, such as physical vapor deposition, and the formation process of the electrode 240 may also be an electroplating process, which will not be repeated here.

To sum up, the technical solution of the present invention has the following advantages:

In the method for forming a fin bipolar junction transistor provided by the present invention, a first emitter ion and a second emitter ion are formed in an emitter fin, and the second emitter ion is located on the top of the emitter fin and the second emitter ion is formed. The concentration of the emitter ions is greater than the concentration of the first emitter ions, and the second emitter ions can reduce the contact barrier between the electrode and the emitter fin subsequently formed on the top surface of the emitter fin.

Further, when the number of the emitter fins is multiple, since there is no need to form an emitter epitaxial layer on the surface of the emitter fin, the adjacent emitter epitaxial layers can be effectively avoided due to the need to form an emitter epitaxial layer. The phenomenon of connection between them can effectively avoid the reduction of the total current through the emitter fin and the degradation of the stability of the fin bipolar junction transistor.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (18)

1. A method for forming a fin bipolar junction transistor, comprising: provide semiconductor substrates; A collector fin, a base fin and an emitter fin are formed on the surface of the semiconductor substrate, the base fin is located between the collector fin and the emitter fin, and the collector fin, the base fin and the emitter fin are parallel to each other; forming a base epitaxial layer on the surface of the base fin; forming a collector epitaxial layer on the surface of the collector fin; doping base fin ions in the base fin and base epitaxial layer; doping collector fin ions in the collector fin and collector epitaxial layer; Doping the emitter fin with a first emitter ion and a second emitter ion, the second emitter ion at the top of the emitter fin, the first emitter ion at the bottom of the second emitter ion , and the concentration of the second emitter ions is greater than the concentration of the first emitter ions. 2 . The method of claim 1 , wherein the base fin surrounds the emitter fin, and the collector fin surrounds the base fin. 3 . 3 . The method for forming a fin bipolar junction transistor according to claim 1 , wherein when the number of the base fins is plural, the plurality of base fins are parallel to each other; When the number of collector fins is multiple, the multiple collector fins are parallel to each other; when the number of the emitter fins is multiple, the multiple emitter fins are parallel to each other. 4 . The method for forming a fin bipolar junction transistor according to claim 1 , wherein the fin bipolar junction transistor is a PNP type fin bipolar junction transistor. 5 . 5 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the concentration of the second emitter ions is 1E15 atoms/cm ² to 3E15 atoms/cm ² ; the first emitter The concentration of ions is 3E14 atom/cm ² to 1E15 atom/cm ² . 6 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the first emitter ions and the second emitter ions are P-type ions. 7 . 7 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the process of doping the first emitter ions to the emitter fin is a first emitter ion implantation process; The process of doping the second emitter ions in the emitter fin is the second emitter ion implantation process. 8 . The method for forming a fin bipolar junction transistor according to claim 7 , wherein the ions used in the first emitter ion implantation process are B ions, the implantation energy is 3KeV˜5KeV, and the implantation dose is 3E14atom/cm ² to 1E15atom/cm ² , and the injection angle is 0 to 7 degrees. 9 . The method for forming a fin bipolar junction transistor according to claim 7 , wherein the ions used in the first emitter ion implantation process are BF ₂ ions, the implantation energy is 8KeV˜15KeV, and the implantation dose It is 3E14 atom/cm ² to 1E15 atom/cm ² , and the injection angle is 0 to 7 degrees. 10 . The method for forming a fin bipolar junction transistor according to claim 7 , wherein the ions used in the second emitter ion implantation process are B ions, the implantation energy is 1KeV～3KeV, and the implantation dose is 10 . 1E15atom/cm ² to 3E15atom/cm ² , and the injection angle is 0 to 7 degrees. 11 . The method for forming a fin bipolar junction transistor according to claim 7 , wherein the ions used in the second emitter ion implantation process are BF ₂ ions, the implantation energy is 4KeV˜7KeV, and the implantation dose It is 1E15atom/cm ² to 3E15atom/cm ² , and the injection angle is 0 to 7 degrees. 12 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the material of the collector epitaxial layer is silicon germanium; the material of the base epitaxial layer is silicon carbide. 13 . 13 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the base fin ions are N-type ions; the collector fin ions are P-type ions. 14 . 14 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the base fin ions have a concentration of 5E14 atoms/cm ² to 1E15 atoms/cm ² ; The concentration is 3E14atom/cm ² to 1E15atom/cm ² . 15 . The method for forming a fin bipolar junction transistor according to claim 4 , wherein the process of doping the base fin and the base epitaxial layer with base fin ions is a base fin ion implantation process. 16 . ; The process of doping collector fin ions to the collector fin and the collector epitaxial layer is a collector fin ion implantation process. 16 . The method for forming a fin bipolar junction transistor according to claim 15 , wherein the ions used in the base fin ion implantation process are P ions, the implantation energy is 6KeV˜10KeV, and the implantation dose is 5E14atom. 17 . /cm ² to 1E15atom/cm ² , and the injection angle is 0 to 7 degrees. 17 . The method for forming a fin bipolar junction transistor according to claim 15 , wherein the ions used in the collector fin ion implantation process are B ions, the implantation energy is 3KeV˜5KeV, and the implantation dose is 3E14atom. 18 . /cm ² to 1E15atom/cm ² , and the injection angle is 0 to 7 degrees. 18 . The method for forming a fin bipolar junction transistor according to claim 1 , wherein the semiconductor substrate comprises a first well region and a second well region connected to the first well region in a horizontal direction. 19 . , the types of ions doped in the second well region and the first well region are opposite, the collector fins are located on the surface of the first well region, and the ions of the collector fins are of the same type as the ions doped in the first well region, The base fin and the emitter fin are located on the surface of the second well region.