CN106409755B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN106409755B CN106409755B CN201510465541.6A CN201510465541A CN106409755B CN 106409755 B CN106409755 B CN 106409755B CN 201510465541 A CN201510465541 A CN 201510465541A CN 106409755 B CN106409755 B CN 106409755B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal layer
- metal
- top surface
- graphene
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Manufacturing & Machinery (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein the forming method of semiconductor structure includes: to provide substrate and the first medium layer positioned at substrate surface；Form the opening for running through first medium layer；Form the first metal layer of filling full gate mouth and the second metal layer positioned at the first metal layer top surface；The first graphene layer is formed in second metal layer top surface and sidewall surfaces；Second dielectric layer is formed in first medium layer top surface and the first graphene layer top surface and sidewall surfaces；Grinding removal is higher than the first graphene layer and second dielectric layer of second metal layer top surface, until exposing second metal layer top surface；The second graphene layer is formed in the second metal layer top surface exposed.Present invention reduces the resistance of semiconductor structure, improve the electric property of semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of semiconductor structure and forming method thereof.
Background technique
With being constantly progressive for super large-scale integration technology, the characteristic size of semiconductor devices constantly reduces,
The performance of semiconductor devices is more and more stronger, and the integrated level of IC chip has been up to the rule of several hundred million or even tens devices
Mould, two layers or more of multilayer interconnection technology are widely used.
Traditional interconnection structure be as aluminium it is standby made of, it is more next but with the continuous diminution of semiconductor dimensions
Higher and higher electric current is carried in smaller interconnection structure, and the response time requirement of interconnection structure is shorter and shorter, conventional aluminum is mutual
Connection structure is no longer satisfied requirement；Therefore, copper metal has been substituted material of the aluminum metal as interconnection structure.Compared with aluminium,
The resistivity of metallic copper is lower and electromigration resisting property is more preferable, and the resistance capacitance (RC) that copper interconnection structure can reduce interconnection structure prolongs
Late, improve electromigration, improve the reliability of device.Therefore, copper interconnection technology replaces aluminium interconnection technique to become development trend.
Material although with copper metal as interconnection structure in semiconductor structure can improve semiconductor to a certain extent
The performance of structure, however the performance of semiconductor structure is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, optimizes the property of semiconductor structure
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: provide substrate and position
In the first medium layer of substrate surface；The graphical first medium layer, forms the opening for running through the first medium layer；It is formed
Fill the first metal layer of the full opening and the second metal layer positioned at the first metal layer top surface, and described second
Metal layer covers first medium layer atop part surface；The first stone is formed in the second metal layer top surface and sidewall surfaces
Black alkene layer；Second is formed in the first medium layer top surface and the first graphene layer top surface and sidewall surfaces to be situated between
Matter layer；Grinding removal is higher than the first graphene layer and second dielectric layer of second metal layer top surface, until exposing the
Two metal layer top surfaces；The second graphene layer is formed in the second metal layer top surface exposed.
Optionally, first graphene layer is formed using laser writing technology；It is formed using laser writing technology described
Second graphene layer.Optionally, it is 5 milliwatts to 500 millis that the technological parameter for forming first graphene layer, which includes: laser power,
Watt, direct write rate is 100 micron per minutes to 1000 micron per minutes.
Optionally, it further comprises the steps of: using AuCl3Processing is doped to first graphene layer.
Optionally, first graphene layer with a thickness of 1 angstrom to 100 angstroms；Second graphene layer with a thickness of 1 angstrom
To 100 angstroms.
Optionally, the material of the first metal layer is copper；The material of the second metal layer is copper.Optionally, it is formed
The processing step of the first metal layer and second metal layer includes: to form filling to expire the metal film of the opening, and the gold
Belong to film and is also covered in first medium layer top surface；Planarization process is carried out to the metal film；At the graphical planarization
Metal film after reason forms the first metal layer being located in opening and positioned at described the second of the first metal layer top surface
Metal layer.
Optionally, the processing step for forming the first metal layer and second metal layer includes: to be formed to open described in filling completely
First metal film of mouth；Grinding removal is higher than the first metal film of first medium layer top surface, forms the of filling full gate mouth
One metal layer；The second metal film is formed in the first metal layer top surface and first medium layer top surface；Graphically
Second metal film forms the second metal for being located at the first metal layer top surface and part first medium layer top surface
Layer.
Optionally, using chemical mechanical milling tech, grinding removal is described to be higher than the first of second metal layer top surface
Graphene layer and second dielectric layer.
Optionally, the material of the first medium layer is silica, low k dielectric materials or ultra-low k dielectric material；Described
The material of second medium layer is silica, low k dielectric materials or ultra-low k dielectric material.
The present invention also provides a kind of semiconductor structures, comprising: substrate and the first medium layer positioned at the substrate surface；
Opening in the first medium layer and through the first medium layer；Fill the full opening the first metal layer, with
And the second metal layer positioned at the first metal layer top surface, and the second metal layer covers first medium layer atop part table
Face；Positioned at the first graphene layer of the second metal layer sidewall surfaces；Positioned at the second of the second metal layer top surface
Graphene layer；Positioned at the first graphene layer sidewall surfaces and the second dielectric layer of first medium layer top surface.
Optionally, the material of the first metal layer is copper；The material of the second metal layer is copper.Optionally, described
First graphene layer with a thickness of 1 angstrom to 100 angstroms；Second graphene layer with a thickness of 1 angstrom to 100 angstroms.
The present invention also provides a kind of forming methods of semiconductor structure, comprising: provides substrate and positioned at substrate surface
First medium layer；The graphical first medium layer, forms the opening for running through the first medium layer；It is formed and is opened described in filling completely
Mouthful the first metal layer and second metal layer positioned at the first metal layer top surface, and second metal layer covering the
One dielectric layer segments top surface；Graphene layer is formed in the second metal layer top surface and sidewall surfaces；In the stone
Black alkene layer top surface and sidewall surfaces, the first medium layer top surface form second dielectric layer；Described second is etched to be situated between
Matter layer forms the groove for running through the second dielectric layer, and the channel bottom exposes graphene layer top surface.
Optionally, the graphene layer is formed using laser writing technology.Optionally, the technique of the graphene layer is formed
Parameter includes: that laser power is 5 milliwatts to 500 milliwatts, and direct write rate is 100 micron per minutes to 1000 micron per minutes.
Optionally, it further comprises the steps of: and processing is doped to the graphene layer using AuCl3.Optionally, the graphite
Alkene layer with a thickness of 1 angstrom to 100 angstroms.
Optionally, the processing step for forming the first metal layer and second metal layer includes: to be formed to open described in filling completely
The metal film of mouth, and the metal film is also covered in first medium layer top surface；Planarization process is carried out to the metal film；
Metal film after the graphical planarization process forms the first metal layer being located in opening and is located at the first metal layer
The second metal layer of top surface.
The present invention also provides a kind of semiconductor structures, comprising: substrate and the first medium layer positioned at the substrate surface；
Opening in the first medium layer and through the first medium layer；Fill the full opening the first metal layer, with
And the second metal layer positioned at the first metal layer top surface, and the second metal layer covers first medium layer atop part table
Face；Positioned at the graphene layer of the second metal layer top surface and sidewall surfaces；Positioned at the graphene layer top surface and
The second dielectric layer of sidewall surfaces and the first medium layer top surface；In the second dielectric layer and run through institute
The groove of second dielectric layer is stated, and the channel bottom exposes graphene layer top surface.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of semiconductor structure provided by the invention, the first metal of filling full gate mouth is formed
Layer and positioned at the first metal layer top surface second metal layer, and second metal layer cover first medium layer atop part
Surface；The first graphene layer is formed in second metal layer top surface and sidewall surfaces；In first medium layer top surface and
First graphene layer top surface and sidewall surfaces form second dielectric layer；Grinding removal is higher than second metal layer top surface
First graphene layer and second dielectric layer, until exposing second metal layer top surface；In second gold medal exposed
Belong to layer top surface and forms the second graphene layer, it can be by second metal layer and external structure electricity by second graphene layer
Connection.Since second metal layer sidewall surfaces are formed with the first graphene layer, second metal layer top surface is formed with the second stone
The integrally-built resistance of black alkene layer, second metal layer, the first graphene layer and the second graphene layer is less than second metal layer
Resistance, the integrally-built thermal conductivity of second metal layer, the first graphene layer and the second graphene layer is better than the second metal
The thermal conductivity of layer, therefore the resistance of semiconductor structure that is formed of the present invention reduces and thermal conductivity is improved.
Further, first graphene layer is formed using laser direct-writing technique in the present invention, using laser direct-writing technique
Second graphene layer is formed, so that forming the simple process of the first graphene layer and the second graphene layer.
Further, the processing step for forming the first metal layer and second metal layer includes: the metal to form filling full gate mouth
Film, and the metal film is also covered in first medium layer top surface；Planarization process is carried out to the metal film top surface；
Metal film after the graphical planarization process forms the first metal layer being located in opening and is located at the first metal layer top
The second metal layer on portion surface.In the present invention, grown due to being higher than the crystal grain of metal film of first medium layer top surface
Limitation is not affected by journey, therefore the metal film for being higher than first medium layer top surface has biggish crystallite dimension and crystal grain boundary
Few, so that the crystallite dimension of the second metal layer formed is big and crystal grain boundary is few, the crystal grain boundary scattering in second metal layer is weak,
So that second metal layer has lower resistivity, the resistance of semiconductor structure is further decreased.
Correspondingly, the present invention provides a kind of superior semiconductor structure of structural behaviour, wherein second metal layer top surface
It is formed with the second graphene layer, second metal layer sidewall surfaces are formed with the first graphene layer, and pass through the second graphene layer energy
Enough it is electrically connected second metal layer with external circuit.Due to second metal layer, the first graphene layer and the second graphene layer
Integrally-built resistance is less than the resistance of second metal layer, and second metal layer, the first graphene layer and the second graphene layer
Thermal conductivity it is better than the thermal conductivity of second metal layer so that the resistance of semiconductor structure is low and thermal conductivity is good.
The present invention also provides a kind of forming method of semiconductor structure, formed filling full gate mouth the first metal layer and
Positioned at the second metal layer of the first metal layer top surface, and second metal layer covers first medium layer atop part surface；?
Second metal layer top surface and sidewall surfaces form graphene layer；In graphene layer top surface and sidewall surfaces, Yi Ji
One dielectric layer top surface forms second dielectric layer；The second dielectric layer is etched, the ditch for running through the second dielectric layer is formed
Slot, and the channel bottom exposes graphene layer top surface, therefore second metal layer and outer can be made by graphene layer
The electrical connection of portion's circuit.The integrally-built resistance of second metal layer and the graphene layer is less than the resistance of second metal layer,
Second metal layer and the integrally-built thermal conductivity of the graphene layer are better than the thermal conductivity of second metal layer, therefore the present invention
The resistance of the semiconductor structure of formation is small and thermal conductivity is good.
Correspondingly, the present invention also provides a kind of superior semiconductor structures of structural behaviour, wherein table at the top of second metal layer
Face and sidewall surfaces are formed with graphene layer, and can make second metal layer by the graphene layer of second metal layer top surface
It is electrically connected with external circuit.Since the integrally-built resistance of second metal layer and graphene layer is less than the electricity of second metal layer
The integrally-built thermal conductivity of resistance, second metal layer and graphene layer is better than the thermal conductivity of second metal layer, therefore the present invention
The resistance of the semiconductor structure of offer is low and thermal conductivity is good.
Detailed description of the invention
Fig. 1 to Figure 10 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process；
Figure 11 to Figure 15 be another embodiment of the present invention provides semiconductor structure formed process the schematic diagram of the section structure.
Specific embodiment
It can be seen from background technology that the performance for the semiconductor structure that the prior art is formed needs to be further increased.
It has been investigated that although copper metal is more suitable for the material of interconnection structure in conductor structure than aluminum metal,
Since the resistivity of copper metal is still larger, the resistance of semiconductor structure is still larger.
Further study show that graphene (Graphene) is that a kind of carbon atom in monolayer honeycomb crystal lattice forms
Two crystal, graphene not only have very outstanding mechanical property and thermal stability, also have outstanding electric property, such as
The ballistic transport characteristic of submicron order, high carrier mobility, tunable band gap, quantum hall effect at room temperature etc., and
And graphene also has the advantages that low-resistivity.
If can be beneficial to reduce by half using graphene and copper connected applications as the material of interconnection structure in semiconductor structure
The resistance of conductor structure.
For this purpose, the present invention provides a kind of forming method of semiconductor structure, substrate is provided and positioned at the of substrate surface
One dielectric layer；Form the opening for running through first medium layer；It forms the first metal layer of filling full gate mouth and is located at the first metal
The second metal layer of layer top surface；The first graphene layer is formed in second metal layer top surface and sidewall surfaces；First
Dielectric layer top surface and the first graphene layer top surface and sidewall surfaces form second dielectric layer；Grinding removal is higher than
The first graphene layer and second dielectric layer of second metal layer top surface, until exposing second metal layer top surface；
The second graphene layer is formed in the second metal layer top surface exposed.Since second metal layer top surface is formed with
Second graphene layer, second metal layer sidewall surfaces are formed with the first graphene layer, the first graphene layer and the second graphene layer
Has the advantages that low-resistivity, therefore the resistance of semiconductor structure reduces, to optimize the electric property of semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
With reference to Fig. 1, substrate 100 and the first medium layer 102 positioned at 100 surface of substrate are provided.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide or GaAs；The material of the substrate 100 may be used also
Think the silicon on monocrystalline silicon, polysilicon, amorphous silicon or insulator.
100 surface of substrate can also be formed with several boundary layers or epitaxial layer to improve the electrical property of semiconductor structure
Energy.Can also be formed with semiconductor devices in the substrate 100, the semiconductor devices be PMOS transistor, NMOS transistor,
CMOS transistor, capacitor, resistor or inductor.
In the present embodiment, the substrate 100 is silicon base.
Bottom metal layer 101 can also be formed in the substrate 100, and the substrate 100 exposes the bottom gold
Belong to 101 top surface of layer.The bottom metal layer 101 with the first metal layer to be formed for being connected, it can also be used to subsequent
The first metal layer of formation is electrically connected with external or other metal layers.The material of the bottom metal layer 101 is Cu, Al or W
Equal conductive materials.In the present embodiment, 101 top surface of bottom metal layer is flushed with 100 top surface of substrate.In other realities
It applies in example, the bottom metal layer top surface can also be higher than base top surface.
In one embodiment, a bottom metal layer 101 is formed in the substrate 100.In another embodiment, institute
It states and is formed with several bottom metal layers 101 in substrate 100.In the present embodiment, to be formed with 3 bottoms in the substrate 100
Metal layer 101 is as an example, correspondingly, the subsequent opening formed in first medium layer 102 is also 3.
The material of the first medium layer 102 is silica, (low k dielectric materials refer to relative dielectric constant to low k dielectric materials
More than or equal to the 2.6, dielectric material less than or equal to 3.9) or ultra-low k dielectric material (ultra-low k dielectric material refers to relative dielectric constant
Dielectric material less than 2.6).
The material of the first medium layer 102 is SiOH, SiCOH, FSG (silica of fluorine doped), BSG (the two of boron-doping
Silica), PSG (silica of p-doped), BPSG (silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ,
(HSiO1.5)n) or methyl silsesquioxane (MSQ, (CH3SiO1.5)n)。
In the present embodiment, the material of the first medium layer 102 is ultra-low k dielectric material, and the ultra-low k dielectric material is
SiCOH。
In the present embodiment, further comprises the steps of: and form passivation layer (not shown) on 102 surface of first medium layer, the passivation
Layer plays the role of protecting first medium layer 102, the lattice constant of first medium layer 102 and the patterned exposure mask being subsequently formed
The lattice constant difference of layer is larger, and the lattice constant of passivation layer is positioned there between, therefore passivation layer also functions to transitional function,
It avoids applying stress since lattice constant is mutated to first medium layer 102 and first medium layer 102 being caused to deform.The material of passivation layer
Material is silica or contains silicon oxide carbide.
Etching barrier layer can also be formed between the substrate 100 and first medium layer 102, the opening being subsequently formed is also
Through the etching barrier layer.The etching barrier layer plays the role of etch stopper, subsequent etching first medium layer 102 subsequent
Etching technics it is smaller to the etch rate of etching barrier layer, to play the role of etching stopping, prevent to substrate 100 or bottom
Metal layer 101 causes over etching.Also, the etching technics of etching barrier layer described in subsequent etching is to the quarter of bottom metal layer 101
It is small to lose rate, to further avoid causing etching injury to bottom metal layer 101.The material of the etching barrier layer and first
The material of dielectric layer 102 is different.The material of the etching barrier layer is silicon nitride, silicon oxynitride or carbonitride of silicium.
With reference to Fig. 2, patterned mask layer 103 is formed on 102 surface of first medium layer.
The groove 104 for exposing 102 top surface of first medium layer is formed in the patterned mask layer 103, and
The figure that the figure that the groove 104 is projected on 100 surface of substrate is projected on 100 surface of substrate with bottom metal layer 101 has
Intersection.
The groove 104 defines the positions and dimensions for the opening being subsequently formed.In the present embodiment, formed in substrate 100
There are 3 bottom metal layers, correspondingly, the quantity of the groove 104 in the patterned mask layer 103 is 3.
The patterned mask layer 103 is single layer structure or laminated construction.The material of the patterned mask layer 103
For medium mask material or metal mask material, wherein medium mask material is SiN, SiC or SiCN, and metal mask material is
Ta, Ti, Tu, TaN, TiN, TuN or WN.
In one embodiment, the patterned mask layer 103 is the single layer structure of medium mask layer.In another embodiment
In, the patterned mask layer 103 is the single layer structure of metal mask layer.In other embodiments, described patterned to cover
Film layer is the laminated construction of medium mask layer and the metal mask layer positioned at medium exposure mask layer surface.
In the present embodiment, the material of the patterned mask layer 103 is TiN.
In other embodiments, the material of patterned mask layer can also be organic material.For example, patterned exposure mask
Layer is the single layer structure of photoresist layer, alternatively, patterned mask layer includes organic distribution layer, positioned at organic distribution layer surface
Bottom antireflective coating and photoresist layer positioned at bottom antireflective coating surface.
With reference to Fig. 3, with the patterned mask layer 103 (referring to Fig. 2) for exposure mask, the graphical first medium layer
102, form the opening 105 for running through the first medium layer 102.
In the present embodiment, 105 bottom-exposeds of the opening go out the bottom metal layer 101.
The first medium layer 102 is etched using dry etch process.In a specific embodiment, the dry etching
The etching gas of technique includes CH2F2、C4F6、CF4Or CHF3, in order to reduce dry etch process to the quarter of first medium layer 102
Deteriorate wound, the etching gas of the dry etch process can also include O2。
In the present embodiment, it is described opening 105 sidewall surfaces be mutually perpendicular to 100 top surface of substrate, be open 105 top
Portion's size is identical as bottom size.In other embodiments, the top dimension of opening can also be greater than bottom size.
Subsequent to fill the first metal layer in opening 105, the first metal layer is convex as the metal in semiconductor structure
Column (Pillar)；Subsequent to form second metal layer in the first metal layer top surface, the second metal layer is as semiconductor junction
Metal connecting line (Line) in structure.
In the present embodiment, after forming the opening 105, the patterned mask layer 103 (referring to Fig. 2) is removed.
With reference to Fig. 4, the metal film 106 of the full opening 105 (referring to Fig. 3) of filling is formed, and the metal film 106 also covers
It is placed on 102 top surface of first medium layer；Planarization process, and the metal after planarization process are carried out to the metal film 106
It is higher than 102 top of first medium layer at the top of film 106.
The metal film 106 provides Process ba- sis to be subsequently formed the first metal layer and second metal layer.
In the present embodiment, the material of the metal film 106 is copper.Using metal organic chemical deposition technique, physical vapor
Deposition or atom layer deposition process form the metal film 106.In other embodiments, additionally it is possible to use electrochemical plating membrane process
Form the metal film.
In the present embodiment, the metal film 106 is formed using physical gas-phase deposition.
It is relatively large sized due to 102 top surface of first medium layer, in 102 top surface shape of first medium layer
At the size of metal film 106 also will be bigger so that the crystal grain being higher than in the metal film 106 at 102 top of first medium layer is raw
It is long to be not affected by limitation, therefore the metal film 106 for being higher than 102 top of first medium layer has biggish crystallite dimension (Grain
Size) and crystal grain boundary (Grain Boundary) is few, so that being higher than crystal grain in the metal film 106 at 102 top of first medium layer
Interface scattering (Grain Boundary Scattering) is weak, therefore be higher than the metal film 106 at 102 top of first medium layer
Resistivity is relatively low.
Using chemical mechanical milling tech, planarization process is carried out to the metal film 106.
With reference to Fig. 5,106 surface of metal film after the planarization process forms graph layer 107.
The graph layer 107 defines the positions and dimensions for the second metal layer being subsequently formed.Subsequent etching is not by figure
The metal film 106 of 107 covering of layer, until exposing 102 top surface of first medium layer.
The graph layer 107 is projected on the figure on 100 surface of substrate and opening 105 (with reference to Fig. 3) is projected on 100 table of substrate
The figure in face has intersection, and the figure that 105 are projected on 100 surface of substrate that is open is located at graph layer 107 and is projected on
In the figure on 100 surface of substrate.
In the present embodiment, the material of the graph layer 107 is photoresist, and the processing step for forming institute's graph layer 107 includes:
106 surface of metal film after the planarization process coats photoresist film；To the photoresist film be exposed processing and
Development treatment forms the graph layer 107.
In other embodiments, the material of the graph layer may be hard mask material, such as metal mask material or Jie
Matter mask material.
Metal film with reference to Fig. 6, with the graph layer 107 (referring to Fig. 5) for exposure mask, after the graphical planarization process
106 (referring to Fig. 5) form the first metal layer 108 of the full opening 105 (referring to Fig. 3) of filling and are located at the first metal layer
The second metal layer 109 of 108 top surfaces, and the second metal layer 109 covers 102 atop part surface of first medium layer.
Metal film 106 in the present embodiment, after the planarization process is etched using dry etch process.
The first metal layer 107 is used as and partly leads as the metal pillar in semiconductor structure, the second metal layer 108
Metal connecting line in body structure.
In the present embodiment, the second metal layer 109 is the graphical metal film for being located at 102 top surface of first medium layer
106 acquisitions, the metal film 106 due to being higher than 102 top of first medium layer has biggish crystallite dimension and crystal grain boundary is few,
So that it is weak to be higher than crystal grain boundary scattering in the metal film 106 at 102 top of first medium layer, therefore it is higher than first medium layer 102 and pushes up
The resistivity of the metal film 106 in portion is relatively low.That is, the material of second metal layer 109 have compared with big crystal grain size and
Crystal grain boundary is few, therefore crystal grain boundary scattering is weak in second metal layer 109, so that second metal layer 109 is with lower
Resistivity, so that semiconductor structure has lower resistance.
After forming the first metal layer 108 and second metal layer 109, the graph layer 107 is removed (with reference to figure
5)。
In the present embodiment, removed photoresist using wet process or cineration technics removes the graph layer 107 (with reference to Fig. 5).
In the present embodiment, the first metal layer 108 and second metal layer 109 are to be formed on the basis of metal film 106
, and patterned mask layer 103 is removed before forming metal film 106 (with reference to Fig. 2).In other embodiments, it is being formed
After opening, additionally it is possible to first retain patterned mask layer, form the first metal layer, the processing step of second metal layer includes:
The first metal film of filling full gate mouth is formed, and first metal film is also located at patterned exposure mask layer surface；Grinding removal
Higher than the first metal film and patterned mask layer of first medium layer top surface, the gold medal for filling the full opening is formed
Belong to layer；The second metal film is formed in the first metal layer top surface and first medium layer top surface；It is graphical described
Second metal film forms the second metal layer for being located at the first metal layer top surface and part first medium layer top surface.
With reference to Fig. 7, the first graphene layer 110 is formed in 109 top surface of second metal layer and sidewall surfaces.
In the present embodiment, first graphene layer is formed using laser writing technology (Laser Direct Writing)
110。
In a specific embodiment, the technological parameter of first graphene layer 110 is formed using laser writing technology
It include: laser power for 5 milliwatts to 500 milliwatts, direct write rate is 100 micron per minutes to 1000 micron per minutes.
First graphene layer 110 with a thickness of 1 angstrom to 100 angstroms.
In the present embodiment, further comprise the steps of: using AuCl3Processing is doped to first graphene layer 110.It is good
Be in: using AuCl3Processing is doped to the first graphene layer 110, the lattice in the first graphene layer 110 can be repaired
Defect further decreases the resistance of semiconductor structure to further decrease the resistivity of 110 material of the first graphene layer.
With reference to Fig. 8, in 102 top surface of first medium layer and 110 top surface of the first graphene layer and side wall
Surface forms second dielectric layer 111.
The material of the second dielectric layer 111 is silica, (low k dielectric materials refer to relative dielectric constant to low k dielectric materials
More than or equal to the 2.6, dielectric material less than or equal to 3.9) or ultra-low k dielectric material (ultra-low k dielectric material refers to relative dielectric constant
Dielectric material less than 2.6).
When the material of the second dielectric layer 111 is low k dielectric materials or ultra-low k dielectric material, second dielectric layer 111
Material be SiOH, SiCOH, FSG (silica of fluorine doped), BSG (silica of boron-doping), PSG (silica of p-doped),
BPSG (silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ,
(CH3SiO1.5)n)。
In the present embodiment, the material of the second dielectric layer 111 is SiOH, forms described second using spin coating process
Dielectric layer 111.
With reference to Fig. 9, the first graphene layer 110 and second that grinding removal is higher than 109 top surface of second metal layer is situated between
Matter layer 111, until exposing 109 top surface of second metal layer.
In the present embodiment, 109 top surface of second metal layer is exposed, and is pushed up so as to subsequent in second metal layer 109
Portion surface forms the second graphene layer, and is electrically connected semiconductor structure with other external structures by the second graphene layer.
In the present embodiment, using chemical mechanical milling tech, grinding removal is higher than the of 109 top surface of second metal layer
One graphene layer 110 and second dielectric layer 111.
With reference to Figure 10, the second graphene layer 112 is formed in 109 top surface of second metal layer exposed.
In the present embodiment, second graphene layer 112 is also located at the in addition to being located at 109 top surface of second metal layer
One graphene layer, 110 top surface.It is electrically connected between second metal layer 109 and external circuit by the realization of the second graphene layer 112
It connects.
In the present embodiment, second graphene layer 112 is formed using laser direct-writing technique.In a specific embodiment
In, using laser direct-writing technique to form the technological parameter of the second graphene layer 112 includes: laser power for 5 milliwatts to 500 millis
Watt, direct write rate is 100 micron per minutes to 1000 micron per minutes.
Second graphene layer 112 with a thickness of 1 angstrom to 100 angstroms.
In the present embodiment, since 109 top surface of second metal layer is formed with the second graphene layer 112, second metal layer
109 sidewall surfaces are formed with the first graphite linings 110, so that the resistance of semiconductor structure reduces, and the thermal conductivity of semiconductor structure
Improved, to optimize the electric property of semiconductor structure.
Meanwhile in the present embodiment second metal layer 109 material grains size it is larger and crystal grain boundary is few so that the second gold medal
It is weak to belong to crystal grain boundary scattering in layer 109, therefore second metal layer 109 has lower resistivity, partly leads to further decrease
The resistance of body structure advanced optimizes the electric property of semiconductor structure.
Correspondingly, the present embodiment also provides a kind of semiconductor structure, with reference to Figure 10, the semiconductor structure includes:
Substrate 100 and first medium layer 102 positioned at 100 surface of substrate；
Opening in the first medium layer 102 and through the first medium layer 102；
Fill the first metal layer 108 of the full opening and the second metal positioned at 108 top surface of the first metal layer
Layer 109, and the second metal layer 109 covers 102 atop part surface of first medium layer；
Positioned at the first graphene layer 110 of 109 sidewall surfaces of second metal layer；
Positioned at the second graphene layer 112 of 109 top surface of second metal layer；
Positioned at 110 sidewall surfaces of the first graphene layer and the second dielectric layer of 102 top surface of first medium layer
111。
It will elaborate below to semiconductor structure provided in this embodiment.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide or GaAs.In the present embodiment, the substrate 100
For silicon base.
Several bottom metal layers 101 are also formed in the substrate 100, and the substrate 100 exposes bottom metal layer
101 top surfaces.In the present embodiment, 101 top of the bottom metal layer with flushed at the top of substrate 100.In other embodiments,
Base top can also be higher than at the top of the bottom metal layer.
The material of the first medium layer 102 is silica, low k dielectric materials or ultra-low k dielectric material；Through described
The opening of one dielectric layer 102 exposes 101 top surface of bottom metal layer, thus the first metal layer 108 being located in opening with
Bottom metal layer 101 is electrically connected.
The material of the second dielectric layer 111 is silica, low k dielectric materials or ultra-low k dielectric material.
In the present embodiment, the material of the first metal layer 108 is copper, and the material of the second metal layer 109 is copper.Institute
State the first graphene layer 110 with a thickness of 1 angstrom to 100 angstroms；Second graphene layer 112 with a thickness of 1 angstrom to 100 angstroms.
In the present embodiment, second graphene layer 112 is also located at the in addition to being located at 109 top surface of second metal layer
One graphene layer, 110 top surface.
The material of first graphene layer 110 is graphene, and the material of the second graphene layer 112 is graphene, graphite
Alkene has the advantages that resistivity is low, the second graphene layer 112 is formed in 109 top surface of second metal layer, in the second metal
109 sidewall surfaces of layer are formed with the first graphene layer 110, can reduce the resistance of semiconductor structure, and second metal layer 109
Thermal conductivity enhancing, therefore the thermal conductivity of semiconductor structure provided in this embodiment can also access improvement.
Another embodiment of the present invention also provides a kind of forming method of semiconductor structure, and Figure 11 to Figure 15 is that the present invention is another
The semiconductor structure that embodiment provides forms the schematic diagram of the section structure of process.
With reference to Figure 11, substrate 200 and the second dielectric layer 202 positioned at 200 surface of substrate are provided；Graphical described first
Dielectric layer 202 forms the opening for running through the first medium layer 202；The first metal layer 208 of the full opening of formation filling,
And the second metal layer 209 positioned at 208 top surface of the first metal layer, and the second metal layer 209 covers first medium
202 atop part surface of layer.
In the present embodiment, bottom metal layer 201 is also formed in the substrate 200.
In one embodiment, the processing step for forming the first metal layer 208 and second metal layer 209 includes: shape
At the metal film of filling full gate mouth, and the metal film is also covered in 202 top surface of first medium layer；To the metal film top
Portion surface carries out planarization process；Metal film after the graphical planarization process, forms the first metal being located in opening
Layer 208 and positioned at 208 top surface of the first metal layer the second metal layer 209.
Related substrate 200, bottom metal layer 201, first medium layer 202, the first metal layer 208 and second metal layer
209 description can refer to the explanation of previous embodiment, and details are not described herein.
With reference to Figure 12, graphene layer 210 is formed in 209 top surface of second metal layer and sidewall surfaces.
In the present embodiment, the graphene layer 210 is formed using laser writing technology, technological parameter includes: laser power
For 5 milliwatts to 500 milliwatts, direct write rate is 100 micron per minutes to 1000 micron per minutes.
In the present embodiment, the graphene layer 210 with a thickness of 1 angstrom to 100 angstroms.
In the present embodiment, further comprise the steps of: using AuCl3Processing is doped to the graphene layer 210, to reduce stone
Lattice defect in black alkene layer 210, further decreases the resistivity of 210 material of graphene layer, to further decrease semiconductor
The resistance of structure.
With reference to Figure 13, pushed up in 210 top surface of graphene layer and sidewall surfaces and the first medium layer 202
Portion surface forms second dielectric layer 211.
The material of the second dielectric layer 211 is silica, low k dielectric materials or ultra-low k dielectric material.The present embodiment
In, the material of the second dielectric layer 211 is silica, forms the second dielectric layer 211 using spin coating process.
With reference to Figure 14, graph layer 212 is formed on 211 surface of second dielectric layer, is formed in the graph layer 212 recessed
Slot 213.
The groove 213 defines the positions and dimensions for the groove being subsequently formed.The groove 213 is located at second metal layer
209 top, so that the groove being subsequently formed can will be located at the exposure of graphene layer 210 at 209 top of second metal layer
Out.In the present embodiment, the material of the graph layer 212 is photoresist.In other embodiments, the material of the graph layer is also
It can be metal mask material or medium mask material.
With reference to 15, with the graph layer 212 (referring to Figure 14) for exposure mask, the second dielectric layer 211 is etched, formation runs through
The groove 214 of the second dielectric layer 211, and 214 bottom-exposed of the groove goes out 210 top surface of graphene layer.
It is exposure mask with the graph layer 212 in the present embodiment, second that the groove 213 (referring to Figure 14) is exposed
Dielectric layer 211 performs etching, and forms the groove 214 for running through the second dielectric layer 211.The groove 214 exposes graphene
210 top surface of layer, so that second metal layer 209 be made to be electrically connected with external circuit or other metal layers.
In the present embodiment, since 209 top surface of second metal layer and sidewall surfaces are formed with graphene layer 210, so that
The resistance of semiconductor structure reduces, and the thermal conductivity of semiconductor structure is improved, to optimize the electrical property of semiconductor structure
Energy.
Meanwhile the material grains size of the second metal layer 209 formed in the present embodiment is larger and crystal grain boundary is few, so that
Crystal grain boundary scattering is weak in second metal layer 209, therefore second metal layer 209 has lower resistivity, to further drop
The resistance of low semiconductor structure advanced optimizes the electric property of semiconductor structure.
Correspondingly, the present embodiment also provides a kind of semiconductor structure, Figure 15 is semiconductor structure provided in this embodiment
The schematic diagram of the section structure, comprising:
Substrate 200 and first medium layer 202 positioned at 200 surface of substrate；
Opening in the first medium layer 202 and through the first medium layer 202；
Fill the first metal layer 208 of the full opening and the second metal positioned at 208 top surface of the first metal layer
Layer 209, and the second metal layer 209 covers 202 atop part surface of first medium layer；
Positioned at the graphene layer 210 of 209 top surface of second metal layer and sidewall surfaces；
Positioned at 210 top surface of graphene layer and sidewall surfaces and 202 top surface of first medium layer
Second dielectric layer 211；
Groove 214 in the second dielectric layer 211 and through the second dielectric layer 211, and the groove 214
Bottom-exposed goes out 210 top surface of graphene layer.
It will elaborate below to semiconductor structure provided in this embodiment.
The material of the substrate 200 is silicon, germanium, SiGe, silicon carbide or GaAs.In the present embodiment, the substrate 200
For silicon base.
Several bottom metal layers 201 are also formed in the substrate 200, and the substrate 200 exposes bottom metal layer
201 top surfaces.In the present embodiment, 201 top of the bottom metal layer with flushed at the top of substrate 200.In other embodiments,
Base top can also be higher than at the top of the bottom metal layer.
The material of the first medium layer 202 is silica, low k dielectric materials or ultra-low k dielectric material；Through described
The opening of one dielectric layer 202 exposes 201 top surface of bottom metal layer, thus the first metal layer 208 being located in opening with
Bottom metal layer 201 is electrically connected.
The material of the graphene layer 210 is graphene, with a thickness of 1 angstrom to 100 angstroms.
The material of the second dielectric layer 211 is silica, low k dielectric materials or ultra-low k dielectric material.Through described
214 bottom-exposed of groove of second medium layer 211 goes out 210 top surface of graphene layer, by graphene layer 210 by second metal layer
209 are electrically connected with external structure.
In the present embodiment, since 209 top surface of second metal layer and sidewall surfaces are formed with graphene layer 210, so that
The resistance of semiconductor structure reduces, and the heating conduction of semiconductor structure is improved, to optimize the electricity of semiconductor structure
Performance.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate and the first medium layer positioned at substrate surface are provided；
The graphical first medium layer, forms the opening for running through the first medium layer；
The first metal layer for filling the full opening and the second metal layer positioned at the first metal layer top surface are formed, and
The second metal layer covers first medium layer atop part surface；
The first graphene layer is formed in the second metal layer top surface and sidewall surfaces；
Second medium is formed in the first medium layer top surface and the first graphene layer top surface and sidewall surfaces
Layer；
Grinding removal is higher than the first graphene layer and second dielectric layer of second metal layer top surface, until exposing second
Metal layer top surface；
The second graphene layer is formed in the second metal layer top surface exposed.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that form institute using laser writing technology
State the first graphene layer；Second graphene layer is formed using laser writing technology.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that form first graphene layer
Technological parameter includes: that laser power is 5 milliwatts to 500 milliwatts, and direct write rate is 100 micron per minutes to 1000 micron per minutes.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that further comprise the steps of: using AuCl3It is right
First graphene layer is doped processing.
5. the forming method of semiconductor structure as described in claim 1, first graphene layer with a thickness of 1 angstrom to 100
Angstrom；Second graphene layer with a thickness of 1 angstrom to 100 angstroms.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the first metal layer is
Copper；The material of the second metal layer is copper.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the first metal layer and
The processing step of two metal layers includes: to form the metal film for filling the full opening, and the metal film is also covered in first Jie
Matter layer top surface；Planarization process is carried out to the metal film；Metal film after the graphical planarization process, forms position
In the first metal layer in opening and positioned at the second metal layer of the first metal layer top surface.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the first metal layer and
The processing step of two metal layers includes: to form the first metal film for filling the full opening；Grinding removal is higher than first medium layer
First metal film of top surface forms the first metal layer of filling full gate mouth；In the first metal layer top surface and
First medium layer top surface forms the second metal film；Graphical second metal film, forms and is located at the top of the first metal layer
The second metal layer of surface and part first medium layer top surface.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that chemical mechanical milling tech is used,
Grinding removal first graphene layer and second dielectric layer for being higher than second metal layer top surface.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the first medium layer
For silica, low k dielectric materials or ultra-low k dielectric material；The material of the second dielectric layer is silica, low k dielectric materials
Or ultra-low k dielectric material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510465541.6A CN106409755B (en) | 2015-07-31 | 2015-07-31 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510465541.6A CN106409755B (en) | 2015-07-31 | 2015-07-31 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106409755A CN106409755A (en) | 2017-02-15 |
| CN106409755B true CN106409755B (en) | 2019-07-30 |
Family
ID=58007405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510465541.6A Active CN106409755B (en) | 2015-07-31 | 2015-07-31 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106409755B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151101A (en) * | 2013-04-02 | 2013-06-12 | 重庆绿色智能技术研究院 | Doped graphene flexible transparent electrode and preparation method thereof |
| CN103456677A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104428893A (en) * | 2012-05-10 | 2015-03-18 | 三星电子株式会社 | Graphene cap for copper interconnect structures |
| CN104517894A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5755618B2 (en) * | 2012-09-06 | 2015-07-29 | 株式会社東芝 | Semiconductor device |
-
2015
- 2015-07-31 CN CN201510465541.6A patent/CN106409755B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104428893A (en) * | 2012-05-10 | 2015-03-18 | 三星电子株式会社 | Graphene cap for copper interconnect structures |
| CN103456677A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103151101A (en) * | 2013-04-02 | 2013-06-12 | 重庆绿色智能技术研究院 | Doped graphene flexible transparent electrode and preparation method thereof |
| CN104517894A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106409755A (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11062901B2 (en) | Low-k dielectric and processes for forming same | |
| US9613880B2 (en) | Semiconductor structure and fabrication method thereof | |
| TWI703633B (en) | Electronic device and methods to manufacture electronic device, to provide maskless air gap flow, and to provide replacement interlayer dielectric flow | |
| TWI694622B (en) | Embedded mram in interconnects and method for producing the same | |
| US8384219B2 (en) | Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles | |
| TWI636576B (en) | Embedded Metal-Insulator-Metal (MIM) Capacitors | |
| TW201011861A (en) | Method for fabricating integrated circuit | |
| CN101477978A (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN106486418A (en) | Semiconductor device and method for manufacturing the same | |
| CN110556300A (en) | Method of forming semiconductor device | |
| US9997562B1 (en) | Mram memory device and manufacturing method thereof | |
| US8987859B2 (en) | Techniques for enhancing dielectric breakdown performance | |
| US20200098976A1 (en) | Integrated circuits with embedded memory structures and methods for fabricating the same | |
| CN110313065A (en) | Graphene heterosphere for electronic application | |
| US11101175B2 (en) | Tall trenches for via chamferless and self forming barrier | |
| US10157775B2 (en) | Method for manufacturing a semiconductor device | |
| CN107230679A (en) | High density memory cells structure | |
| CN110838464A (en) | Metal internal connection structure and its making method | |
| US20160204344A1 (en) | Structure and formation method of memory device | |
| CN106409755B (en) | Semiconductor structure and forming method thereof | |
| US12125790B2 (en) | Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via | |
| CN116344499A (en) | Staggered and vertically spaced integrated circuit line metallization with different via and metal selective deposition | |
| US10366900B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI802008B (en) | Interconnect structure including graphite and method forming same, and integrated circuit structure | |
| TW201939668A (en) | Method of manufacturing semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |