CN106328527A - Forming method of fin type field effect transistor - Google Patents

Abstract

A method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a plurality of fins; forming an isolation structure on the surface of the semiconductor substrate between adjacent fins, the isolation structure The surface of the fin is lower than the top surface of the fin; forming a gate structure across the fin, the gate structure covering part of the top and sidewall of the fin; using a first ion implantation in the isolation structure Implanting first ions, and making the first ions diffuse into the fins on both sides of the isolation structure, forming a first lightly doped region at the bottom of the fins; after the first ion implantation, the fins on both sides of the gate structure forming a source and drain region on the surface of the fin; performing a third ion implantation to form a second lightly doped region in the fin, and the second lightly doped region is located between the source and drain region and the first lightly doped region . The forming method of the fin field effect transistor improves the performance of the fin field effect transistor.

Description

Method for forming fin field effect transistor

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor.

Background technique

MOS transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and source and drain regions located in the semiconductor substrate on both sides of the gate structure. MOS transistors generate switching signals by applying a voltage to the gate and regulating the current through the channel at the bottom of the gate structure.

With the development of semiconductor technology, the ability of the traditional planar MOS transistor to control the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of the semiconductor substrate, a gate structure covering part of the top and side walls of the fin, located at the gate The source and drain regions in the fins on both sides of the pole structure.

The method for forming a fin field effect transistor includes: providing a semiconductor substrate, the surface of the semiconductor substrate has a raised fin and a gate structure across the fin, the gate structure covers part of the fin The top and sidewalls of the gate structure; sidewalls are formed on the sidewall surfaces on both sides of the gate structure; ion implantation is performed on the fins on both sides of the gate structure by using the sidewalls and the gate structure as a mask to form heavily doped source and drain regions.

As the feature size shrinks further, the performance and reliability of the FinFETs formed by the prior art are poor.

Contents of the invention

The problem solved by the present invention is to provide a method for forming a fin field effect transistor to improve the performance and reliability of the fin field effect transistor.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a plurality of fins; the surface of the semiconductor substrate between adjacent fins forming an isolation structure, the surface of the isolation structure is lower than the top surface of the fin; forming a gate structure across the fin, and the gate structure covers part of the top and sidewall of the fin; using the first Ion implantation implants first ions into the isolation structure, and diffuses the first ions into the fins on both sides of the isolation structure, forming a first lightly doped region at the bottom of the fin; after the first ion implantation, the Form source and drain regions on the fin surfaces on both sides of the gate structure; perform third ion implantation to form a second lightly doped region in the fin, and the second lightly doped region is located between the source and drain regions and the between the first lightly doped regions.

Optionally, the diffusion direction points to the fin along the direction perpendicular to the extending direction of the fin.

Optionally, when the formed FinFET is an N-type FinFET, the first ion implantation and the third ion implantation use N-type ions.

Optionally, when the formed FinFET is a P-type FinFET, the first ion implantation and the third ion implantation use P-type ions.

Optionally, the first ion implantation uses As ions, the implantation energy is 8KeV-25KeV, the implantation dose is 5E12atom/cm ² ˜8E13atom/cm ² , and the implantation angle is 0 degree.

Optionally, the ion used in the first ion implantation is P, the implantation energy is 5KeV˜15KeV, the implantation dose is 3E12atom/cm ² ˜6E13atom/cm ² , and the implantation angle is 0 degree.

Optionally, the first ion implantation uses B ions, the implantation energy is 6KeV˜10KeV, the dose range is 2E12atom/cm ² ˜6E13atom/cm ² , and the implantation angle is 0°.

Optionally, As is used for the third ion implantation, the implantation energy is 2KeV-5KeV, the implantation dose is 1E14atom/cm ² -5E15atom/cm ² , and the implantation angle is 0°-20°.

Optionally, the ion used in the third ion implantation is P, the implantation energy is 1KeV-3KeV, the implantation dose is 1E14atom/cm ² -5E15atom/cm ² , and the implantation angle is 0°-20°.

Optionally, B is used for the third ion implantation, the implantation energy is 1KeV-4KeV, the implantation dose is 1E14atom/cm ² -5E15atom/cm ² , and the implantation angle is 0°-20°.

Optionally, the fins have a width of 8nm˜20nm.

Optionally, the depth of the first lightly doped region in the fin is 5nm˜30nm.

Optionally, the depth of the second lightly doped region in the fin is 2nm˜15nm.

Optionally, the gate structure includes a gate dielectric layer across the fin and a gate electrode layer located on the surface of the gate dielectric layer.

Optionally, the method for forming the source and drain regions includes: epitaxially growing the material layer of the source and drain regions on the surface of the fin; doping ions in situ while epitaxially growing the material layer of the source and drain regions; The material layer is then heavily doped with ions by second ion implantation.

Optionally, when the formed Fin Field Effect Transistor is an N-type Fin Field Effect Transistor, the ions doped in the source and drain regions are N-type ions; when the formed Fin Field Effect Transistor is a P-type Fin Field Effect Transistor In the case of a field effect transistor, the ions doped in the source and drain regions are P-type ions.

Optionally, the N-type ions include P or As.

Optionally, the P-type ions include B or In.

Optionally, the ion concentration in the second lightly doped region is smaller than the ion concentration in the source-drain region and greater than the ion concentration in the first lightly doped region.

Optionally, the method further includes: performing annealing treatment after the third ion implantation.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The first ion implantation is used to implant first ions into the isolation structure, and the first ions are diffused into the fins on both sides of the isolation structure to form a first lightly doped region at the bottom of the fins. The first ions do not need to pass through the fin longitudinally to enter the bottom area of the fin, but enter the bottom area of the fin through diffusion. Since the width of the fin is small, the first ion can enter through diffusion. The fins on both sides of the isolation structure form a first lightly doped region at the bottom of the fin, and the first lightly doped region is distributed in the width direction of the fin, so that the energy of the first ion implantation can be reduced, Thereby, the damage to the fin portion by the first ion implantation can be reduced; in addition, since the first lightly doped region is formed in the bottom region of the fin portion, the subsequent third ion implantation can use lower implantation energy, which can reduce the subsequent third ion implantation. The implantation energy required by the triple ion implantation can reduce the implantation damage of the third ion implantation to the fin.

Further, a second lightly doped region located between the source and drain regions and the first lightly doped region is formed in the fin, the ion concentration in the second lightly doped region is lower than the ion concentration in the source and drain regions and The ion concentration is higher than that in the first lightly doped region, thereby forming a concentration gradient among the source-drain region, the second lightly doped region and the first lightly doped region, and further improving the junction capacitance of the FinFET.

Description of drawings

1 to 5c are structural schematic diagrams of the formation process of the fin field effect transistor in an embodiment of the present invention.

6 to 11c are structural schematic diagrams of the formation process of the fin field effect transistor in another embodiment of the present invention.

detailed description

As the feature size of the fin field effect transistor formed in the prior art is further reduced, the performance and reliability of the fin field effect transistor are poor.

1 to 5c are structural schematic diagrams of the formation process of the fin field effect transistor in an embodiment of the present invention.

1, FIG. 2a, FIG. 2b and FIG. 2c, a semiconductor substrate 100 is provided, the surface of the semiconductor substrate 100 has a fin 120 and a gate structure 130 across the fin 120, the gate structure 130 covers part of the fin 120 top and side walls.

Figure 2a is a cross-sectional view of the fin field effect transistor along the extending direction of the fin in Figure 1 (A-A1 axis), and Figure 2b is a cross-sectional view of the fin field effect transistor along the extending direction of the gate structure in Figure 1 (B-B1 axis) Figure 2c is a cross-sectional view of the fin field effect transistor along the extending direction parallel to the gate structure in Figure 1 and passing through the fin on one side of the gate structure (axis C-C1).

The gate structure 130 includes a gate dielectric layer 131 across the fin portion 120 and a gate electrode layer 132 covering the gate dielectric layer 131 .

There is also an isolation structure 110 on the semiconductor substrate 100 , the surface of the isolation structure 110 is lower than the top surface of the fin 120 , and the isolation structure 110 is used to electrically isolate adjacent fins 120 .

With reference to FIG. 3 a , FIG. 3 b and FIG. 3 c , sidewalls 140 are formed on both sidewalls of the gate structure 130 .

Referring to FIG. 4 a , FIG. 4 b and FIG. 4 c together, source and drain regions 150 are formed on the surfaces of the fins 120 on both sides of the gate structure 130 .

The method for forming the source-drain region 150 is: forming a sidewall material layer (not shown), the sidewall material layer covers the fin 120 and the gate structure 130, and etching the sidewall material layer to expose the gate structure 130 For the fins on both sides, fin sidewalls are formed on the sidewalls on both sides of the fin 120, and the fin sidewalls are lower than the top surface of the fin 120; the fin 120 is etched, so that the etched The fin portion 120 is flush with the sidewall of the fin portion; the source and drain region material layer is epitaxially grown on the surface of the etched fin portion 120; while the source and drain region material layer is epitaxially grown, in-situ doping or epitaxially grown The source-drain region material layer is then heavily doped by second ion implantation to form the source-drain region 150 .

Referring to FIG. 5 a , FIG. 5 b and FIG. 5 c together, a first ion implantation is performed to form a first doped region 160 in the fin portion 120 at the bottom of the source and drain regions 150 .

The function of the first doped region 160 is to reduce the concentration gradient between the source-drain region 150 and the bottom region of the fin 120 , thereby reducing the junction capacitance formed between the source-drain region 150 and the bottom region of the fin 120 .

The concentration of ions doped in the first doped region 160 is lower than the concentration of ions doped in the source and drain regions 150 .

After the first doped region 160 is formed, annealing is performed.

Research has found that the fin field effect transistors formed by the above method still have poor performance and reliability due to:

Since the first doped region is located at the bottom of the source and drain regions, that is, at the bottom region of the fin, high ion implantation energy is needed to implant the fin into the fin during the process of forming the first doped region. In the bottom region, the high-energy implantation energy causes serious damage to the source-drain region and the first doped region, and the damage is difficult to repair in the subsequent annealing process.

In order to reduce the implantation damage of the first ion implantation to the source drain region and the first doped region, the first doped region may be formed by thermal ion implantation, but the first doped region may be formed by thermal ion implantation. A lightly doped region will increase the complexity of the process, specifically: thermal ion implantation requires a higher temperature, usually in the temperature range of 400 degrees Celsius to 500 degrees Celsius, and requires an increase in heat source; photoresist will seriously occur in the temperature range deformation, and cannot be used as a mask for thermal ion implantation, so it is necessary to form a hard mask layer as a mask for thermal ion implantation, and forming the hard mask layer also requires the use of photoresist to define the pattern of the hard mask layer, The number of processes and the complexity are increased; the fins are easily damaged during the process of removing the hard mask layer.

The present invention provides a method for forming a fin field effect transistor according to another embodiment, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a plurality of fins; forming a fin field effect transistor on the surface of the semiconductor substrate between adjacent fins an isolation structure, the surface of the isolation structure is lower than the top surface of the fin; forming a gate structure across the fin, the gate structure covers part of the top and sidewalls of the fin; using the first ion Implanting first ions into the isolation structure, and causing the first ions to diffuse into the fins on both sides of the isolation structure, forming a first lightly doped region in the fins; after the first ion implantation, the Forming source and drain regions on the surfaces of the fins on both sides of the gate structure; performing a third ion implantation to form a second lightly doped region in the fin, and the second lightly doped region is located between the source and drain regions and the first lightly doped region. between the doped regions.

The first ions do not need to pass through the fin longitudinally to enter the bottom region of the fin, but enter the bottom region of the fin by diffusing the first ions in the doped isolation structure, since the width of the fin is relatively small Small, the first ions can enter the fins on both sides of the isolation structure through diffusion, and form a first lightly doped region at the bottom of the fin, and the first lightly doped region is distributed in the width direction of the fin , which can reduce the energy of the first ion implantation, thereby reducing the damage of the first ion implantation to the fin; in addition, since the first lightly doped region is formed in the bottom region of the fin, the subsequent third ion implantation can be By adopting lower implantation energy, the implantation energy required for the subsequent third ion implantation can be reduced, thereby reducing the implantation damage to the fin portion by the third ion implantation.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from the description herein, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below. Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention again.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 6 , FIG. 7 a , FIG. 7 b and FIG. 7 c together, a semiconductor substrate 200 is provided, and the surface of the semiconductor substrate 200 has a plurality of fins 220 .

Fig. 7a is a cross-sectional view of the fin field effect transistor along the extending direction of the fin in Fig. 6 (A-A1 axis), and Fig. 7b is a cross-sectional view of the fin field effect transistor along the extending direction of the gate structure in Fig. 6 (B-B1 axis) 7c is a cross-sectional view of the FinFET along the direction parallel to the extension of the gate structure in FIG. 6 and passing through the fin on one side of the gate structure (axis C-C1).

The semiconductor substrate 200 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 can also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide; the semiconductor substrate 200 can be a bulk material , can also be a composite structure, such as silicon-on-insulator; the semiconductor substrate 200 can also be other semiconductor materials, which will not be exemplified here. In this embodiment, the material of the semiconductor substrate 200 is silicon.

In this embodiment, the fin portion 220 is connected to the semiconductor substrate 200 in one piece, and the method for forming the fin portion 220 is: forming a patterned mask layer on the surface of the semiconductor substrate 200, and the patterned mask layer The layers define the positions of the fins 220 , and the semiconductor substrate 200 is etched using the patterned mask layer as a mask to form a plurality of protruding fins 220 on the surface of the semiconductor substrate 200 .

In another embodiment, the fin 220 may be formed by depositing a fin material layer on the semiconductor substrate 200 and then etching the fin material layer using the semiconductor substrate 200 as an etch stop layer.

The width of the fin portion 220 ranges from 8 nm to 20 nm.

The distance between adjacent fins 220 is 20 nm˜50 nm.

The fin portion 220 can also be doped with different impurity ions according to the type of the fin field effect transistor to be formed, so as to adjust the threshold voltage of the fin field effect transistor. When an N-type FinFET is to be formed, the fin 220 is doped with P-type ions; when a P-type FinFET is to be formed, the fin 220 is doped with N-type ions.

In this embodiment, the figure shows two fins 220 for illustration, and does not represent the number of fins 220 , and a plurality of fins 220 may be formed as required in an actual process.

Continuing to refer to FIG. 6 , FIG. 7 a , FIG. 7 b and FIG. 7 c , an isolation structure 210 is formed on the surface of the semiconductor substrate 200 between adjacent fins 220 , and the surface of the isolation structure 210 is lower than the top surface of the fins 220 .

The isolation structure 210 is used to electrically isolate adjacent fins 220 .

In this embodiment, the isolation structure 210 is a shallow trench isolation structure.

The material of the isolation structure 210 includes silicon oxide, silicon oxynitride or silicon hydroxide. In this embodiment, the material of the isolation structure 210 is silicon oxide.

The method of forming the isolation structure 210 is: forming an isolation structure material layer covering the surface of the semiconductor substrate 200 and the fins 220, and filling the grooves between adjacent fins 220; using a planarization process, such as a chemical mechanical mask film, planarizing the material layer of the isolation structure, using the top surface of the fin 220 as a stop layer; etching and removing part of the material layer of the isolation structure to form an isolation structure 210, the surface of the isolation structure 210 is lower than the fin 220 of the top surface.

The method for forming the material layer of the isolation structure is a deposition process, such as an atomic layer deposition process, a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. In this embodiment, the isolation structure material layer is formed by a plasma enhanced chemical vapor deposition process.

Continuing to refer to FIG. 6 , FIG. 7 a , FIG. 7 b and FIG. 7 c , a gate structure 230 is formed across the fin portion 220 , and the gate structure 230 covers part of the top and sidewalls of the fin portion 220 .

The gate structure 230 includes a gate dielectric layer 231 across the fin portion 220 and a gate electrode layer 232 covering the gate dielectric layer 231 .

The gate dielectric layer 231 is located on the surface of the isolation structure 210 and covers part of the top and sidewall of the fin 220 , and the gate electrode layer 232 is located on the surface of the gate dielectric layer 231 .

In this embodiment, the material of the gate dielectric layer 231 is silicon oxide, and the material of the gate electrode layer 232 is polysilicon. In other embodiments, the material of the gate dielectric layer 231 is a high-K dielectric material (K greater than 3.9), such as HfO ₂ , HfSiON, HfAlO ₂ , ZrO ₂ or Al ₂ O ₃ , and the material of the gate electrode layer 232 is metal Materials such as Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, Ta, TaN, W, WN or WSi.

The method for forming the gate structure 230 is: forming a gate dielectric material layer covering the isolation structure 210 and the fin portion 220; forming a gate electrode material layer on the surface of the gate dielectric material layer; Forming a patterned mask layer, the patterned mask layer defines the position of the formed gate structure 230; using the patterned mask layer as a mask, etching the gate dielectric material by an etching process layer and a layer of gate electrode material to form a gate structure 230 . Part of the fins 220 are exposed on both sides of the gate structure 230 .

The method for depositing the gate dielectric material layer may be metal organic vapor phase chemical deposition, atomic layer deposition process or plasma enhanced chemical vapor deposition process. The method for forming the gate electrode material layer may be physical vapor deposition or chemical vapor deposition, such as sputtering process, electroplating process, atomic layer deposition process or molecular beam epitaxy. In this embodiment, the gate dielectric material layer and the gate electrode material layer are formed by plasma enhanced chemical vapor deposition.

It should be noted that, in the process of forming the gate structure 230, the mask layer defining the position of the gate structure 230 may not be removed, and the mask layer (not shown) is retained on the top surface of the gate structure 230, and the subsequent The gate structure 230 can be protected during the process of performing the first ion implantation and forming the source and drain regions.

Referring to FIG. 8 a , FIG. 8 b and FIG. 8 c together, offset sidewalls 240 are formed on both sides of the gate structure 230 .

The offset sidewall 240 can protect the gate structure 230 .

The material of the offset sidewall 240 includes insulating materials such as silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the material of the offset sidewall 240 is silicon oxide.

The process of forming the offset sidewall 240 may be, for example, chemical vapor deposition. In this embodiment, the offset sidewall 240 is formed by in-situ oxidation.

Referring to FIG. 9a, FIG. 9b and FIG. 9c together, the first ion implantation 211 is used to implant first ions in the isolation structure 210 (refer to FIG. 8b and FIG. 8c), and the first ion diffusion 212 enters both sides of the isolation structure 210. The fin portion 220 is formed, and the first lightly doped region 214 is formed at the bottom of the fin portion 220 .

A first ion implantation is performed on the isolation structure 210 by using the offset sidewall 240 and the gate structure 230 as a mask, so that the isolation structure 210 is doped with first ions to form a doped isolation structure 213 . Due to the small width of the fin 210 , the first ions in the doped isolation structure 212 can enter the fins 220 on both sides of the isolation structure 213 through the diffusion 212 , forming the first lightly doped region 214 at the bottom of the fin 220 . The first lightly doped region 214 is located at the bottom region of the fin portion 220 , and the first lightly doped region 214 is distributed along the width direction of the fin portion 220 .

It should be noted that the first ions are mainly diffused 212 along a direction perpendicular to the extending direction of the fin portion 220 and pointing to the fin portion 220 to form a first lightly doped region 214 .

When the formed Fin Field Effect Transistor is an N-type Fin Field Effect Transistor, the first ion implantation 211 uses N-type ions, such as As or P; when the formed Fin Field Effect Transistor is a P-type Fin Field Effect Transistor For field effect transistors, the first ion implantation 211 uses P-type ions, including B, In and so on.

In one embodiment, the fin field effect transistor to be formed is an N-type fin field effect transistor, the ions used in the first ion implantation 211 are As, the implantation energy ranges from 8KeV to 25KeV, and the implantation dose ranges from 5E12atom/ ^cm2 ~8E13atom/cm ² , the injection angle is 0 degrees.

In another embodiment, the fin field effect transistor to be formed is an N-type fin field effect transistor, the ion used in the first ion implantation 211 is P, the implantation energy ranges from 5KeV to 15KeV, and the implantation dose ranges from 3E12atom/cm ² ~ 6E13atom/cm ² , the injection angle is 0 degrees.

In yet another embodiment, the fin field effect transistor to be formed is a P-type fin field effect transistor, the ion used in the first ion implantation 211 is B, the implantation energy ranges from 6KeV to 10KeV, and the implantation dose ranges from 2E12atom/cm ² ~ 6E13atom/cm ² , the injection angle is 0 degrees.

The depth of the first ion implantation 211 implanted into the isolation structure 210 is 5 nm˜30 nm.

The width of the fin 220 is very small, and the first ions in the doped isolation structure 213 can be doped into the fins 220 on both sides of the doped isolation structure 213 through the diffusion 212, forming the first light at the bottom of the fin 220. doped regions 214 , and the first lightly doped regions 214 are distributed along the width direction of the fin portion 220 . Since the first ions do not need to pass through the fin 220 longitudinally to enter the bottom region of the fin 220, but the first ions in the doped isolation structure 213 enter the bottom region of the fin 220 through diffusion, which can be Reduce the energy of the first ion implantation, thereby reducing the damage of the first ion implantation to the fin portion 210; in addition, since the first lightly doped region is formed in the bottom region of the fin portion 220, the subsequent third ion implantation can use The lower implantation energy can reduce the implantation energy required for the subsequent third ion implantation, thereby reducing the implantation damage of the third ion implantation to the fin.

Referring to FIG. 10 a , FIG. 10 b and FIG. 10 c together, gap sidewalls 241 are formed on both sides of the gate structure 230 .

The gap sidewall 241 is used to protect the gate structure 230 and define the distance between the subsequently formed source and drain regions 250 and the gate structure 230 .

The material of the spacer sidewall 241 includes insulating materials such as silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the material of the spacer sidewall 241 is silicon oxide.

The process of forming the gap sidewall 241 is to deposit a gap sidewall material layer, and the gap sidewall material layer covers the gate structure 230; anisotropic dry etching is used to perform an anisotropic dry etching on the gap sidewall material layer. Etching to form gap sidewalls 241 on both sides of the gate structure 230 .

Continuing to refer to FIG. 10 a , FIG. 10 b and FIG. 10 c , after the first ion implantation 211 , source and drain regions 250 are formed on the surfaces of the fins 220 on both sides of the gate structure 230 .

The method for forming the source-drain region 250 is: forming a sidewall material layer (not shown), the sidewall material layer covers the fin 220 and the gate structure 230, and etching the sidewall material layer to expose the gate structure 230 For the fins 220 on both sides, fin sidewalls are formed on the sidewalls on both sides of the fins 220, and the fin sidewalls are lower than the top surface of the fins 220; the fins 220 are etched so that after etching The fin portion 220 of the fin portion is flush with the sidewall of the fin portion; the source-drain region material layer is epitaxially grown on the surface of the etched fin portion 220; while the source-drain region material layer is epitaxially grown, ions are doped in situ or in-situ After epitaxially growing the material layer of the source and drain regions, a second ion implantation is performed to heavily dope ions to form the source and drain regions 250 .

When the formed Fin Field Effect Transistor is an N-type Fin Field Effect Transistor, the second ion implantation or the in-situ doping uses N-type ions, As or P, etc.; when the formed Fin Field Effect Transistor When the transistor is a P-type fin field effect transistor, the second ion implantation or the in-situ doping uses P-type ions, such as B or In.

In this embodiment, the source and drain regions 250 are formed by doping ions in situ while epitaxially growing the material layer of the source and drain regions.

It should be noted that, instead of etching the fin portion 220 , the material layer of the source and drain regions may be epitaxially grown directly on the surface of the fin portion 220 , and then the material layer of the source and drain region may be doped. At this time, there is no need to form fin sidewalls on the sidewalls of the fins 220 .

Referring to FIG. 11a, FIG. 11b and FIG. 11c, a third ion implantation is performed on the fin portion 220 to form a second lightly doped region 260 in the fin portion 220, and the second lightly doped region 260 is located between the source and drain regions 250 and between the first lightly doped regions 214 .

When the formed Fin Field Effect Transistor is an N-type Fin Field Effect Transistor, the third ion implantation uses N-type ions, such as As or P; when the formed Fin Field Effect Transistor is a P-type Fin Field Effect Transistor In the case of an effect transistor, the third ion implantation uses P-type ions, including B, In, and the like.

In one embodiment, the fin field effect transistor to be formed is an N-type fin field effect transistor, the ions used in the third ion implantation are As, the implantation energy ranges from 2KeV to 5KeV, and the implantation dose ranges from 1E14atom/cm ² to 5E15atom/cm ² , the injection angle is 0°-20°.

In another embodiment, the fin field effect transistor to be formed is an N-type fin field effect transistor, the ion used in the third ion implantation is P, the ion energy range of the third ion implantation is 1KeV～3KeV, and the dose range is 1E14atom/cm ² to 5E15atom/cm ² , and the injection angle is 0° to 20°.

In yet another embodiment, the fin field effect transistor to be formed is a P-type fin field effect transistor, the ion used in the third ion implantation is B, the ion energy range of the third ion implantation is 1KeV-4KeV, and the dose range is 1E14atom/cm ² to 5E15atom/cm ² , and the injection angle is 0° to 20°.

The depth of the third ion implantation into the fin portion 220 is 2˜15 nm.

Since the first lightly doped region 214 is formed in the bottom region of the fin portion 220, the third ion implantation can use lower implantation energy so that the formed second lightly doped region 260 is located at the source and drain region 250 and the first lightly doped region. Between the impurity regions 214 , the implantation energy required for the third ion implantation is reduced, so that the implantation damage to the fin portion 220 by the third ion implantation can be reduced.

After the third ion implantation, an annealing treatment is performed. During the annealing treatment, the first ions doped in the first lightly doped region 214 can be further diffused uniformly.

It should be noted that an annealing treatment can be performed respectively after the first ion implantation, the second ion implantation, and the third ion implantation to activate the dopant ions; an annealing treatment can also be performed after the third ion implantation is completed to activate the dopant ions. hetero ions.

The ion concentration in the second lightly doped region 260 is consistent with the ion concentration in the first lightly doped region 214, or the ion concentration in the second lightly doped region 260 is less than the ion concentration in the source and drain regions 250 and greater than the first The ion concentration in the lightly doped region 214 .

In this embodiment, the ion concentration in the second lightly doped region 260 is lower than the ion concentration in the source and drain regions 250 and greater than the ion concentration in the first lightly doped region 214, so that in the source and drain regions 250, the second lightly doped region A concentration gradient is formed between the impurity region 260 and the first lightly doped region 214 to further improve the junction capacitance of the FinFET.

The present invention has the following advantages:

The first ions in the doped isolation structure can enter the fin through diffusion to form a first lightly doped region in the fin, and the first lightly doped region is located at the bottom region of the fin. Since the first ions do not need to pass through the fin longitudinally to enter the bottom region of the fin, but the first ions in the doped isolation structure enter the fins on both sides of the doped isolation structure by diffusion, A first lightly doped region is formed at the bottom of the fin, and the first lightly doped region is distributed in the width direction of the fin, so that the energy of the first ion implantation can be reduced, thereby reducing the impact of the first ion implantation on the fin. In addition, since the first lightly doped region is formed in the fin bottom region, the subsequent third ion implantation can use lower implantation energy, which can reduce the implantation energy required for the subsequent third ion implantation, Therefore, the implantation damage to the fin portion by the third ion implantation can be reduced.

Further, a second lightly doped region located between the source and drain regions and the first lightly doped region is formed in the fin, the ion concentration in the second lightly doped region is lower than the ion concentration in the source and drain regions and The ion concentration is higher than that in the first lightly doped region, thereby forming a concentration gradient among the source-drain region, the second lightly doped region and the first lightly doped region, and further improving the junction capacitance of the FinFET.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a Fin Field Effect Transistor, comprising: providing a semiconductor substrate having a plurality of fins on a surface thereof; forming isolation structures on the surface of the semiconductor substrate between adjacent fins, the surfaces of the isolation structures being lower than the top surfaces of the fins; forming a gate structure across the fin, the gate structure covering part of the top and sidewall of the fin; using first ion implantation to implant first ions into the isolation structure, and making the first ions Diffusion into the fins on both sides of the isolation structure to form a first lightly doped region at the bottom of the fins; After the first ion implantation, source and drain regions are formed on the surfaces of the fins on both sides of the gate structure; A third ion implantation is performed to form a second lightly doped region in the fin, and the second lightly doped region is located between the source and drain regions and the first lightly doped region. 2 . The method for forming a fin field effect transistor according to claim 1 , wherein the direction of the diffusion points to the fin along a direction perpendicular to the extending direction of the fin. 3 . 3. The forming method of the Fin Field Effect Transistor according to claim 1, wherein when the Fin Field Effect Transistor formed is an N-type Fin Field Effect Transistor, the first ion implantation and the third ion implantation Implantation uses N-type ions. 4. The forming method of the Fin Field Effect Transistor according to claim 1, characterized in that, when the Fin Field Effect Transistor formed is a P-type Fin Field Effect Transistor, the first ion implantation and the third ion implantation Implantation uses P-type ions. 5. The method for forming a fin field effect transistor according to claim 3, wherein the ion used in the first ion implantation is As, the implantation energy is 8KeV-25KeV, and the implantation dose is 5E12atom/ ^cm2-8E13atom /cm ² , the injection angle is 0 degrees. 6. The method for forming a fin field effect transistor according to claim 3, wherein the ion used in the first ion implantation is P, the implantation energy is 5KeV-15KeV, and the implantation dose is 3E12atom/ ^cm2-6E13atom /cm ² , the injection angle is 0 degrees. 7. The method for forming a fin field effect transistor according to claim 4, wherein the ion used in the first ion implantation is B, the implantation energy is 6KeV-10KeV, and the dose range is 2E12atom/ ^cm2-6E13atom /cm ² , the injection angle is 0 degrees. 8. The method for forming a fin field effect transistor according to claim 3, wherein the ion used in the third ion implantation is As, the implantation energy is 2KeV-5KeV, and the implantation dose is 1E14atom/ ^cm2-5E15atom /cm ² , the injection angle ranges from 0° to 20°. 9. The method for forming a fin field effect transistor according to claim 3, characterized in that, the ion used in the third ion implantation is P, the implantation energy is 1KeV-3KeV, and the implantation dose is 1E14atom/ ^cm2-5E15atom /cm ² , the injection angle ranges from 0° to 20°. 10. The method for forming a fin field effect transistor according to claim 4, characterized in that, the ion used in the third ion implantation is B, the implantation energy is 1KeV-4KeV, and the implantation dose is 1E14atom/ ^cm2-5E15atom /cm ² , the injection angle ranges from 0° to 20°. 11 . The method for forming a fin field effect transistor according to claim 1 , wherein the width of the fin portion is 8nm˜20nm. 12 . The method for forming a fin field effect transistor according to claim 1 , wherein the depth of the first lightly doped region in the fin portion is 5 nm˜30 nm. 13 . 13 . The method for forming a fin field effect transistor according to claim 1 , wherein the depth of the second lightly doped region in the fin is 2 nm˜15 nm. 14 . 14. The method for forming a fin field effect transistor according to claim 1, wherein the gate structure comprises a gate dielectric layer across the fin and a gate electrode layer located on the surface of the gate dielectric layer . 15. The method for forming a fin field effect transistor according to claim 1, characterized in that, the method for forming the source and drain regions comprises: epitaxially growing a material layer for the source and drain regions on the surface of the fin; Simultaneous in-situ doping of ions in the material layer of the drain region or heavy doping of ions by second ion implantation after epitaxial growth of the material layer of the source and drain regions. 16. The method for forming a Fin Field Effect Transistor according to claim 15, wherein when the Fin Field Effect Transistor formed is an N-type Fin Field Effect Transistor, the doped ions in the source and drain regions are N-type ions; when the formed Fin Field Effect Transistor is a P-type Fin Field Effect Transistor, the ions doped in the source and drain regions are P-type ions. 17. The method for forming a fin field effect transistor according to claim 3 or 16, wherein the N-type ions include P or As. 18. The method for forming the FinFET according to claim 4 or 16, wherein the P-type ions include B or In. 19. The method for forming a fin field effect transistor according to claim 1, wherein the ion concentration in the second lightly doped region is lower than the ion concentration in the source and drain regions and greater than that in the first lightly doped region. Ion concentration in the lightly doped region. 20 . The method for forming a fin field effect transistor according to claim 1 , further comprising: performing annealing treatment after the third ion implantation. 21 .