CN106301393B - A Fast Calculation Method of Interleaving Address Based on Turbo Coding - Google Patents

Abstract

The invention relates to a fast calculation method of an interleaving address based on turbo coding. According to the requirements of the calculation algorithm of the interleaving address, after mathematical derivation and simulation confirmation, a turbo coding interleaving address calculation method based on addition logic is proposed. Compared with the existing satellite technology that adopts complex multiplication and division and modulo logic, or uses limited Block RAM resources, this patent solves the traditional interleaving address calculation method, which has complex calculation process logic, large FPGA resource occupation, and large delay in calculation results. Technical shortcomings greatly improve the efficiency and real-time performance of interleaving address calculations, and have broad application prospects in realizing Turbo-based encoding and decoding for all satellites.

Description

A Fast Calculation Method of Interleaving Address Based on Turbo Coding

technical field

The invention relates to a fast calculation method for interleaving addresses based on Turbo coding, which overcomes technical shortcomings such as complex calculation processes such as multiplication and division logic and Block RAM lookup tables, large FPGA resource occupation, and large delay in calculation results, and greatly improves the efficiency of interleaving address calculations. It is mainly used on the measurement and control platforms of various orbiting satellites, and belongs to the field of satellite measurement and control technology.

Background technique

Turbo coding, also known as parallel concatenated convolutional code, belongs to a high-gain channel coding in the field of measurement and control or communication. In the turbo coding process, in order to increase the coding gain, reduce the system power consumption, and reduce the effective radiation power of the transmitting antenna, the data reading address of the encoder b (that is, the interleaving address) is required to be random, which needs to be calculated according to the established turbo coding algorithm.

The interleaving address calculation algorithm based on multiplication and division logic strictly follows the given algorithm of Turbo coding, and the interleaving address search algorithm based on Memory resources can obtain the interleaving address, but these designs have the following deficiencies: (1) The interleaving address calculation algorithm based on multiplication and division logic has its own It is characterized by a large amount of logic operations, complex implementation, and takes up more hardware resources (multiplier IP, Slices, and lookup tables LUTs), and the delay in calculation results is large; (2) The interleaving address lookup algorithm based on Memory resources is characterized by this Simple and intuitive, the complex multiplication, division, shift and modulus logic operations are delivered to the matlab program. The algorithm uses Slices and LUTs to greatly reduce hardware resources, but the device occupies 6 of the 96 Block RAM resources. For the non-coherent spread spectrum multi-station orbit determination requirements required by the background model, the 6 Block RAM block resources are very precious, and it may even cause the given hardware platform to fail to complete the model task requirements.

With the increase of the transmission information rate, the interleaving address calculation technology based on multiplication and division logic or memory resources has been unable to meet the requirements of low resource occupancy, reliable calculation process, and small delay of calculation results.

Contents of the invention

The technical problem of the present invention is: to overcome the deficiencies of the prior art, to provide a fast calculation method for interleaving addresses based on Turbo coding, to realize the calculation of interleaving addresses by using addition logic, and to satisfy the high efficiency and accuracy of the calculation of interleaving addresses by satellites to the greatest extent and fast demand.

Technical solution of the present invention is:

A fast calculation method for interleaving addresses based on Turbo coding, the steps are as follows:

(1) Complete the AOS (Advanced On-Orbit System) framing of the data to be transmitted according to the established format of Turbo (parallel cascaded convolution) encoding. The section length is Nb, that is, Nb*8 bits;

(2) Cache valid data into the FPGA dual-port Block RAM in the form of a bit stream, the RAM bit width is 1, and the depth must not be less than Nb*8;

(3) The input data Dataa of the component encoder a needs to be read sequentially from the RAM. The sequential reading refers to starting from the zero address in the process of reading the number. Every time 1 bit of stored data is read, the address is increased by 1, and the code is recorded. The data address of device a is order, and the value range is 0~Nb*8-1;

(4) The input data of component encoder b is also the data stored in Block RAM, but the data acquisition process is random, and the data reading address needs to be calculated in real time. Note that the data address of encoder b is Interl, and the value range is also 0~Nb*8 -1;

(5) Take the data address order of encoder a as a parameter, and calculate the data interleaving address of encoder b by referring to the parity characteristics and value range of order. If the order is an even number, use (6)～( 13) Calculations are performed on different branches. If the order is an odd number, then branch (14) is directly used for calculation;

(6) If order is an even number and order is equal to zero, then Interl=Interl+0x0003, then enter step (15);

(7) If order is an even number, order is greater than 0 and less than 2040, then Interl=Interl+0x0081, then enter step (15);

(8) If order is an even number, and order equals 2040, then Interl=Interl+0x007F, then enter step (15);

(9) If the order is an even number, and the order is greater than 2040 and less than 4080, then Interl=Interl+0x0051, then enter step (15);

(10) If order is an even number, and order is equal to 4080, then Interl=Interl+0x0057, then enter step (15);

(11) If the order is an even number, and the order is greater than 4080 and less than 6120, then Interl=Interl+0x00D1, then enter step (15);

(12) If order is an even number, and order is equal to 6120, then Interl=Interl+0x00CF, then enter step (15);

(13) If the order is an even number, and the order is greater than 6120 and less than Nb*8-1, then Interl=Interl+0x00B1, then enter step (15);

(14) If the address order of encoder a input data is an odd number, that is, order (0) is not 0 after being converted into hexadecimal, then Interl=Interl+0x00A7, then enter step (15) afterwards;

(15) Carry out 8160 modulus to calculated Interl, the remainder that the gained is less than 8160 is the interleaving address Interl corresponding to the current sequential address order;

(16) Use Interl as the data address input by the encoder b, read the corresponding interleaved data Datab from the Block RAM, and send it to the Turbo encoder together with the Dataa read from the sequential address order to realize channel Turbo encoding.

The Turbo coding gain is 8dB, and the coding ratio has 4 levels of 1/2, 1/3, 1/4 and 1/6.

Compared with the prior art, the present invention has the beneficial effects that: the present invention follows the given interleaving address calculation algorithm of Turbo coding, and through mathematical derivation and simulation confirmation, it proposes the fast calculation of interleaving address realized by addition logic for the first time, which solves the problem based on The technical problem of complex multiplication and division logic calculations and large delays in the results breaks through the engineering bottleneck based on Memory occupying a lot of hardware resources, improves the data throughput of Turbo encoding, and reduces the harsh demand for hardware resources.

Description of drawings

Fig. 1 is a flowchart of the present invention;

Fig. 2 is that the present invention relates to Turbo encoding block diagram;

Fig. 3 is that the present invention relates to Turbo encoding frame structure;

Fig. 4 is a schematic diagram of interleaving addresses involved in the present invention.

Detailed ways

Specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

The integrated system of measurement, control and digital transmission aims at the model requirements of the transmission of high-speed digital transmission data in the measurement and control channel, combined with the non-coherent spread spectrum measurement and control system, a new type of measurement and control system is proposed after adding the function of distance measurement and speed measurement, mainly used to establish reliable communication between the satellite and the ground. And stable telemetry, remote control, distance measurement and speed measurement and high-speed data transmission links.

When the spread spectrum transponder works in the integrated system of measurement, control and data transmission, the receiving ground measurement and control station transmits uplink 1-channel remote control and 3-channel ranging signals, and the format and characteristics are the same as those of the non-coherent spread spectrum measurement and control system.

The downlink of the transponder follows the AOS protocol of the advanced on-orbit system (advanced on-orbit system, the abbreviation of Advanced Orbiting Systems, supports the transmission of images, voice, high-speed, low-speed various data in any direction, and supports asynchronous, synchronous, isochronous transmission Mode and bit stream, subpacket and other transmission services, can transmit a variety of different types of data on a physical channel, is a flexible and convenient data processing service), adopts isochronous insertion services, and uses distance measurement and speed measurement information Insert it into the downlink transmission frame of high-speed data transmission, then adopt 1/3 or 1/6 channel Turbo coding, adopt BPSK method to phase modulate the carrier, after power amplification and filtering processing, send it to the ground station through the measurement and control antenna.

In the process of implementing Turbo channel coding, the fast calculation of the interleaving address is a technical difficulty, and the basic requirements are less FPGA resources, a small delay in the calculation results, and simple and reliable calculation logic.

Compared with the existing satellite technology using complex multiplication and division and modulo logic, or using limited BlockRAM resources, the present invention solves the traditional interleaving address calculation method with complex calculation process logic, large FPGA resource occupation, and large delay in calculation results. The disadvantage is that it greatly improves the efficiency and real-time performance of interleaving address calculation, and has broad application prospects in all satellites to realize Turbo-based encoding and decoding.

FIG. 1 shows a flow chart of the present invention, and FIG. 2 shows that the present invention involves the principle of Turbo coding. As shown in Fig. 2, Turbo coding is composed of modules such as input buffer, data interleaving, component coding, output buffer and frame header multiplexing, and the present invention discusses the data interleaving part.

As shown in Figure 3, the turbo encoding frame structure is composed of frame synchronization header ASM, leading header, insertion area, data field, and transmission frame CRC modules. The background model involved in this patent uses this frame format to complete the integration of measurement, control and data transmission system.

As shown in FIG. 4 , the present invention relates to interleaving addresses, that is, encoder a data is sequentially read from RAM, while data input to encoder b is randomly read from RAM, that is, how to realize fast and efficient calculation of interleaving addresses.

As shown in Figure 1-4, a kind of interleaving address fast calculation method based on Turbo coding that the present invention proposes, the implementation steps are as follows:

(1) The AOS framing of the data to be transmitted is completed according to the established format of Turbo encoding. The number of bytes in the frame length of the entire frame is recorded as Na (1024 bytes), and the effective data byte length (participating in Turbo encoding) is Nb (1020 bytes) byte), that is, Nb*8 bits (8160 bits);

(2) Cache the effective data into the FPGA dual-port Block RAM in the form of a bit stream. The bit width of the Block RAM is 1, and the depth must not be less than Nb*8;

(3) The input data Dataa of the component encoder a needs to be read sequentially from the RAM. The sequential reading refers to starting from the zero address in the process of reading the number. Every time 1 bit of stored data is read, the address is increased by 1, and the code is recorded. The data address of device a is order, and the value range is 0~Nb*8-1;

(4) The input data of component encoder b is also the data stored in Block RAM, but the data acquisition process is random, and the address of the read data needs to be calculated in real time. Note that the data address of encoder b is Interl, and the value range is also 0~Nb *8-1;

(5) Take the data address order of encoder a as a parameter, and calculate the data interleaving address of encoder b by referring to the parity characteristics and value range of order. If the order is an even number, use (6)～( 13) Calculations are performed on different branches. If the order is an odd number, then branch (14) is directly used for calculation;

(6) If order is an even number and order is equal to zero, then Interl=Interl+0x0003, then enter step (15);

(7) If order is an even number, order is greater than 0 and less than 2040, then Interl=Interl+0x0081, then enter step (15);

(8) If order is an even number, and order equals 2040, then Interl=Interl+0x007F, then enter step (15);

(9) If the order is an even number, and the order is greater than 2040 and less than 4080, then Interl=Interl+0x0051, then enter step (15);

(10) If order is an even number, and order is equal to 4080, then Interl=Interl+0x0057, then enter step (15);

(11) If the order is an even number, and the order is greater than 4080 and less than 6120, then Interl=Interl+0x00D1, then enter step (15);

(12) If order is an even number, and order is equal to 6120, then Interl=Interl+0x00CF, then enter step (15);

(13) If the order is an even number, and the order is greater than 6120 and less than Nb*8-1, then Interl=Interl+0x00B1, then enter step (15);

(14) If the address order of encoder a input data is an odd number, that is, order (0) is not 0 after being converted into hexadecimal, then Interl=Interl+0x00A7, then enter step (15) afterwards;

(15) Carry out 8160 modulus to calculated Interl, and the resulting remainder (less than 8160) is the interleaving address Interl corresponding to the current sequential address order;

(16) Use Interl as the data address input by the encoder b, read the corresponding interleaved data Datab from the Block RAM, and send it to the Turbo encoder together with the Dataa read from the sequential address order to realize channel Turbo encoding.

The present invention is currently using this method on launched model satellites. The entire satellite test shows that after the method of the present invention is applied, the technical requirements of Turbo coding for efficient, accurate and fast interleaving address calculations are met, and the data of Turbo coding is greatly improved. Throughput, while reducing the harsh requirements for hardware resources, effectively ensuring the reliable establishment of measurement and control links and data transmission requirements.

The content that is not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims (2)

1. a kind of interleaving address quick calculation method based on Turbo coding, it is characterised in that steps are as follows:

(1) the Advanced Orbiting Systems AOS group of completion data to be transferred is required according to parallel cascade convolution Turbo coding established form Frame, whole frame frame length byte number are denoted as Na, wherein the valid data byte length for participating in Turbo coding is Nb, i.e. Nb*8 bit；

(2) valid data are cached in a manner of bit stream into FPGA dual-port Block RAM, Block RAM bit width is 1, deep Degree need to be not less than Nb*8；

(3) component coder a input data Dataa needs sequence successively to read from Block RAM, and the sequence, which is successively read, to be referred to During access since zero-address, 1 bit canned data of every reading, address adds 1, and the data address of note encoder a is Order, value range are 0~Nb*8-1；

(4) component coder b input data is also Block RAM stored data, but process of fetching is random, data read address It then needs by being calculated in real time, note encoder b data address is Interl, and value range is also 0~Nb*8-1；

(5) using the data address order of encoder a as parameter, referring to the odd even characteristic and value range calculation code device of order The different branches in (6)~(13) are taken to carry out according to the value range of order if order is even number in the data interlacing address of b It calculates, if order is odd number, (14) branch is directly taken to be calculated；

(6) if order is even number and order is equal to zero, Interl=Interl+0x0003, (15) are then entered step later；

(7) if order is even number, order is greater than 0 and less than 2040, then Interl=Interl+0x0081, then enters later Step (15)；

(8) if order is even number, order is equal to 2040, then Interl=Interl+0x007F, then enters step later (15)；

(9) if order is even number, order is greater than 2040 and less than 4080, then Interl=Interl+0x0051, later then into Enter step (15)；

(10) if order is even number, order is equal to 4080, then Interl=Interl+0x0057, then enters step later (15)；

(11) if order is even number, order is greater than 4080 and less than 6120, then Interl=Interl+0x00D1, later then Enter step (15)；

(12) if order is even number, order is equal to 6120, then Interl=Interl+0x00CF, then enters step later (15)；

(13) if order is even number, order is greater than 6120 and is less than Nb*8-1, then Interl=Interl+0x00B1, later Then enter step (15)；

(14) if the address order of encoder a input data is odd number, that is, order (0) is not 0 after being converted into 16 systems, then Interl=Interl+0x00A7 then enters step (15) later；

(15) to gained Interl 8160 modulus of progress are calculated, remainder of the gained less than 8160 is current order address order Corresponding interleaving address Interl；

(16) data address for using Interl to input as encoder b reads corresponding interleaving data from Block RAM Datab is sent together with the Dataa read from sequence address order to Turbo encoder, realizes channel Turbo coding.

2. the interleaving address quick calculation method according to claim 1 based on Turbo coding, it is characterised in that: described Turbo coding gain is 8dB, and coding ratio has 1/2,1/3,1/4 and 1/6 to amount to 4 grades.