CN106298790B - The forming method of flash memory - Google Patents
The forming method of flash memory Download PDFInfo
- Publication number
- CN106298790B CN106298790B CN201610828320.5A CN201610828320A CN106298790B CN 106298790 B CN106298790 B CN 106298790B CN 201610828320 A CN201610828320 A CN 201610828320A CN 106298790 B CN106298790 B CN 106298790B
- Authority
- CN
- China
- Prior art keywords
- side wall
- ion
- floating gate
- source
- structural membrane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 76
- 238000007667 floating Methods 0.000 claims abstract description 142
- 239000012528 membrane Substances 0.000 claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 150000002500 ions Chemical class 0.000 claims description 66
- 238000002513 implantation Methods 0.000 claims description 33
- 238000005516 engineering process Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000007943 implant Substances 0.000 claims description 16
- -1 boron ion Chemical class 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 3
- 229910001449 indium ion Inorganic materials 0.000 claims description 3
- 241000208340 Araliaceae Species 0.000 claims 4
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 4
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 4
- 235000008434 ginseng Nutrition 0.000 claims 4
- 239000010410 layer Substances 0.000 description 130
- 239000000463 material Substances 0.000 description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 239000000377 silicon dioxide Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 238000000926 separation method Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000000170 cell membrane Anatomy 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of forming method of flash memory, including：Semiconductor substrate is provided, there is floating gate structural membrane and the control gate structural membrane in floating gate structural membrane in semiconductor substrate；Several discrete dielectric layers are formed in control gate structural membrane, and there is the first opening between adjacent dielectric；The first side wall is formed in the first opening sidewalls；The control grid structural membrane and floating gate structural membrane that the first open bottom is removed using the first side wall as exposure mask form the second opening in the first open bottom；Source region is formed in the semiconductor substrate of the second open bottom, and there is source ion in source region；After forming source region, the second side wall is formed in the second opening sidewalls；After forming the second side wall, the doping compensation ion in source region, the conduction type of the counterion and the conduction type of source ion are identical；In source region after doping compensation ion, line layer in source is formed in the first opening and the second opening.The method is avoided that flash memory erasing failure.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of flash memory.
Background technique
Flash memory is a kind of important device in IC products.Flash memory is mainly characterized by being not added
The information of storage can be kept in the case where voltage for a long time.Flash memory has integrated level height, faster access speed and is easy to
The advantages that erasing, thus be widely used.
Flash memory is divided into two types：Gatestack (stack gate) flash memory and divide grid (split gate) fast
Flash memory.There is erasing in gatestack flash memory.Split-gate flash memory due to higher programming efficiency,
Can be to avoid excessive erasable problem in erasable function, thus it is widely used in all kinds of such as smart cards, SIM card, microcontroller
In the electronic products such as device, mobile phone.
However, there is serious erasing failure in existing Split-gate flash memory.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of flash memory, wipes and loses to avoid flash memory
Effect.
To solve the above problems, the present invention provides a kind of forming method of flash memory, including：Semiconductor lining is provided
Bottom has floating gate structural membrane and the control gate structural membrane in floating gate structural membrane in the semiconductor substrate；It is controlling
Several discrete dielectric layers are formed on grid structure film, and there is the first opening between adjacent dielectric；In the first opening sidewalls shape
At the first side wall；The control grid structural membrane and floating gate structural membrane that the first open bottom is removed using the first side wall as exposure mask,
First open bottom forms the second opening；Form source region in the semiconductor substrate of the second open bottom, have in source region source from
Son；After forming source region, the second side wall is formed in the second opening sidewalls；After forming the second side wall, the doping compensation ion in source region,
The conduction type of the counterion and the conduction type of source ion are identical；In source region after doping compensation ion, opened first
Source line layer is formed in mouth and the second opening.
Optionally, the technique of doping compensation ion is ion implantation technology in the source region.
Optionally, when the conduction type of the source ion is p-type, the conduction type of the counterion is p-type.
Optionally, the parameter of the ion implantation technology includes：The ion used for boron ion, Implantation Energy be 2KeV~
4KeV, implantation dosage 1E15atom/cm2~1E16atom/cm2, implant angle is 70 degree~90 degree.
Optionally, the parameter of the ion implantation technology includes：The ion used for indium ion, Implantation Energy be 5KeV~
20KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
Optionally, when the conduction type of the source ion is N-type, the conduction type of the counterion is N-type.
Optionally, the parameter of the ion implantation technology includes：The ion used for phosphonium ion, Implantation Energy be 2KeV~
5KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
Optionally, the parameter of the ion implantation technology includes：The ion used for arsenic ion, Implantation Energy be 3KeV~
15KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
Optionally, the semiconductor substrate has wordline bitline regions and source line floating gate region, and source line floating gate region is located at phase
Between adjacent wordline bitline regions；The floating gate structural membrane is located in the semiconductor substrate of part source line floating gate region, and it is floating to be located at source line
Floating gate structural membrane in the semiconductor substrate of grid region also extends in the semiconductor substrate of the wordline bitline regions；The control grid
Structural membrane is located in semiconductor substrate and floating gate structural membrane；The control gate structure of dielectric layer covering wordline bitline regions
Film.
Optionally, after forming the source line layer, further include：Remove the dielectric layer and control gate structure of wordline bitline regions
Film forms control gate structure in the first side wall bottom；Third side is formed in the control gate structure and the first side wall side wall
Wall；Using first side wall, source line layer and third side wall as exposure mask, the part floating gate structural membrane of wordline bitline regions is removed,
Floating gate structure is formed on the bottom for controlling gate structure and third side wall；In the third side wall side wall and floating gate structure exposed
Side wall forms word line structure.
Compared with prior art, technical solution of the present invention has the following advantages that：
In the forming method for the flash memory that technical solution of the present invention provides, source is formed before forming the second side wall
Area, so that source region is in capacitor increasing larger perpendicular to the size on the second opening sidewalls direction, that source region and floating gate structure are constituted
Greatly, therefore the voltage on the line layer of source can be more coupled in floating gate structure, is conducive to flash memory and is programmed.
After forming the second side wall, the doping compensation ion in source region.Due to the conduction type of the counterion and leading for source ion
Electric type is identical, therefore the counterion can compensate for loss of the source ion in the second side wall forming process in source region.Make
The concentration for obtaining source ion in the region of source region and the contact of source line layer increases.So that the contact resistance between source line layer and source region
It reduces.Therefore, the electric current that flash memory is read during erasing operation is larger, to avoid word line structure erasing failure.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of Split-gate flash memory；
Fig. 2 to Figure 17 is the structural schematic diagram of flash memory forming process in one embodiment of the invention.
Specific embodiment
As described in background, there are serious erasings to fail for existing Split-gate flash memory.
Fig. 1 is a kind of structural schematic diagram of Split-gate flash memory, and Split-gate flash memory includes：Semiconductor substrate 100；
Gate structure unit, gate structure unit include two discrete gate structures, have groove (not shown) between gate structure,
Gate structure includes the floating gate structure 120 on part semiconductor substrate 100 and the control in floating gate structure 120
Gate structure 121；First side wall 130 is located on control gate structure 121；Second side wall 131 is located at recess sidewall；Source line layer
140, between the first side wall 130 and between the second side wall 131；Word line structure is located at gate structure, the first side wall 130
With the two sides side wall of source line layer 140；Source region 150, in the semiconductor substrate 100 of the source bottom Xian Ceng140.
A kind of method forming above-mentioned Split-gate flash memory includes：Semiconductor substrate, the semiconductor substrate tool are provided
There are wordline bitline regions and source line floating gate region, source line floating gate region is between adjacent word line bitline regions；It is served as a contrast in part semiconductor
The floating gate structural membrane and control grid structural membrane of the wordline bitline regions and source line floating gate region are developed across on bottom；Form medium
Layer, the dielectric layer cover the floating gate structural membrane and control grid structural membrane of wordline bitline regions, have between adjacent dielectric
First opening；The first side wall is formed in the first opening sidewalls；The floating gate of the first open bottom is removed using the first side wall as exposure mask
Structural membrane and control grid structural membrane form the second opening in the first open bottom；In the semiconductor substrate of the second open bottom
Middle formation source region；After forming source region, the second side wall is formed in the second opening sidewalls；After forming the second side wall, first opening and
Source line layer is formed in second opening；After the line layer of formation source, dielectric layer, control grid structural membrane and the floating gate of wordline bitline regions are removed
Pole structural membrane forms control gate structure and floating gate structure；Then in the first side wall, the control gate structure and floating exposed
Gate structure sidewall forms word line structure.
In the above method, it is initially formed source region, it is rear to form the second side wall.It is initially formed source region, rear the reason of forming the second side wall
It is：So that source region is in capacitor larger perpendicular to the size on the second opening sidewalls direction, that source region and floating gate structure are constituted
Increase, therefore the voltage on the line layer of source can be more coupled in floating gate structure, in flash memory programmed
The voltage in floating gate structure is improved in journey, is conducive to Split-gate flash memory and is programmed.
However, there are serious erasing Problem of Failure for the Split-gate flash memory of above method formation, it has been investigated that, it is former
Because being：
During forming the second side wall, etching can be caused to be lost to the source region exposed, be easy the source in source region
The corresponding region removal of the peak concentration of ion, causes the concentration of source ion in the region of source region and the contact of source line layer lower than described
Peak concentration, thus cause the contact resistance of source line layer and source region larger.And then cause in Split-gate flash memory erasing operation
The electric current read in the process is too small.And sentenced whether Split-gate flash memory erasing failure according to the size of the electric current of the reading
It is disconnected.If the electric current of the reading is too small, it is judged as Split-gate flash memory erasing failure.
On this basis, the present invention provides a kind of forming method of flash memory, including：Semiconductor substrate, institute are provided
Stating has floating gate structural membrane and the control gate structural membrane in floating gate structural membrane in semiconductor substrate；In control grid structure
Several discrete dielectric layers are formed on film, and there is the first opening between adjacent dielectric；First is formed in the first opening sidewalls
Side wall；The control grid structural membrane and floating gate structural membrane that the first open bottom is removed using the first side wall as exposure mask, are opened first
Second opening is formed on mouth bottom；Source region is formed in the semiconductor substrate of the second open bottom, and there is source ion in source region；It is formed
After source region, the second side wall is formed in the second opening sidewalls；After forming the second side wall, the doping compensation ion in source region, the benefit
The conduction type for repaying ion is identical with the conduction type of source ion；In source region after doping compensation ion, in the first opening and the
Source line layer is formed in two openings.
In the method, source region is formed before forming the second side wall, so that source region is perpendicular to the second opening sidewalls side
Upward size is larger, and the capacitor that source region and floating gate structure are constituted increases, therefore can be more by the voltage on the line layer of source
It is coupled in floating gate structure, is conducive to flash memory and is programmed.After forming the second side wall, the doping compensation in source region
Ion.Since the conduction type of the counterion and the conduction type of source ion are identical, the counterion can be mended
Repay loss of the source ion in the second side wall forming process in source region.So that source ion in the region of source region and the contact of source line layer
Concentration increases.So that the contact resistance between source line layer and source region reduces.Therefore, flash memory is in erasing operation process
The electric current of middle reading is larger, to avoid word line structure erasing failure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 17 is the structural schematic diagram of flash memory forming process in one embodiment of the invention.
With reference to Fig. 2, semiconductor substrate 200 is provided.
The semiconductor substrate 200 provides technique platform to form flash memory.
The semiconductor substrate 200 has wordline bitline regions and source line floating gate region, and source line floating gate region is located at adjacent words
Between line bitline regions.
The material of the semiconductor substrate 200 can be silicon, germanium or SiGe.The semiconductor substrate 200 can be with
Silicon-on-insulator (SOI), germanium on insulator (GeOI) or germanium on insulator SiClx (SiGeOI).It is described partly to lead in the present embodiment
The material monocrystalline silicon of body substrate 200.
Then, floating gate structural membrane and control gate structural membrane are formed.
In the present embodiment, the floating gate structural membrane is located in part source line floating gate region semiconductor substrate 200, and is located at source
Floating gate structural membrane in line floating gate region semiconductor substrate 200 also extends in wordline bitline regions semiconductor substrate 200；Control
Controlling grid structural film is located in semiconductor substrate 200 and floating gate structural membrane.
Floating gate structural membrane is specifically introduced below with reference to Fig. 3 to Fig. 7 and controls the forming process of grid structural membrane.
With reference to Fig. 3, initial floating gate structural membrane 210 is formed on semiconductor substrate 200；In the initial floating gate structure
The first mask layer 220 is formed on film 210.
The initial floating gate structural membrane 210 includes initial floating gate oxide film and initial in initial floating gate oxide film
Floating gate film.
Initial floating gate film and semiconductor substrate 200 is isolated in the initial floating gate oxide film.The initial floating gate oxide film is used
In being subsequently formed floating gate oxide film.The formation process of the initial floating gate oxide film is depositing operation or oxidation technology.It is described first
The material of beginning floating gate oxide film is silica.
The initial floating gate film is for being subsequently formed floating gate film.The formation process of the initial floating gate film is depositing operation,
Such as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition process.Institute
The material for stating initial floating gate film is polysilicon.
First mask layer 220 is for being subsequently formed mask layer.The formation work of first mask layer 220
Skill is depositing operation, such as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemistry gas
Phase depositing operation.First mask layer 220 can be single layer structure, or laminated construction.When the first exposure mask material
When the bed of material 220 is single layer structure, the material of the first mask layer 220 can be silicon nitride, silicon oxynitride or fire sand.When
When first mask layer 220 is laminated construction, each layer of material in laminated construction can for silicon nitride, silicon oxynitride or
Fire sand.
The thickness of the initial floating gate oxide film, initial floating gate film and the first mask layer 220 can be according to technique need
It wants and sets.
With reference to Fig. 4, graphical first mask layer 220 (referring to Fig. 3), (reference of initial floating gate structural membrane 210
Fig. 3) with part semiconductor substrate 200, floating gate structural membrane 211 is formed in the semiconductor substrate 200 and is located at floating gate
The first mask layer 221 in structural membrane 211, is formed simultaneously groove 230, and the groove 230 is located at adjacent floating gate structure film
211, between adjacent first mask layer 221 and in semiconductor substrate 200.
The floating gate structural membrane 211 is located in part source line floating gate region semiconductor substrate 200, and is located at source line floating gate region
Floating gate structural membrane 211 in semiconductor substrate 200 also extends in wordline bitline regions semiconductor substrate 200.
The floating gate structural membrane 211 includes the floating gate oxide film on the part semiconductor substrate 200 and is located at floating gate
Floating gate film on oxidation film.The floating gate oxide film is located in part source line floating gate region semiconductor substrate 200, and it is floating to be located at source line
Floating gate oxide film in grid region semiconductor substrate 200 also extends in wordline bitline regions semiconductor substrate 200.
In the present embodiment, patterned photoresist layer, the patterned photoetching are formed on the first mask layer 220
Glue-line defines the position of groove 230；Using the patterned photoresist layer as exposure mask, etching the first mask layer 220, just
Beginning floating gate structural membrane 210 and part semiconductor substrate 200 form groove 230, floating gate structural membrane 211 and the first mask layer
221；Then the patterned photoresist layer is removed.
In other embodiments, patterned photoresist layer, the patterned light are formed on the first mask layer
Photoresist layer defines the position of groove；Using the patterned photoresist layer as exposure mask, the first mask layer is etched, forms the
One mask layer；Then it using first mask layer as the initial floating gate structural membrane of mask etching and part semiconductor substrate, is formed
Groove, floating gate structural membrane；After forming the first mask layer, the patterned photoresist layer is removed.
With reference to Fig. 5, separation layer 240 is formed in groove 230 (referring to Fig. 4)；After forming separation layer 240, removal first is covered
Film layer 221 (refers to Fig. 4).
The material of the separation layer 240 is silica.
The top surface of the separation layer 240 is higher than the top surface of floating gate structural membrane 211；Or separation layer 240
Top surface is higher than 200 surface of semiconductor substrate and is lower than the top surface of floating gate structural membrane 211；Or separation layer 240
Top surface is flushed with the top surface of floating gate structural membrane 211.
In the present embodiment, the top surface of the separation layer 240 is higher than the top surface of floating gate structural membrane 211.
In conjunction with reference Fig. 6 and Fig. 7, Fig. 7 is the sectional view obtained along cutting line A-A1 in Fig. 6, in semiconductor substrate 200
Grid structural membrane 250 is controlled with being formed in floating gate structural membrane 211.
Specifically, the control grid structural membrane 250 covers separation layer 240 and floating gate structural membrane 211.
The control grid structural membrane 250 includes control gate dielectric film and the control grid electrode on control gate dielectric film
Film.The control gate dielectric film covering floating gate structural membrane 211 and separation layer 240.
In the present embodiment, the control gate dielectric film is laminated construction, and the control gate dielectric film includes the first control gate
Deielectric-coating controls on gate dielectric film positioned at the second control gate dielectric film on the first control gate dielectric film surface and positioned at second
Third controls gate dielectric film.
The material of the first control gate dielectric film and third control gate dielectric film is silica.Second control gate is situated between
The material of plasma membrane is silicon nitride.
The advantages of control gate dielectric film is laminated construction be：So that the dielectric constant of control gate dielectric film is larger, control
The numerical value of gate electrode film processed, control gate dielectric film and the capacitor constituted with floating gate film increases, and the voltage on subsequent control grid can
More it is coupled on floating gate, is conducive to the progress of the programming of flash memory.
In other embodiments, the control gate dielectric film is single layer structure, and the material of the control gate dielectric film is oxygen
SiClx.
The material of the control grid electrode film is the polysilicon of heavy doping.
Form the first control gate dielectric film, the second control gate dielectric film and third control gate dielectric film and control gate electricity
The technique of pole film is depositing operation, and such as plasma activated chemical vapour deposition technique, atom layer deposition process, low pressure chemical phase is heavy
Product technique or sub-atmospheric pressure chemical vapor deposition process.
Continuing with reference Fig. 6 and Fig. 7, several discrete dielectric layers 260, phase are formed in control gate structural membrane 250
There is the first opening 261 between adjacent dielectric layer 260.
Wordline bitline regions A and source line floating gate region B are shown in Fig. 7.
The dielectric layer 260 covers the control grid structural membrane 250 of wordline bitline regions A, and exposes source line floating gate region B's
Control grid structural membrane 250.
The material of the dielectric layer 260 is silicon nitride or silicon oxynitride.
Formed dielectric layer 260 method include：Deielectric-coating (not shown) is formed in the control grid structural membrane 250；
Patterned second mask layer is formed on the deielectric-coating, the second mask layer covers the deielectric-coating of wordline bitline regions A and exposure
The deielectric-coating of source line floating gate region B out；The deielectric-coating of source line floating gate region B is removed using the second mask layer as mask etching, forms medium
Layer 260；Then the second mask layer is removed.
It is schematic diagram on the basis of Fig. 7 with reference to Fig. 8, Fig. 8, forms the first side wall 270 in the first 261 side walls of opening.
The material of first side wall 270 is silica or silicon oxynitride.
The method for forming first side wall 270 includes：In the side wall of first opening 261 and bottom and medium
The top surface of layer 260 forms the first side wall film (not shown)；Remove 260 top surface of dielectric layer and the first 261 bottoms of opening
The first side wall film in portion forms the first side wall 270.
The technique for forming the first side wall film is depositing operation, such as plasma activated chemical vapour deposition technique, low pressure
Learn gas-phase deposition, sub-atmospheric pressure chemical vapor deposition process or atom layer deposition process.
The technique of removal 260 top surface of dielectric layer and the first side wall film of the first 261 bottoms of opening is to be etched back to work
Skill.Specifically, the technique of removal 260 top surface of dielectric layer and the first side wall film of the first 261 bottoms of opening can be for certainly
Etched in alignment technique.
With reference to Fig. 9, for the control grid structural membrane 250 of 261 bottoms of the first opening of exposure mask removal and floated with the first side wall 270
Gate structure film 211 forms the second opening 262 in the first 261 bottoms of opening.
It is exposure mask with the first side wall 270, the control grid structural membrane 250 and floating gate knot of 261 bottoms of the first opening of etching
Structure film 211 is until expose the surface of semiconductor substrate 200, in first the second opening 262 of 261 bottoms of opening formation.
With reference to Figure 10, source region 280 is formed in the semiconductor substrate 200 of the second 262 bottoms of opening.
There is source ion in the source region.
When the type of the flash memory is N-type, the conduction type of source ion is N-type in the source region 280；Work as institute
When the type for stating flash memory is p-type, the conduction type of source ion is p-type in the source region 280.
Formed source region 280 method include：It is exposure mask with first side wall 270, to partly leading for the second 262 bottoms of opening
Body substrate 200 carries out source ion injection, forms source dopant region；Then source annealing is carried out to the source dopant region, forms source
Area 280.
The source annealing repairs semiconductor caused by source ion injects for activating the source ion in source dopant region
Lattice damage in substrate 200.
After forming source region 280, the peak concentration position of the source ion in source region 280 is located near 280 surface of source region.
With reference to Figure 11, after forming source region 280, the second side wall 271 is formed in the second 262 side walls of opening.
The material of second side wall 271 is silica or silicon oxynitride.
The method for forming the second side wall 271 includes：It is open on dielectric layer 260 and 270 surface of the first side wall and second
Second side wall film (not shown) is formed on 262 side walls and bottom；Etching removes the second of dielectric layer 260 and 270 surface of the first side wall
Side wall film forms the second side wall 271.
In the present embodiment, second side wall 271 is different from the material of first side wall 270, reduces removal dielectric layer
260 and 270 surface of the first side wall the second side wall film during to the first side wall 270 etch be lost.
In the present embodiment, it is initially formed source region 280, rear to form the second side wall 271, advantage is：So that source region 280 is vertical
Larger in the size in the second 262 sidewall directions of opening, the capacitor that source region 280 and subsequent floating gate structure are constituted increases, therefore
Voltage on subsequent source line layer can be more coupled in floating gate structure, to be mentioned in programming process in flash memory
Voltage in high floating gate structure, is conducive to Split-gate flash memory and is programmed.
It should be noted that etching can be caused to damage to the source region 280 exposed during forming the second side wall 271
Consumption is easy to remove in the corresponding region of the peak concentration of the source ion in source region 280, source region 280 and subsequent source line layer is caused to connect
The concentration of source ion is lower than the peak concentration in the region of touching, thus leads to the contact resistance of subsequent source line layer and source region 280
It is larger.And then it is smaller to will lead to the subsequent electric current read during flash memory is in erasing operation.And flash memory
Judged whether erasing failure according to the size of the electric current of the reading.If the electric current of the reading is too small, it is judged as quick flashing
Memory erasing failure.Therefore, in the present embodiment, after forming the second side wall 271, the subsequent doping compensation ion in source region 280.
With reference to Figure 12, after forming the second side wall 271, the doping compensation ion in source region 280, the conduction of the counterion
Type is identical with the conduction type of source ion.
The technique of doping compensation ion is ion implantation technology in source region 280.
Specifically, being exposure mask with dielectric layer 260, the first side wall 270 and the second side wall 271, existed using ion implantation technology
Injecting compensating ion in source region 280, thus the doping compensation ion in source region 280.
The doping compensation ion in source region 280 forms compensating basin, the surface of the compensating basin and source region in source region 280
280 surface flushes.
When the conduction type of the source ion in the source region 280 is p-type, the conduction type of the counterion is p-type.
When the conduction type of the source ion in the source region 280 is N-type, the conduction type of the counterion is N-type.
If the energy of the ion implanting is excessively high, cause the depth of counterion injection source region 280 excessive, counterion is dense
The distance for spending highest zone to 280 surface of source region is excessive, correspondingly, concentration of the counterion in 280 near-surface region of source region
It is too small.Therefore the contact resistance of source region 280 and the source line layer being subsequently formed cannot be effectively reduced.If the energy of the ion implanting
It measures too low, effectively counterion cannot be injected into source region 280.And the different corresponding atomic masses of counterion is not
Together.In the case where identical injection depth, the energy that the biggish counterion of atomic mass needs to be lost is larger, thus need compared with
Big Implantation Energy.
If the implantation dosage of the ion implantation technology is excessively high, process costs is caused to increase；If the ion implantation technology
Implantation dosage it is too low, cause concentration of the ion implanting post-compensation ion in source region 280 too small, therefore cannot effectively reduce
The contact resistance of source region 280 and the source line layer being subsequently formed.Counterion lesser for atomic mass, atomic mass is smaller,
Divergence loss of the counterion in ion implantation process is bigger.Therefore need to make up different counterions in ion implantation process
In corresponding divergence loss.Counterion so lesser for atomic mass, atomic mass is smaller, the implantation dosage phase needed
To bigger.
The implant angle of the ion implantation technology is related with Implantation Energy, and the implant angle is and semiconductor substrate
Angle between 100 surfaces.In the case where certain injection depth, Implantation Energy is bigger, and the implant angle needed is smaller.
To sum up, the Implantation Energy, implantation dosage and implant angle of the ion implantation technology need to select suitable range.
And the different corresponding atomic masses of modified ion is different.In the case where identical injection depth, atomic mass is biggish to be changed
Property ion need the energy that is lost larger, therefore need biggish Implantation Energy.
When the counterion is boron ion, the parameter of the ion implantation technology includes：The ion used for boron from
Son, Implantation Energy are 2KeV~4KeV, implantation dosage 1E15atom/cm2~1E16atom/cm2, implant angle be 70 degree~
90 degree.
When the counterion is indium ion, the parameter of the ion implantation technology includes：Implantation Energy be 5KeV~
20KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
When the counterion is phosphonium ion, the parameter of the ion implantation technology includes：Implantation Energy be 2KeV~
5KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
When the counterion is arsenic ion, the parameter of the ion implantation technology includes：Implantation Energy be 3KeV~
15KeV, implantation dosage 1E14atom/cm2~1E15atom/cm2, implant angle is 70 degree~90 degree.
It after carrying out the ion implanting, is made annealing treatment, to activate the counterion, and repairs ion implanting and cause
Source region 280 lattice damage.
With reference to Figure 13, in source region 280 after doping compensation ion, in the first opening 261 (referring to Figure 12) and the second opening
Formation source line layer 290 in 262 (referring to Figure 12).
The material of the source line layer 290 is polysilicon.
The method of formation source line layer 290 includes：First opening 261 and second opening 262 in and 270 and of the first side wall
Source line film (not shown) is formed on dielectric layer 260；Removal is higher than the source line film of 260 top surface of dielectric layer, in the first opening 261
Source line layer 290 is formed in the second opening 262.
The technique of formed source line film is depositing operation, such as plasma activated chemical vapour deposition technique, low pressure chemical phase
Depositing operation or sub-atmospheric pressure chemical vapor deposition process.
The technique that removal is higher than the source line film of 260 top surface of dielectric layer is flatening process, such as chemical mechanical grinding work
Skill.
With reference to Figure 14, after forming source line layer 291, the dielectric layer 260 (referring to Figure 13) and control gate of wordline bitline regions A are removed
Pole structural membrane 250 (refers to Figure 13), forms control gate structure 251 in 270 bottom of the first side wall.
Remove wordline bitline regions A dielectric layer 260 and control grid structural membrane 250 technique be wet-etching technology or
Dry etch process.
In the present embodiment, the dielectric layer 260 of removal wordline bitline regions A is wet-etching technology, removal control gate structure
The technique of film 250 is dry etch process.
The control gate structure 251 includes control gate dielectric layer and the control grid electrode on control gate dielectric layer
Layer.The control gate dielectric layer corresponds to the control gate dielectric film, and the control gate electrode layer corresponds to the control grid electrode film.
In the present embodiment, the control gate dielectric layer is laminated construction, and the control gate dielectric layer includes the first control gate
Dielectric layer controls gate dielectric layer and the third on the second control gate dielectric layer positioned at the second of first grid dielectric layer surface
Control gate dielectric layer.The corresponding first control gate dielectric film of first control gate dielectric layer, the second control gate dielectric layer pair
The second control gate dielectric film is answered, the third control gate dielectric layer corresponds to third control gate dielectric film.
In other embodiments, when the control gate dielectric film is single layer structure, the control gate dielectric layer is single layer
Structure.
With reference to Figure 15, third side wall is formed in the control gate structure 251 and 270 side wall of the first side wall.
In the present embodiment, the third side wall includes inside wall 301 and external wall 302, and inside wall 301 is located at external wall
Between 302 and control gate structure 251 and between external wall 302 and the first side wall 270.
In the present embodiment, the forming method for forming third side wall includes：In floating gate structural membrane 211, the first side wall, control
The surface of gate structure 251 and source line layer 290 forms the first side wall film (not shown)；It is etched back to the first side wall film, shape
At third side wall.
Specifically, in floating gate structural membrane 211, the surface of the first side wall, control gate structure 251 and source line layer 290
Form inside wall film；External wall film is formed in inside wall film surface, external wall film and inside wall film constitute the first side wall film.
The corresponding inside wall film of the inside wall 301, the corresponding external wall film of the external wall 302.
The inside wall 301 is L-shaped, and the external wall 302 is located at " L " the type surface of inside wall 301.
The material of the inside wall 301 is silica, and the material of the external wall 302 is silicon nitride.
In other embodiments, the third side wall is single layer structure, and the material of the third side wall is silica or nitrogen
Silica.
Due to foring third side wall, so that the floating gate structure being subsequently formed is perpendicular to floating gate structure side wall
Size on direction is greater than control gate structure 251 perpendicular to the size in control 251 sidewall direction of gate structure.Secondly,
So that the isolation performance enhancing between control gate structure 251 and the word line structure being subsequently formed.
It should be noted that in the present embodiment, third side wall includes inside wall 301 and external wall 302, inside wall 301
Material is silica, and the material of the external wall 302 is silicon nitride.It can be improved control gate structure 251 and be subsequently formed
Isolation performance between word line structure, and avoid third side wall excessive to the stress of control gate structure 251, to avoid described
The excessive lattice defect for causing to control gate structure 251 of stress.
With reference to Figure 16, using first side wall 270, source line layer 290 and third side wall as exposure mask, wordline bitline regions A is removed
Part floating gate structural membrane 211, control gate structure 251 and third side wall bottom formed floating gate structure 212.
The floating gate structure 212 includes floating gate dielectric layer and the floating gate on floating gate dielectric layer.The floating gate dielectric
The corresponding floating gate oxide film of layer, the floating gate correspond to the floating gate film.
The floating gate structure 212 is located on the part semiconductor substrate 200 of source line floating gate region B.
The technique for removing the floating gate structural membrane 211 of wordline bitline regions A is wet-etching technology or dry etch process.
In the present embodiment, the floating gate structure 212 is greater than perpendicular to the size in 212 sidewall direction of floating gate structure
Gate structure 251 is controlled perpendicular to the size in control 251 sidewall direction of gate structure, advantage is：It is compiled in flash memory
There is more electronics deposit floating gate structure 212 when journey, improves the programming efficiency of flash memory.
Then, with reference to Figure 17, word line structure is formed in the third side wall side wall and 212 side wall of floating gate structure exposed.
The word line structure is located in the semiconductor substrate 200 of part wordline bitline regions A.
The word line structure includes wordline oxide layer 303 and wordline 304, and the wordline 304 is located at the side wall of third side wall；
The wordline oxide layer 303 between third side wall and wordline 304, between floating gate structure 212 and wordline 304, Yi Jiban
Between conductor substrate 200 and wordline 304.
The material of the wordline oxide layer 303 is silica.
The material of the wordline 304 is polysilicon.
The method for forming wordline oxide layer 303 and wordline 304 includes：In the semiconductor substrate 200 of the wordline bitline regions A
The third side wall side wall and 212 side wall of floating gate structure and source line layer 290 and the first side that surface, wordline bitline regions A expose
Wordline oxidation film (not shown) is formed on wall 270；Wordline film is formed on the wordline oxidation film；It is etched back to wordline film and wordline
Oxidation film forms wordline oxide layer 300 and wordline 304.
The corresponding wordline oxidation film of the wordline oxide layer 303, the corresponding wordline film of the wordline 304.
Between the wordline 304 and source line layer 290 by wordline oxide layer 300, third side wall and the first side wall 270 every
From.
Then, wordline side wall 305 is formed in the side wall of the wordline 304；It is with the wordline side wall 305 and word line structure
Exposure mask carries out leakage ion implanting to the semiconductor substrate 200 of 305 side of wordline side wall, the semiconductor in 305 side of wordline side wall
Leakage doped region is formed in substrate 200；Then leakage annealing is carried out to the leakage doped region, forms drain region 281.
The drain region 281 is between adjacent word line structure.The drain region 281 is for being electrically connected bit line.
It should be noted that in other embodiments, not forming third side wall.Correspondingly, after forming source line layer, removal
Dielectric layer, control grid structural membrane and the floating gate structural membrane of wordline bitline regions, form the control gate for being located at the first side wall bottom
Pole structure and positioned at control grid structural base floating gate structure.In the case, floating gate structure is perpendicular to floating gate
Size on the structure side wall direction of pole is equal to control gate structure perpendicular to the size on control gate structure sidewall direction.So
Afterwards, word line structure is formed in the side wall of the first side wall, control gate structure and the floating gate structure that expose；In word line structure side
Wall forms wordline side wall；Drain region is formed in the semiconductor substrate of wordline side wall side.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of flash memory, which is characterized in that including：
Semiconductor substrate is provided, there is floating gate structural membrane and the control in floating gate structural membrane in the semiconductor substrate
Grid structure film；
Several discrete dielectric layers are formed in control gate structural membrane, and there is the first opening between adjacent dielectric；
The first side wall is formed in the first opening sidewalls；
The control grid structural membrane and floating gate structural membrane that the first open bottom is removed using the first side wall as exposure mask, in the first opening
Second opening is formed on bottom；
Source region is formed in the semiconductor substrate of the second open bottom, and there is source ion in source region；
After forming source region, the second side wall, during forming the second side wall, the source region that exposes are formed in the second opening sidewalls
Be etched loss；
After forming the second side wall, the doping compensation ion in source region, the conduction type of the counterion and the conduction of source ion
Type is identical, and the counterion is suited to compensate for loss of the source ion in the second side wall forming process in source region；
In source region after doping compensation ion, line layer in source is formed in the first opening and the second opening.
2. the forming method of flash memory according to claim 1, which is characterized in that the doping compensation in the source region
The technique of ion is ion implantation technology.
3. the forming method of flash memory according to claim 2, which is characterized in that when the conductive-type of the source ion
When type is p-type, the conduction type of the counterion is p-type.
4. the forming method of flash memory according to claim 3, which is characterized in that the ginseng of the ion implantation technology
Number includes：For the ion used for boron ion, Implantation Energy is 2KeV~4KeV, implantation dosage 1E15atom/cm2~
1E16atom/cm2, implant angle is 70 degree~90 degree.
5. the forming method of flash memory according to claim 3, which is characterized in that the ginseng of the ion implantation technology
Number includes：For the ion used for indium ion, Implantation Energy is 5KeV~20KeV, implantation dosage 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree~90 degree.
6. the forming method of flash memory according to claim 2, which is characterized in that when the conductive-type of the source ion
When type is N-type, the conduction type of the counterion is N-type.
7. the forming method of flash memory according to claim 6, which is characterized in that the ginseng of the ion implantation technology
Number includes：For the ion used for phosphonium ion, Implantation Energy is 2KeV~5KeV, implantation dosage 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree~90 degree.
8. the forming method of flash memory according to claim 6, which is characterized in that the ginseng of the ion implantation technology
Number includes：For the ion used for arsenic ion, Implantation Energy is 3KeV~15KeV, implantation dosage 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree~90 degree.
9. the forming method of flash memory according to claim 1, which is characterized in that the semiconductor substrate has word
Line bitline regions and source line floating gate region, source line floating gate region is between adjacent word line bitline regions；Floating gate structural membrane position
Also extend in the floating gate structural membrane in the semiconductor substrate of part source line floating gate region, and in the semiconductor substrate of source line floating gate region
On to wordline bitline regions semiconductor substrate；The control grid structural membrane is located at semiconductor substrate and floating gate structural membrane
On；The control grid structural membrane of dielectric layer covering wordline bitline regions.
10. the forming method of flash memory according to claim 9, which is characterized in that after forming the source line layer, also
Including：The dielectric layer and control grid structural membrane for removing wordline bitline regions form control gate structure in the first side wall bottom；?
The control gate structure and the first side wall side wall form third side wall；It is with first side wall, source line layer and third side wall
Exposure mask removes the part floating gate structural membrane of wordline bitline regions, forms floating gate in the bottom of control gate structure and third side wall
Pole structure；Word line structure is formed in the third side wall side wall and floating gate structure side wall exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610828320.5A CN106298790B (en) | 2016-09-18 | 2016-09-18 | The forming method of flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610828320.5A CN106298790B (en) | 2016-09-18 | 2016-09-18 | The forming method of flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298790A CN106298790A (en) | 2017-01-04 |
| CN106298790B true CN106298790B (en) | 2018-11-27 |
Family
ID=57712334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610828320.5A Active CN106298790B (en) | 2016-09-18 | 2016-09-18 | The forming method of flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298790B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109872994B (en) * | 2019-03-07 | 2021-09-03 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN111653568B (en) * | 2020-06-01 | 2023-02-03 | 中国科学院微电子研究所 | A kind of semiconductor structure and its manufacturing method, DRAM and semiconductor chip |
| CN111739892A (en) * | 2020-07-30 | 2020-10-02 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN112242398B (en) * | 2020-11-12 | 2023-10-13 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing memory |
| CN114743980B (en) * | 2022-04-19 | 2025-03-25 | 上海华虹宏力半导体制造有限公司 | Memory structure and method of forming the same |
| CN115360196A (en) * | 2022-08-30 | 2022-11-18 | 上海华虹宏力半导体制造有限公司 | Flash memory and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196831A (en) * | 1995-09-19 | 1998-10-21 | 西门子公司 | Process for generating source regions of flast-EEPROM storage cell field |
| CN1378272A (en) * | 1999-12-04 | 2002-11-06 | 华邦电子股份有限公司 | Manufacturing method of flash reference memory cell |
| CN101625976A (en) * | 2008-07-08 | 2010-01-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102368479A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN102800679A (en) * | 2012-08-22 | 2012-11-28 | 上海宏力半导体制造有限公司 | Formation method for memory cell of flash memory |
-
2016
- 2016-09-18 CN CN201610828320.5A patent/CN106298790B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196831A (en) * | 1995-09-19 | 1998-10-21 | 西门子公司 | Process for generating source regions of flast-EEPROM storage cell field |
| CN1378272A (en) * | 1999-12-04 | 2002-11-06 | 华邦电子股份有限公司 | Manufacturing method of flash reference memory cell |
| CN101625976A (en) * | 2008-07-08 | 2010-01-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102368479A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN102800679A (en) * | 2012-08-22 | 2012-11-28 | 上海宏力半导体制造有限公司 | Formation method for memory cell of flash memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN109712981B (en) * | 2019-01-02 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298790A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106298790B (en) | The forming method of flash memory | |
| US8890232B2 (en) | Methods and apparatus for non-volatile memory cells with increased programming efficiency | |
| CN103426826B (en) | Flash cell and forming method thereof | |
| CN106129008B (en) | The forming method of flash memory | |
| CN105826273A (en) | Flash memory device and manufacturing method thereof | |
| CN109742076B (en) | Flash memory and forming method thereof | |
| CN104425366A (en) | Forming method of semiconductor structure | |
| TWI536504B (en) | Non-volatile memory unit, non-volatile memory unit manufacturing method and non-volatile memory matrix | |
| CN111524894A (en) | Memory structure and method of making the same | |
| US10153349B2 (en) | Methods and structures for a split gate memory cell structure | |
| CN104617048A (en) | Flash memory and forming method thereof | |
| US20150179821A1 (en) | Selective gate oxide properties adjustment using fluorine | |
| CN102738209B (en) | Semiconductor element and its manufacturing method | |
| CN114334986A (en) | Semiconductor structure and forming method thereof | |
| CN106783865B (en) | A kind of production method of storage unit | |
| CN105428319A (en) | Manufacturing method of flash memory structure | |
| CN105140301A (en) | Floating gate type flash memory structure and fabrication method thereof | |
| CN109216372B (en) | Method for forming semiconductor structure | |
| CN111048513B (en) | How to make floating gate flash memory | |
| CN114927528A (en) | Memory structure and forming method thereof | |
| CN103178018A (en) | Method for manufacturing separation gate quick-flashing memory unit | |
| CN111799269B (en) | Flash memory and method for manufacturing the same | |
| KR20130044699A (en) | Semiconductor memory device and method of manufacturing the same | |
| CN105990092B (en) | The forming method of semiconductor structure | |
| CN104766825B (en) | A kind of method and flash devices of increase flash device gate capacitance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |