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CN106298742B - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN106298742B
CN106298742B CN201610858225.XA CN201610858225A CN106298742B CN 106298742 B CN106298742 B CN 106298742B CN 201610858225 A CN201610858225 A CN 201610858225A CN 106298742 B CN106298742 B CN 106298742B
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China
Prior art keywords
chip
semiconductor package
heat dissipation
substrate
packaging body
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Application number
CN201610858225.XA
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Chinese (zh)
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CN106298742A (en
Inventor
沈家贤
刘盈男
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201610858225.XA priority Critical patent/CN106298742B/en
Publication of CN106298742A publication Critical patent/CN106298742A/en
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Publication of CN106298742B publication Critical patent/CN106298742B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A semiconductor package and a method of manufacturing the same. The semiconductor package comprises a chip, a package body, a conductive member and a shielding film. The chip is arranged on the conductive piece and is provided with a heat dissipation piece penetrating through the chip. The package body covers the chip and the conductive member, and has an outer side surface, an upper surface and a lower surface opposite to the outer side surface, and includes a first heat dissipation hole and a second heat dissipation hole. The first heat dissipation hole extends from the heat dissipation member to the upper surface of the package body, and the second heat dissipation hole extends from the upper surface of the package body to a region outside the heat dissipation member on the chip. The shielding films are formed on the upper surface and the outer side surface of the packaging body and are electrically connected with the conductive piece.

Description

Semiconductor package assembly and a manufacturing method thereof
The application is to apply on December 28th, 2012, entitled " partly to lead application No. is " 201210583616.7 " The divisional application of the Chinese invention patent application of body packaging part and its manufacturing method "
Technical field
The invention relates to a kind of semiconductor package assembly and a manufacturing method thereof, and have heat dissipation in particular to one kind The semiconductor package assembly and a manufacturing method thereof in hole.
Background technique
Conventional semiconductor package part includes packaging body and chip, wherein packaging body coats chip, and chip provides semiconductor The function of packaging part.However, chip can generate high fever, and the heat conductivity of packaging body is usually bad, leads to chip ambient temperature It is excessively high and influence its working efficiency.Therefore, the heat for how dispersing chip becomes industry and makes great efforts one of emphasis.
Summary of the invention
The present invention is about a kind of semiconductor package assembly and a manufacturing method thereof, and in an embodiment, semiconductor package part has Heat release hole can disperse the heat of its chip.
According to the present invention it is proposed that a kind of semiconductor package part.Semiconductor package part is led including a chip, a packaging body, one Electric part and a screened film.Chip is set on the conduct piece and has a radiating piece through chip.It packaging body coats chip and leads Electric part, and there is a lateral surface and an opposite upper surface and a lower surface and radiate including one first heat release hole and one second Hole.First heat release hole extends to the upper surface of the packaging body from radiating piece, and the second heat release hole extends from the upper surface of packaging body A region on to chip other than radiating piece.Screened film is formed in the upper surface of packaging body and lateral surface and is electrically connected conduction Part.
According to the present invention it is proposed that a kind of semiconductor package part.Semiconductor package part includes a substrate, a chip, an encapsulation Body and a screened film.Substrate includes an earthing member.Chip is formed on substrate and is electrically connected substrate, and chip has a radiating piece Through the chip.Packaging body coats chip and there is a lateral surface and an opposite upper surface and a lower surface and including one first Heat release hole and one second heat release hole.First heat release hole extends to the upper surface of packaging body from radiating piece, and the second heat release hole is from encapsulation The upper surface of body extends to the region on chip other than radiating piece.Upper surface that screened film is formed in packaging body and lateral surface are simultaneously It is electrically connected the earthing member of substrate.
For above content of the invention can be clearer and more comprehensible, special embodiment below, and cooperate attached drawing, it elaborates It is as follows:
Detailed description of the invention
Figure 1A is painted the cross-sectional view of the semiconductor package part according to one embodiment of the invention.
Figure 1B is painted the top view of Figure 1A.
Fig. 2 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 B is painted the top view of Fig. 4 A.
Fig. 5 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 B is painted the top view of Fig. 5 A.
Fig. 6 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 8 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 9 A to 9G is painted the process drawing of the semiconductor package part of Figure 1A.
Figure 10 A to 10C is painted the process drawing of the semiconductor package part of Fig. 2.
Figure 11 A to 11G is painted the process drawing of the semiconductor package part of Fig. 3.
Figure 12 A to 12F is painted the process drawing of the semiconductor package part of Fig. 4 A.
Figure 13 A to 13C is painted the process drawing of the semiconductor package part of Fig. 5 A.
Figure 14 A to 14B is painted the process drawing of the semiconductor package part of Fig. 8.
Main element symbol description:
100,200,300,400,500,600,700,800: semiconductor package part
110: chip
110a: active surface
110b: the back side
111,471: radiating piece
120: packaging body
120s, 120s1,120s2,130s, 140s, 360s, 470s, 472s: lateral surface
120u, 130u, 470u: upper surface
120b, 140b, 470b: lower surface
121: heat release hole
1211: perforation
1212: thermal conducting material
130: conduct piece
140: screened film
150: soldered ball
151: signal solder balls
152: ground connection soldered ball
153: heat dissipation soldered ball
360: conduction rack
470: substrate
472: earthing member
480: bonding wire
170: temporary substrate
P, P1, P2: Cutting Road
Specific embodiment
Figure 1A is please referred to, the cross-sectional view of the semiconductor package part according to one embodiment of the invention is painted.Semiconductor packages Part 100 includes chip 110, packaging body 120, conduct piece 130, screened film 140 and soldered ball 150.
Chip 110 has opposite active surface 110a and back side 110b, and chip 110 is set in orientation downward with its active surface 110a In on conduct piece 130, and it directly or indirectly is contacted with conduct piece 130, uses and soldered ball 150 is electrically connected at by conduct piece 130.
Chip 110 can be with single or multi-layer structure.Chip 110 further includes an at least radiating piece 111, wherein radiating piece 111 The back side 110b of chip 110 is extended to from the active surface 110a of chip 110, i.e. radiating piece 111 runs through chip 110.In this example, dissipate 111 heat release hole of warmware, for example, 110 Silicon Wafer of chip, and 111 silicon perforation of radiating piece (Through-Silicon Via, TSV), The right embodiment of the present invention is without being limited thereto.In another example, although figure is not painted, the radiating piece 111 of right chip 110 includes at least one horizontal To the heat dissipating layer of extension and at least always to the heat release hole of extension, wherein heat dissipating layer is connected to heat release hole, to constitute a heat dissipation road Diameter.In addition, the material of radiating piece 111 includes the good material of thermal conductivity, such as copper, aluminium, gold, silver or combinations thereof.
It 120 coating chip 110 of packaging body and is dissipated with opposite upper surface 120u and lower surface 120b and including at least one Hot hole 121, heat release hole 121 extend to the upper surface 120u of packaging body 120 from radiating piece 111.In this example, heat release hole 121 and dissipate Direction extends warmware 111 along a straight line, and collectively forms a vertical heat dissipation path, this vertical heat dissipation path is shorter or most short heat dissipation Path can rapidly conduct outside the heat H to semiconductor package part 100 of chip 110.In addition, the material of heat release hole 121 includes The good material of thermal conductivity, such as copper, aluminium, gold, silver or combinations thereof.
Packaging body 120 has more lateral surface 120s, and conduct piece 130 has lateral surface 130s, outer due to packaging body 120 Side 120s and the lateral surface 130s of conduct piece 130 are formed in same Cutting Road, keep lateral surface 120s and conduct piece 130s real It is aligned in matter, e.g. coplanar, cutting method so is known as " wear entirely and cut (full-cut) ".
Packaging body 120 may include phenolic group resin (Novolac-based resin), epoxy (epoxy-based Resin), silicone (silicone-based resin) or other coverings appropriate.Packaging body 120 also may include appropriate Filler, the e.g. silica of powdery.Packaging body, e.g. compression forming are formed using several encapsulation technologies (compression molding), injection moulding (injection molding) or metaideophone form (transfer molding)。
Conduct piece 130 is, for example, connection pad (pad) or conductive sheet (conductive sheet), is formed in chip 110 The lower surface 120b of active surface 110a and packaging body 120.In addition element that conductive sheet is formed with sheet metal engineering method.Electricity can be used in connection pad Electroplating method or suitable method are formed, and thickness can be thinner than conductive sheet.Screened film 140 is formed in the lateral surface of conduct piece 130 130s, to be electrically connected at conduct piece 130.In addition, conduct piece 130 has lower surface 130b, screened film 140 has lower surface 140b, wherein the lower surface 140b substantial alignment of the lower surface 130b of conduct piece 130 and screened film 140, e.g. coplanar.
Screened film 140 is formed in the upper surface 120u and lateral surface 120s of packaging body 120.In this example, screened film 140 is conformal Screened film (conformal shielding), that is, its entire upper surface 120u and entire lateral surface for covering packaging body 120 120s completely to coat packaging body 120, and provides electromagnetic interference shielding action；The right embodiment of the present invention is without being limited thereto, screened film 140 can also cover the portion of upper surface 120u and/or portions of lateral side 120s of packaging body 120.
Screened film 140 also provides a big heat dissipation area in addition to providing electromagnetic interference shielding action.When the heat of chip 110 Conduction to after screened film 140, can be by screened film 140 effectively convection current or conduction to semiconductor package part 100 outside.
The materials of aluminum of screened film 140, copper, chromium, tin, gold, silver, nickel, stainless steel or above-mentioned material combination made by, can Using e.g. chemical vapor deposition (Chemical Vapor Deposition, CVD), electroless plating (electroless Plating), it is electroplated, prints (printing), spraying (spraying), sputter or vacuum deposition (vacuum deposition) Etc. technologies be made.Screened film 140 can be single or multi-layer structure, for multilayered structure, 140 three-decker of screened film, Internal layer stainless steel layer, middle layer layers of copper, and outer layer stainless steel layer；Alternatively, 140 double-layer structure of screened film, internal layer layers of copper, and its Outer layer stainless steel layer.
Soldered ball 150 is formed on conduct piece 130, and semiconductor package part 100 is made to form a BGA packages；Another example In, soldered ball 150 can be omitted, semiconductor package part 100 is made to form a planar lattice array (Land Grid Array, LGA) encapsulation Part.
Several soldered balls 150 include an at least signal solder balls 151, and the master of chip 110 is electrically connected at by conduct piece 130 Dynamic face 110a, with outside the signal of pio chip 110 to semiconductor package part 100 circuit element and/or input from partly leading Signal outside body packaging part 100 is to chip 110.
Several soldered balls 150 include at least one ground connection soldered ball 152, are electrically connected at screened film 140 by conduct piece 130. Ground connection soldered ball 152 can be electrically connected the ground terminal (not being painted) of an electronic component, make screened film 140 by being grounded soldered ball 152 Ground connection.
Several soldered balls 150 include at least one heat dissipation soldered ball 153, and the heat H of chip 110 can pass through radiating piece 111 and heat dissipation Outside the conduction to semiconductor package part 100 of soldered ball 153.Via heat dissipation soldered ball 153, radiating piece 111 and heat release hole 121, chip 110 Heat H can simultaneously up and down conduct to semiconductor package part 100.In this example, radiate soldered ball 153, radiating piece 111 Extend along a straight line jointly with heat release hole 121, and constitute a vertical heat dissipation path, this vertical heat dissipation path is shorter or most short heat dissipation Path can rapidly conduct the heat H of chip 110 while up and down to outside semiconductor package part 100.
Figure 1B is please referred to, the top view of Figure 1A is painted.The quantity of heat release hole 121 is multiple, can be arranged in n × m array, Wherein n and m is identical or different positive integer；In another example, the quantity of heat release hole 121 be can be individually；However, the present invention is real Apply the quantity that example is not intended to limit heat release hole 121.As shown in Figure 1B, conduct piece 130 is, for example, cabling, can be along curve and/or straight Line direction extends, and may extend to the active surface 110a for overlapping and (overlapping as upper and lower) and be electrically connected at chip 110 with chip 110 (Figure 1A).
Referring to figure 2., it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages Part 200 includes chip 110, packaging body 120, conduct piece 130, screened film 140 and soldered ball 150 (selectivity).
Packaging body 120 has lateral surface 120s, and conduct piece 130 has upper surface 130u, and screened film 140 is formed in encapsulation The lateral surface 120s of the body 120 and upper surface 130u of conduct piece 130.Conduct piece 130 has more lateral surface 130s, packaging body 120 Lateral surface 120s formed from the lateral surface 130s of conduct piece 130 respectively at two different cutting techniques, make the outside of packaging body 120 The lateral surface 130s indent of face 120s opposed conductive elements 130 and form a lateral segment difference structure, cutting method so is known as " half It wears and cuts (half-cut) ".In addition, screened film 140 has more lateral surface 140s, lateral surface 140s due to screened film 140 with lead The lateral surface 130s of electric part 130 is formed in same Cutting Road, makes lateral surface 140s and conduct piece 130s substantial alignment, such as It is coplanar.
Referring to figure 3., it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages Part 300 includes chip 110, packaging body 120, conduct piece 130, screened film 140, soldered ball 150 (selectivity) and conduction rack 360.
In this example, packaging body 120 has the first lateral surface 120s1 and the second lateral surface 120s2, the first lateral surface 120s1 And second lateral surface 120s2 formed respectively at two different cutting techniques, make the first lateral surface 120s1 with respect to the second lateral surface 120s2 indent and form a lateral segment difference structure, cutting method so claims " partly wear and cut ".Specifically, conduction rack 360 has Lateral surface 360s, the first lateral surface 120s1 of packaging body 120 and the lateral surface 360s of conduction rack 360 are in same ㄧ cutting technique shape At, make lateral surface 360s and the first lateral surface 120s1 substantial alignment, it is e.g. coplanar.In addition, screened film 140 has outside Face 140s, and conduct piece 130 have lateral surface 130s, due to the lateral surface 140s of screened film 140, packaging body 120 second outside Side 120s2 and the lateral surface 130s of conduct piece 130 are formed in another cutting technique, make lateral surface 140s, the second lateral surface 120s2 and lateral surface 130s substantial alignment, it is e.g. coplanar.
Conduction rack 360 is set on conduct piece 130.Screened film 140 is formed in the lateral surface 360s of conduction rack 360, and passes through Conduction rack 360 is electrically connected at conduct piece 130.Wherein a conduct piece 130 is grounded conduct piece, is grounded screened film 140 by this Conduct piece ground connection, to dredge an electromagnetic interference to ground terminal
A referring to figure 4. is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package Piece installing 400 includes chip 110, packaging body 120, screened film 140, soldered ball 150 (selectivity), substrate 470 and an at least bonding wire 480。
Chip 110 is formed on substrate 470.With its active surface 110a, orientation is set on substrate 470 chip 110 upward, and Substrate 470 is electrically connected at by bonding wire 480.
Substrate 470 can be single or multi-layer structure.Substrate 470 has opposite upper surface 470u and lower surface 470b, And including an at least radiating piece 471, wherein radiating piece 471 extends to upper surface 470u from upper surface 470u.The heat dissipation of chip 110 Part 111 exposes its back side 110b with the radiating piece 471 of connecting substrate 470, and extends to the active surface 110a of chip 110.Chip 110 heat can pass through the radiating piece 471 of substrate 470, the radiating piece 111 of chip 110, heat dissipation soldered ball 153 and packaging body 120 Heat release hole 121 is conducted to the outside of semiconductor package part 400.In this example, the radiating piece 471 of substrate 470, dissipates heat dissipation soldered ball 153 The common direction along a straight line of warmware 111 and heat release hole 121 extends, and constitutes a vertical heat dissipation path, this vertical heat dissipation path compared with Short or most short heat dissipation path, can rapidly conduct outside the heat H to semiconductor package part 400 of chip 110.In another example, though So figure is not painted, and the radiating piece 471 of right substrate 470 is including at least one heat dissipating layer being laterally extended and at least always to the scattered of extension Hot hole, wherein heat dissipating layer is connected to heat release hole, to constitute a heat dissipation path.
Substrate 470 further includes an at least earthing member 472, extends the upper surface 470u and lower surface 470b of substrate 470 Between, this example extends to for the 470b of lower surface from upper surface 470u to be illustrated.Although figure is not painted, right earthing member 472 can pass through The conductive layer (not being painted) of substrate 470 is electrically connected at bonding wire 480 and/or soldered ball 150, uses and is electrically connected to ground terminal.
B referring to figure 4. is painted the top view of Fig. 4 A.The quantity of earthing member 472 is multiple, surrounds chip 110, and mentions Function of shielding is disturbed for 110 electromagnetism sense of chip.In addition, substrate 470 has lateral surface 470s, and packaging body 120 has lateral surface 120s keeps lateral surface 470s and lateral surface 120s real since lateral surface 470s and lateral surface 120s is formed in same Cutting Road It is aligned in matter, e.g. coplanar, cutting method so is known as " wear and cut entirely ".
A referring to figure 5. is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package Piece installing 500 includes chip 110, packaging body 120, screened film 140, soldered ball 150 (selectivity), substrate 470 and an at least bonding wire 480。
Chip 110 is set on substrate 470.With its active surface 110a, orientation is set on substrate 470 chip 110 upward, and Substrate 470 is electrically connected at by bonding wire 480.
B referring to figure 5. is painted the top view of Fig. 5 A.Packaging body 120 has lateral surface 120s, and substrate 470 is with outer Side 470s keeps lateral surface 120s opposite since lateral surface 120s is formed from lateral surface 470s respectively at two different cutting techniques Lateral surface 470s indent and form a lateral segment difference structure, cutting method so is known as " partly wear and cut ".
Fig. 6 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor packages Part 600 includes chip 110, packaging body 120, screened film 140, soldered ball 150 (selectivity) and substrate 470.Compared to semiconductor package Piece installing 400, with its active surface 110a, orientation is set on substrate 470 chip 110 of this example downward, and is electrically connected with an at least soldered ball It is connected to substrate 470.
Fig. 7 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor packages Part 700 includes chip 110, packaging body 120, screened film 140, soldered ball 150 (selectivity) and substrate 470.Compared to semiconductor package The chip 110 of piece installing 600, this example omits radiating piece 111, can still conduct chip 110 by the heat release hole 121 of packaging body 120 Outside heat to semiconductor package part 700.
Fig. 8 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor packages Part 800 includes chip 110, packaging body 120, screened film 140, soldered ball 150 (selectivity) and substrate 470.In this example, packaging body 120 omit heat release hole 121.Packaging body 120 has a upper surface 120u, and the back side 110b of chip 110 is from the upper surface of packaging body 120 120u exposes, and wherein the back side 110b substantial alignment of the upper surface 120u of packaging body 120 and chip 110, e.g. coplanar.
Fig. 9 A to 9G is please referred to, the process drawing of the semiconductor package part of Figure 1A is painted.
As shown in Figure 9 A, temporary substrate 170 is provided.
As shown in Figure 9 A, an at least conduct piece 130 is formed on temporary substrate 170.In this example, 130 conductive sheet of conduct piece, E.g. surface, which can be used, in it pastes technology (SMT) and is placed on temporary substrate 170.In another example, conduct piece 130 also be can be used Plating mode is formed.
As shown in Figure 9 B, a setting at least chip 110 is on conduct piece 130, wherein chip 110 have active surface 110a and Back side 110b and including an at least radiating piece 111, wherein radiating piece 111 extends to chip 110 from the active surface 110a of chip 110 Back side 110b.With its active surface 110a, orientation is set on conduct piece 130 chip 110 downward, and the wherein contact of radiating piece 111 is led Electric part 130.
As shown in Figure 9 C, e.g. compression forming, injection moulding or metaideophone molding can be used, form packaging body 120 and coat Chip 110 and conduct piece 130, wherein packaging body 120 has opposite upper surface 120u and lower surface 120b.
As shown in fig. 9d, e.g. laser can be used, form upper surface 120u of at least perforation 1211 from packaging body 120 The back side 110b for extending to chip 110 e.g. extends to the area other than the radiating piece 111 of radiating piece 111 and/or chip 110 Domain.
As shown in fig. 9e, such as material formation technology can be used, form an at least thermal conducting material 1212 and insert perforation 1211, Wherein thermal conducting material 1212 and perforation 1211 constitute heat release hole 121.Thermal conducting material 1212 is, for example, copper, aluminium, gold, silver or its group It closes.It is, for example, chemical vapor deposition, electroless plating method (electroless plating), electrolysis electricity that material herein, which forms technology, Plate (electrolytic plating), printing, spin coating, spraying, sputter (sputtering) or vacuum deposition method (vacuum deposition)。
As shown in fig. 9f, can be used e.g. cutter or laser, formed an at least Cutting Road P by entire packaging body 120, Entire conduct piece 130 and part temporary substrate 170, to completely cut through packaging body 120 and conduct piece 130, cutting method so Claim " wear and cut entirely ".After cutting, packaging body 120 and conduct piece 130 are respectively formed lateral surface 120s and 130s, wherein lateral surface 120s And 130s substantial alignment, it is such as coplanar.
Radiating piece 111 and the common direction along a straight line of heat release hole 121 extend, and constitute a vertical heat dissipation path, this is vertical Heat dissipation path is shorter or most short heat dissipation path, can rapidly conduct outside the heat H to semiconductor package part 400 of chip 110.
As shown in fig. 9g, above-mentioned material formation technology can be used, form screened film 140 in the upper surface of packaging body 120 On 120u and lateral surface 120s, the wherein heat release hole 121 in electrical contact of screened film 140.When the heat H of chip 110 is conducted to shielding After film 140, can effectively it be radiated by the large area of screened film 140.
After forming screened film 140, temporary substrate 170 can be removed, to expose the lower surface of conduct piece 130；Then, figure is formed The soldered ball 150 and heat dissipation soldered ball 153 of 1A forms at least one semiconductor packages shown in figure 1A in the lower surface of conduct piece 130 Part 100.In another example, soldered ball 150 and heat dissipation soldered ball 153 can be in Cutting Road p-shapeds at preceding formation.In another example, can not also it be formed Soldered ball 150 is on conduct piece 130.
Figure 10 A to 10C is please referred to, the process drawing of the semiconductor package part of Fig. 2 is painted.
As shown in Figure 10 A, e.g. cutter or laser can be used, form at least one first Cutting Road P1 and pass through packaging body The 120 upper surface 130u until exposing conduct piece 130；Alternatively, the first Cutting Road P1 can pass through partially electronically conductive part 130 but not cut off Conduct piece 130.After cutting, packaging body 120 forms lateral surface 120s.
As shown in Figure 10 B, above-mentioned material formation technology can be used, form the upper surface that screened film 140 covers packaging body 120 On 120u and lateral surface 120s.In this example, screened film 140 covers the entire upper surface 120u and entire lateral surface of packaging body 120 120s, and form a conformal screened film.
As illustrated in figure 10 c, e.g. cutter or laser can be used, form at least one second Cutting Road P2 by the first cutting Road P1, screened film 140, conduct piece 130 and part temporary substrate 170, to completely cut through screened film 140 and conduct piece 130.This example Semiconductor package part 200 completed using multiple cutting techniques, cutting method so claims " partly wear and cut ".
After forming screened film 140, temporary substrate 170 can be removed, to expose the lower surface of conduct piece 130；Then, figure is formed 2 soldered ball 150 and heat dissipation soldered ball 153 forms at least one semiconductor package part shown in Fig. 2 in the lower surface of conduct piece 130 200.In another example, soldered ball 150 and heat dissipation soldered ball 153 can form preceding formation in the first Cutting Road P1 or the second Cutting Road P2.Separately In an example, soldered ball 150 and heat dissipation soldered ball 153 can not be also formed on conduct piece 130.
Figure 11 A to 11G is please referred to, the process drawing of the semiconductor package part of Fig. 3 is painted.
As shown in Figure 11 A, e.g. surface can be used and paste technology, an at least conduction rack 360 is set in conduct piece 130 On.Conduction rack 360 is across between adjacent two conduct piece 130.
As shown in Figure 11 B, e.g. compression forming, injection moulding or metaideophone molding can be used, form packaging body 120 and coat Chip 110, conduct piece 130 and conduction rack 360, wherein packaging body 120 has opposite upper surface 120u and lower surface 120b.
As shown in Figure 11 C, e.g. laser can be used, form an at least perforation 1211 from the upper surface of packaging body 120 120u extends to the back side 110b of chip 110, e.g. extends to other than the radiating piece 111 of radiating piece 111 and/or chip 110 Region.
As shown in Figure 11 D, such as above-mentioned material formation technology can be used, form an at least thermal conducting material 1212 and insert perforation 1211, wherein thermal conducting material 1212 and perforation 1211 constitute heat release hole 121.
As depicted in fig. 11E, e.g. cutter or laser can be used, form at least one first Cutting Road P1 and pass through partial encapsulation Body 120 and at least part of conduction rack 360.After cutting, packaging body 120 and conduction rack 360 are respectively formed the first lateral surface 120s1 And lateral surface 360s, wherein the first lateral surface 120s1 and lateral surface 360s substantial alignment, such as coplanar.
As shown in fig. 11f, above-mentioned material formation technology can be used, form the upper surface that screened film 140 covers packaging body 120 The lateral surface 360s of 120u, the first lateral surface 120s1 and conduction rack 360.
As shown in fig. 11g, e.g. cutter or laser can be used, form at least one second Cutting Road P2 by the first cutting Road P1, screened film 140 and part temporary substrate 170, to completely cut through packaging body 120, screened film 140 and conduct piece 130.Cutting Afterwards, packaging body 120, screened film 140 and conduct piece 130 are respectively formed the second lateral surface 120s2, lateral surface 140s and lateral surface 130s, wherein the second lateral surface 120s2, lateral surface 140s and lateral surface 130s substantial alignment, such as coplanar.The semiconductor of this example Packaging part 300 is completed using multiple cutting techniques, and cutting method so claims " partly wear and cut ".
After forming screened film 140, temporary substrate 170 can be removed, to expose the lower surface of substrate conducting part 130；Then, shape At the soldered ball 150 and heat dissipation soldered ball 153 of Fig. 3 in the lower surface of conduct piece 130, and form at least one semiconductor package shown in Fig. 3 Piece installing 300.In another example, soldered ball 150 and heat dissipation soldered ball 153 can form preceding shape in the first Cutting Road P1 or the second Cutting Road P2 At.In another example, soldered ball 150 and heat dissipation soldered ball 153 can not be also formed on conduct piece 130.
Figure 12 A to 12F is please referred to, the process drawing of the semiconductor package part of Fig. 4 A is painted.
As illustrated in fig. 12, a setting at least chip 110 is on substrate 470, wherein chip 110 have active surface 110a and Back side 110b and including an at least radiating piece 111, wherein radiating piece 111 extends to chip 110 from the active surface 110a of chip 110 Back side 110b, and contact substrate 470 radiating piece 471.With its active surface 110a, orientation is set to conduct piece to chip 110 upward On 130, and substrate 470 is electrically connected at by an at least bonding wire 480.
As shown in Figure 12 B, e.g. compression forming, injection moulding or metaideophone molding can be used, form packaging body 120 and coat Chip 110 and bonding wire 480, wherein packaging body 120 has opposite upper surface 120u and lower surface 120b.
As indicated in fig. 12 c, e.g. laser can be used, form an at least perforation 1211 from the upper surface of packaging body 120 120u extends to the active surface 110a of chip 110, e.g. extend to the radiating piece 111 of radiating piece 111 and/or chip 110 with Outer region.
As indicated in fig. 12d, e.g. above-mentioned material formation technology can be used, form an at least thermal conducting material 1212 filling and pass through Hole 1211, wherein thermal conducting material 1212 and perforation 1211 constitute heat release hole 121.
As shown in figure 12e, e.g. cutter or laser can be used, form an at least Cutting Road P and pass through packaging body 120 and base The earthing member 472 of plate 470, to completely cut through the earthing member 472 of packaging body 120 and substrate 470, cutting method so claims " complete It wears and cuts ".After cutting, the earthing member 472 of packaging body 120 and substrate 470 is respectively formed lateral surface 120s and 472s, wherein lateral surface 120s and 130s substantial alignment, it is such as coplanar.
As shown in Figure 12 F, above-mentioned material formation technology can be used, form screened film 140 in the upper surface of packaging body 120 On the lateral surface 472s of 120u, lateral surface 120s and earthing member 472.
After forming screened film 140, the soldered ball 150 of Fig. 4 A can be formed and the soldered ball 153 that radiates is in the lower surface of substrate 470, and Form semiconductor package part 400 shown at least Fig. 4 A.In another example, soldered ball 150 and heat dissipation soldered ball 153 can be in Cutting Road P It is formed before being formed.In another example, soldered ball 150 can not be also formed on substrate 470.
Figure 13 A to 13C is please referred to, the process drawing of the semiconductor package part of Fig. 5 A is painted.
As shown in FIG. 13A, e.g. cutter or laser can be used, form at least one first Cutting Road P1 and pass through packaging body 120 earthing member 472 until exposing substrate 470.After cutting, packaging body 120 forms lateral surface 120s；Alternatively, the first Cutting Road P1 can pass through entire packaging body 120 and partial earthing part 472, but not cut off earthing member 472.
As shown in Figure 13 B, above-mentioned material formation technology can be used, form the upper surface that screened film 140 covers packaging body 120 The earthing member 472 of 120u, lateral surface 120s and exposing.
As shown in fig. 13 c, e.g. cutter or laser can be used, form at least one second Cutting Road P2 by the first cutting The earthing member 472 of road P1, screened film 140 and substrate 470, to completely cut through the earthing member 472 of screened film 140 and substrate 470.Separately In an example, the second Cutting Road P2 successively passes through 140 to the first Cutting Road P1 of substrate 470 and screened film, and completely cuts through substrate 470 And screened film 140.The semiconductor package part 500 of this example is completed using multiple cutting techniques, and cutting method so claims " partly to wear It cuts ".
After forming screened film 140, the soldered ball 150 and heat dissipation soldered ball 153 that can form Fig. 5 are in the lower surface of substrate 470, and shape At at least one semiconductor package part 500 shown in fig. 5.In another example, soldered ball 150 and heat dissipation soldered ball 153 can be in the first Cutting Roads P1 or the second Cutting Road P2 form preceding formation.In another example, soldered ball 150 can not be also formed on substrate 470.
The manufacturing method of the semiconductor package part 600 of Fig. 6 is similar to Fig. 4 A, holds this and repeats no more.The semiconductor packages of Fig. 7 The manufacturing method of part 700 is similar to Fig. 4 A, holds this and repeats no more.
Figure 14 A to 14B is please referred to, the process drawing of the semiconductor package part of Fig. 8 is painted.
As shown in Figure 14 A, e.g. compression forming, injection moulding or metaideophone molding can be used, form packaging body 120 and coat Chip 110.
As shown in Figure 14B, material removal technique can be used and remove 120 some materials of packaging body, such as grind (Grinding), until the radiating piece 111 of exposed chip 110 and the upper surface 120u of packaging body 120.Remove packaging body 120 After dividing material, the back side 110b of chip 110 and the upper surface 120u substantial alignment of packaging body 120 are such as coplanar.In this example, by Package material above chip 110 is removed, therefore heat release hole 121 can not be formed on chip 110.Chip 110 passes through certainly The radiating piece 111 of body can still radiate.
Remaining step of semiconductor package part 800 is similar to the correspondence step of above-mentioned semiconductor package part 400, holds this no longer It repeats.
In summary, semiconductor package part, which can be used to wear entirely, cuts or partly wears blanking method completion cutting.For partly wearing and cut, envelope It fills body and forms the first lateral surface and the second lateral surface, wherein the first lateral surface of packaging body is with respect in the second lateral surface of packaging body It is recessed and form a lateral segment difference structure；Alternatively, packaging body and substrate respectively form a lateral surface, wherein one of packaging body and substrate Lateral surface a lateral segment difference structure is formed with respect to the lateral surface indent of another one；Alternatively, substrate formed the first lateral surface and Second lateral surface, wherein the second lateral surface indent of the first lateral surface opposing substrate of substrate and form a lateral segment difference structure. For wearing and cut entirely, the entire lateral surface substantial alignment of semiconductor package part is such as coplanar.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various change and profit can be made Decorations.Therefore, the scope of protection of the present invention is defined by those of the claims.

Claims (10)

1.一种半导体封装件，包括：1. A semiconductor package, comprising: 一导电件；a conductor; 一芯片，设置于该导电件上，且具有一散热件贯穿该芯片；a chip, disposed on the conductive member, and having a heat dissipation member penetrating the chip; 一封装体，包覆该芯片及该导电件，且具有一外侧面及相对的一上表面及一下表面且包括一第一散热孔及一第二散热孔，该第一散热孔从该散热件延伸至该封装体的该上表面，及该第二散热孔从该封装体的该上表面延伸至该芯片上该散热件以外的一区域,且不通过该芯片；以及a package body, covering the chip and the conductive member, having an outer side surface and an opposite upper surface and a lower surface, and including a first heat dissipation hole and a second heat dissipation hole, the first heat dissipation hole extending from the heat dissipation member extending to the upper surface of the package body, and the second heat dissipation hole extends from the upper surface of the package body to an area on the chip other than the heat sink, and does not pass through the chip; and 一屏蔽膜，形成于该封装体的该上表面及该外侧面并电性连接该导电件。A shielding film is formed on the upper surface and the outer side surface of the package body and is electrically connected to the conductive member. 2.如权利要求1所述的半导体封装件，更包括：2. The semiconductor package of claim 1, further comprising: 一导电架，设于该导电件上且具有一外侧面；a conductive frame, which is arranged on the conductive member and has an outer side surface; 其中，该屏蔽膜形成该导电架的该外侧面，而通过该导电架电性连接于该导电件。Wherein, the shielding film forms the outer side surface of the conductive frame, and is electrically connected to the conductive member through the conductive frame. 3.如权利要求1所述的半导体封装件，其中该导电件具有一上表面及一外侧面，该屏蔽膜具有一外侧面，该屏蔽膜更形成于该导电件的该上表面上，且该导电件的该外侧面与该屏蔽膜的该外侧面对齐。3. The semiconductor package of claim 1, wherein the conductive member has an upper surface and an outer side surface, the shielding film has an outer side surface, the shielding film is further formed on the upper surface of the conductive member, and The outer side of the conductive member is aligned with the outer side of the shielding film. 4.如权利要求1所述的半导体封装件，其中该导电件具有一外侧面，该屏蔽膜形成于该导电件的该外侧面，且该导电件的该外侧面与该封装体的该外侧面对齐。4. The semiconductor package of claim 1, wherein the conductive member has an outer side, the shielding film is formed on the outer side of the conductive member, and the outer side of the conductive member and the outer side of the package body face alignment. 5.如权利要求1所述的半导体封装件，更包括：5. The semiconductor package of claim 1, further comprising: 数个焊球，形成于该导电件上。Several solder balls are formed on the conductive member. 6.一种半导体封装件，包括：6. A semiconductor package, comprising: 一基板，包括一接地件；a base plate, including a grounding member; 一芯片，形成于该基板上且电性连接该基板，该芯片具有一散热件贯穿该芯片；a chip, formed on the substrate and electrically connected to the substrate, the chip has a heat sink penetrating the chip; 一封装体，包覆该芯片且具有一外侧面及相对的一上表面及一下表面且包括一第一散热孔及一第二散热孔，该第一散热孔从该散热件延伸至该封装体的该上表面，及该第二散热孔从该封装体的该上表面延伸至该芯片上该散热件以外的一区域,且不通过该芯片；以及a package body, covering the chip, having an outer side surface and an opposite upper surface and a lower surface, including a first heat dissipation hole and a second heat dissipation hole, the first heat dissipation hole extending from the heat sink to the package body the upper surface of the package, and the second heat dissipation hole extends from the upper surface of the package to an area on the chip other than the heat sink, and does not pass through the chip; and 一屏蔽膜，形成于该封装体的该上表面及该外侧面并电性连接基板的该接地件。A shielding film is formed on the upper surface and the outer side surface of the package body and is electrically connected to the grounding member of the substrate. 7.如权利要求6所述的半导体封装件，其中该基板具有相对的上表面与下表面，且包括至少一散热件，其中该基板的该散热件从该上表面延伸至该下表面。7. The semiconductor package of claim 6, wherein the substrate has opposite upper and lower surfaces, and comprises at least one heat sink, wherein the heat sink of the substrate extends from the upper surface to the lower surface. 8.如权利要求7所述的半导体封装件，更包括：8. The semiconductor package of claim 7, further comprising: 数个焊球，形成于该基板的该下表面。A plurality of solder balls are formed on the lower surface of the substrate. 9.如权利要求8所述的半导体封装件，其中数个焊球包含至少一散热焊球。9. The semiconductor package of claim 8, wherein the plurality of solder balls comprise at least one heat dissipation solder ball. 10.如权利要求9所述的半导体封装件，其中该基板的该至少一散热件、该至少一散热焊球、该芯片的该散热件与该封装体的该第一散热孔共同沿一直线方向延伸。10 . The semiconductor package of claim 9 , wherein the at least one heat sink, the at least one heat dissipation solder ball of the substrate, the heat sink of the chip and the first heat dissipation hole of the package are along a line together. 11 . direction extension.
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