CN106298729A - Packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a substrate, a chip and a packaging colloid. The substrate includes a core layer, a solder mask layer, and first and second patterned metal layers. The core layer includes opposing first and second surfaces. The first and second patterned metal layers are respectively disposed on the first and second surfaces. The second patterned metal layer includes a plurality of solder pads and metal pads. The welding pad has a first thickness, and the maximum thickness of the metal pad is greater than the first thickness. The solder mask covers the second surface and partially exposes the soldering pad and the metal pad. The maximum thickness of the solder mask is equal to the maximum thickness of the metal pad. The chip is disposed on the first surface and electrically connected to the first patterned metal layer. The distribution range of the metal pad on the second surface overlaps with the orthographic projection of the chip on the second surface. The packaging colloid is disposed on the first surface and covers the chip and the first patterned metal layer. The invention can effectively improve the structural reliability of the packaging structure and the yield rate of the manufacturing process.

Description

Encapsulation structure and manufacturing method thereof

technical field

The present invention relates to a packaging structure and its manufacturing method, and in particular to a chip packaging structure and its manufacturing method.

Background technique

Integrated Circuits (IC for short) are almost ubiquitous in our daily life. In order to meet the requirements of high-speed processing, multi-functionality, integration, small size and light weight of electronic devices, semiconductor process technology is also developing towards miniaturization and high density. The requirements for development and packaging are becoming more and more complex. However, with the miniaturization of the substrate and the complexity of the circuit, the existing substrate encounters many new problems in the manufacturing process. With the gradual increase in the number of signal contacts of electronic devices, the early use of pin grid array (PGA) as the signal transmission interface structure substrate is no longer enough, so the development of land grid array (Land Grid Array, referred to as LGA) As the signal transmission interface of the build substrate. The contacts used in the LGA type package structure are many pad-shaped terminals arranged in a planar array on the bottom surface of the LGA substrate.

FIG. 2 shows a schematic cross-sectional view of a conventional LGA package structure. The package structure 50 includes a substrate 500 , a solder resist layer 550 , a chip 600 and an encapsulant 700 . The substrate 500 includes a core layer 510 , a first patterned metal layer 520 and a second patterned metal layer 530 , and the first patterned metal layer 520 and the second patterned metal layer 530 are respectively disposed on upper and lower surfaces of the core layer 510 . The second metal layer 530 may include a plurality of pads 532 and metal pads 534 having a signal transmission function. The chip 600 is disposed on the upper surface of the core layer 510 and electrically connected to the first patterned metal layer 520, while the solder resist layer 550 covers the lower surface of the core layer 510 and has a plurality of openings 550a, which partially expose the second The pad 532 and the metal pad 534 of the metal layer 530 are patterned, so that the pad 532 can be used as a pad-shaped contact for electrically connecting the packaging structure 50 and external electronic components, and the metal pad 534 is located under the chip 600. On the one hand, it can The support chip 600 can be used as a heat dissipation pad on the one hand. In order to effectively dissipate the heat energy generated by the chip 600 during operation, the opening 550a of the solder resist layer 550 that partially exposes the metal pad 534 should generally be as large as possible, so that the metal pad 534 The exposed area is maximized as much as possible.

However, when the chip 600 disposed on the upper surface of the core layer 510 is subjected to wiring processing or sealing process, due to the different thicknesses of the solder resist layer 550 on the lower surface of the core layer 510 and the metal pad 534 located below the chip 600, That is, there is a height difference between the bottom surface of the solder resist layer 550 and the bottom surface of the metal pad 534, the solder resist layer 550 provides support at the bottom surface, but cannot provide support at the opening 550a where the metal pad 534 is exposed, causing the substrate 500 When subjected to the positive stress of wire bonding or sealing, the uneven support force below it will cause warpage (Warpage), and then the chip 600 will be affected by the instantaneous positive pressure and the supporting part below it (that is, the substrate). 500 ) produces warping to cause deformation, and even brittle cracking as shown in FIG. 2 , causing damage to the chip 600 and reducing the reliability of the existing packaging structure 50 .

Contents of the invention

The invention provides a packaging structure and a manufacturing method thereof, which can improve the structural reliability and process yield of the packaging structure.

The packaging structure of the present invention includes a substrate, a chip and packaging colloid. The substrate includes a core layer, a first patterned metal layer, a second patterned metal layer and a solder resist layer. The core layer includes a first surface and a second surface opposite to the first surface. The first patterned metal layer is disposed on the first surface. The second patterned metal layer is disposed on the second surface. The second patterned metal layer includes a plurality of welding pads and metal pads. The pad has a first thickness, and the maximum thickness of the metal pad is greater than the first thickness. The solder resist layer covers the second surface and has a first opening and a plurality of second openings. The first openings partially expose the metal pads, and the second openings respectively partially expose the welding pads. The maximum thickness of the solder mask is equal to the maximum thickness of the metal pad. The chip is disposed on the first surface and electrically connected to the first patterned metal layer. The distribution range of the first openings at least partially overlaps with the orthographic projection of the chip on the second surface. The packaging colloid is arranged on the first surface and covers the chip and the first patterned metal layer.

The manufacturing method of the packaging structure of the present invention comprises the following steps: firstly, a substrate is provided, the substrate includes a core layer, a first metal layer and a second metal layer, the core layer includes opposite first surfaces and second surfaces, the first metal The first metal layer and the second metal layer are respectively disposed on the first surface and the second surface, and then, the first metal layer and the second metal layer are patterned to form a first patterned metal layer and a second patterned metal layer , the second patterned metal layer includes a plurality of welding pads and metal pads. The pad has a first thickness, and the maximum thickness of the metal pad is greater than the first thickness. Next, a solder resist layer is formed, the solder resist layer covers the second surface and has a first opening and a plurality of second openings. The first opening partially exposes the metal pad, the second opening partially exposes the welding pad respectively, the maximum thickness of the solder resist layer is equal to the maximum thickness of the metal pad, and then, the chip is placed on the first surface. The chip is electrically connected to the first patterned metal layer, and the distribution range of the first opening at least partially overlaps with the orthographic projection of the chip on the second surface. Next, an encapsulation compound is formed on the first surface, and the encapsulation compound covers the chip and the first patterned metal layer.

Based on the above, the packaging structure of the present invention and its manufacturing method form a second patterned metal layer with a plurality of solder pads and metal pads through two-stage patterning, wherein the maximum thickness of the metal pads is greater than the thickness of the solder pads, and is equivalent to The maximum thickness of the solder resist layer, so that the bottom surface of the metal pad facing away from the second surface and the lower surface of the solder resist layer facing away from the second surface are coplanar. In this way, when the wire bonding and sealing process are performed, the bottom surface of the metal pad and the lower surface of the solder resist layer are coplanar to provide uniform support when the substrate and chip are subjected to positive stress, thereby avoiding stress. Focus on the problems of substrate warping and chip cracking caused by the edge of the metal pad (ie, the boundary of the first opening). Therefore, the present invention can indeed effectively improve the structural reliability of the packaging structure and the yield rate of the manufacturing process.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1F are schematic cross-sectional flow diagrams of a manufacturing method of a packaging structure according to an embodiment of the present invention;

FIG. 2 shows a schematic cross-sectional view of a conventional LGA package structure.

Explanation of reference signs:

10, 50: Encapsulation structure;

100, 500: Substrate;

105: substrate;

110, 510: core layer;

112: first surface;

114: second surface;

120, 520: the first patterned metal layer;

120a: first metal layer;

130, 530: the second patterned metal layer;

130a: second metal layer;

132, 532: Welding pads;

132a: welding pad part;

134, 534: metal pad;

134a: metal pad;

134b: main body;

134c: flange portion;

134d: bottom surface;

136: opening;

140: conduction column;

150, 550: solder mask;

150a: first opening;

150b: second opening;

152: lower surface;

200, 600: chip;

300, 700: encapsulation colloid;

400: wire;

550a: opening;

T1: first thickness;

T2, T3: maximum thickness;

A1: distribution range;

P1: Orthographic projection.

detailed description

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed descriptions of the embodiments with reference to the figures. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Accordingly, the directional terms used are illustrative, not limiting, of the invention. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.

1A to 1F are schematic cross-sectional flow diagrams of a manufacturing method of a packaging structure according to an embodiment of the present invention. The manufacturing method of the packaging structure of this embodiment includes the following steps. First, a substrate 105 as shown in FIG. 1A is provided. The substrate 105 includes a core layer 110, a first metal layer 120a and a second metal layer 130a, wherein the core layer 110 includes a first surface 112 and a second surface 114 opposite to the first surface 112, the first metal layer 120a and the second metal layer 130a The two metal layers 130 a are respectively disposed on the first surface 112 and the second surface 114 . In addition, the substrate 105 also includes a plurality of vias 140, which are formed by first forming a plurality of via holes in the core layer 110, wherein the via holes can, for example, penetrate through the core layer 110 to communicate with the first metal layer 120a and the second metal layer 120a. layer 130a. Next, electroplating is performed on the through holes to form a plurality of vias 140 , wherein the vias 140 are electrically connected to the first metal layer 120 a and the second metal layer 130 a.

Next, please refer to FIG. 1B and FIG. 1C at the same time, and pattern the first metal layer 120a and the second metal layer 130a to form the first patterned metal layer 120 and the second patterned metal layer as shown in FIG. 1C respectively. Layer 130. In detail, the step of patterning the second metal layer 130a may include: first, performing a first patterning process on the second metal layer 130a to form a plurality of pads connected to each other as shown in FIG. 1B 132a and the metal pad portion 134a, wherein the thickness of the metal pad portion 134a is greater than the thickness of the welding pad portion 132a. Next, the above-mentioned second metal layer 130a is subjected to a second patterning process to form a plurality of openings 136 between the metal pad portion 134a and the welding pad portion 132a and between the welding pad portions 132a to define the following FIG. 1C shows the solder pads 132 and the metal pads 134 separated from each other. Moreover, the first metal layer 120a may be patterned at the same time to form the first patterned metal layer 120 as shown in FIG. 1C . In this embodiment, the solder pad 132 has a first thickness T1, and the maximum thickness T2 of the metal pad 134 is greater than the first thickness T1. Further, the metal pad 134 has a flange portion 134c and a main body portion 134b, the flange portion 134c surrounds the main body portion 134b, and the flange portion 134c has a first height relative to the second surface 114, and the first height is equal to the soldering height. The first thickness T1 of the pad 132 ; the main body portion 134 b has a second height relative to the second surface 114 , and the second height is equal to the maximum thickness T2 of the metal pad 134 . In this embodiment, the patterning treatment on the first metal layer 120a can be performed simultaneously with the second patterning treatment on the second metal layer 130a. Of course, the present invention is not limited thereto. In other embodiments Among them, the patterning treatment on the first metal layer 120a may also be performed separately from the second patterning treatment.

Next, referring to FIG. 1D , a solder resist layer 150 is formed. The solder resist layer 150 covers the second surface 114 and has a first opening 150 a and a plurality of second openings 150 b. The first opening 150 a partially exposes the metal pad 134 , and the second openings 150 b partially exposes the solder pad 132 respectively. Specifically, the solder resist layer 150 covers the flange portion 134 c of the metal pad 134 , and the first opening 150 a exposes the bottom surface 134 d of the main body portion 134 b facing away from the second surface 114 . The maximum thickness T3 of the solder resist layer 150 is equal to the maximum thickness T2 of the metal pad 134 . In other words, the bottom surface 134d of the main body portion 134b of the metal pad 134 is coplanar with the lower surface 152 of the solder resist layer 150 facing away from the second surface 114 . In addition, in this embodiment, the solder resist layer 150 may further cover the first surface 112 of the core layer 110 and partially expose the first patterned metal layer 120 as shown in FIG. 1D . In this way, the substrate 100 as shown in FIG. 1D is formed.

Next, please refer to FIG. 1E , disposing the chip 200 on the first surface 112 and electrically connecting the chip 200 and the first patterned metal layer 120 . In detail, the chip 200 is disposed on the solder resist layer 150 on the first surface 112 and is electrically connected to the first patterned metal layer 120 exposed by the solder resist layer 150 . In this embodiment, the chip 200 can be electrically connected to the first patterned metal layer 120, for example, through a plurality of wires 400, that is, electrically connected to the substrate 100 by wire bonding. Of course, the present invention is not limited thereto. here. In other embodiments, the chip 200 may also be electrically connected to the substrate 100 through flip-chip bonding. Specifically, the distribution range A1 of the first opening 150 a partially exposing the metal pad 134 at least partially overlaps with the orthographic projection P1 of the chip 200 on the second surface 114 . More specifically, the distribution range A1 of the first openings 150a may be within the range of the orthographic projection P1 of the chip 200 on the second surface 114 as shown in FIG. The projection P1 may completely cover the distribution range A1 of the first opening 150a. In this case, the bottom surface 134d of the main body portion 134b of the metal pad 134 is coplanar with the lower surface 152 of the solder resist layer 150, so that when the substrate 100 is subjected to a normal stress, the supporting force below it is relatively uniform, which can Avoid warping of the substrate 100 and cracks of the chip 200 caused by stress concentration on the edge of the metal pad 134 (ie, the boundary of the first opening 150 a ). In this embodiment, the metal pad 134 can be a heat dissipation pad, so that the heat energy generated by the chip 200 can be dissipated to the outside through the metal pad 134 .

Next, referring to FIG. 1F , an encapsulant 300 is formed on the first surface 112 , wherein the encapsulant 300 covers the chip 200 and the first patterned metal layer 120 . When the encapsulant 300 is formed to cover the chip 200, the substrate 100 and the chip 200 bear the positive stress applied by the encapsulant 300. At this time, the bottom surface 134d of the metal pad 134 is coplanar with the lower surface 152 of the solder mask 150. The configuration can provide uniform support for the substrate 100 , thereby avoiding warping of the substrate 100 and cracking of the chip 200 caused by stress concentration. In this way, the fabrication of the package structure 10 is roughly completed.

In terms of structure, the packaging structure 10 formed according to the above manufacturing method may include a substrate 100 , a chip 200 and an encapsulant 300 as shown in FIG. 1F . The substrate 100 includes a core layer 110 , a first patterned metal layer 120 , a second patterned metal layer 130 and a solder resist layer 150 . The core layer 110 includes a first surface 112 and a second surface 114 opposite to each other. The first patterned metal layer 120 and the second patterned metal layer 130 are respectively disposed on the first surface 112 and the second surface 114 . The second patterned metal layer 130 includes a plurality of solder pads 132 and metal pads 134, wherein the maximum thickness T2 of the metal pads 134 is greater than the first thickness T1 of the solder pads 132, and the solder resist layer 150 covers the second surface 114, and There are a first opening 150 a and a plurality of second openings 150 b , wherein the first opening 150 a partially exposes the metal pad 134 , and the second openings 150 b partially expose the solder pad 132 respectively. The maximum thickness T3 of the solder resist layer 150 is equal to the maximum thickness T2 of the metal pad 134 . That is to say, the bottom surface 134 d of the metal pad 134 facing away from the second surface 114 is coplanar with the lower surface 152 of the solder resist layer 150 facing away from the second surface 114 . The chip 200 is disposed on the first surface 112 and electrically connected to the first patterned metal layer 120 . The distribution range A1 of the first openings 150 a at least partially overlaps with the orthographic projection P1 of the chip 200 on the second surface 114 . The encapsulant 300 is formed on the first surface 112 and covers the chip 200 and the first patterned metal layer 120 .

In summary, the packaging structure and the manufacturing method thereof of the present invention form a second patterned metal layer having a plurality of welding pads and metal pads through two-stage patterning process, wherein the maximum thickness of the metal pads is greater than the thickness of the welding pads, And equal to the maximum thickness of the solder resist layer, so that the bottom surface of the metal pad facing away from the second surface and the lower surface of the solder resist layer facing away from the second surface are coplanar. In this way, when the wire bonding and sealing process are performed, the bottom surface of the metal pad and the lower surface of the solder resist layer are coplanar to provide uniform support when the substrate and chip are subjected to positive stress, thereby avoiding stress. Concentrated problems, thereby reducing substrate warping and chip cracking. Therefore, the present invention can indeed effectively improve the structural reliability of the packaging structure and the yield rate of the manufacturing process.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (14)

1. A packaging structure, characterized in that, comprising: Substrates, including: a core layer comprising a first surface and a second surface opposite the first surface; a first patterned metal layer disposed on the first surface; The second patterned metal layer is disposed on the second surface, the second patterned metal layer includes a plurality of welding pads and metal pads, the welding pads have a first thickness, and the maximum thickness of the metal pads is greater than the the first thickness; and a solder resist layer covering the second surface and having a first opening and a plurality of second openings, the first opening partially exposes the metal pad, the second openings partially expose the solder pads, and The maximum thickness of the solder resist layer is equal to the maximum thickness of the metal pad; a chip disposed on the first surface and electrically connected to the first patterned metal layer, the distribution range of the first opening at least partially overlaps with the orthographic projection of the chip on the second surface; and The encapsulant is arranged on the first surface and covers the chip and the first patterned metal layer. 2. The packaging structure according to claim 1, wherein the metal pad has a flange portion and a main body portion, the flange portion has a first height relative to the second surface, and the first height Equal to the first thickness, the body portion has a second height relative to the second surface, the second height being equal to the maximum thickness of the metal pad. 3. The package structure according to claim 2, wherein the solder resist layer covers the flange portion of the metal pad and the first opening exposes the main body portion away from the second surface The bottom surface of the solder resist layer is coplanar with the lower surface of the solder resist layer away from the second surface. 4 . The package structure according to claim 1 , wherein a distribution range of the first openings is located within an orthographic projection of the chip on the second surface. 5. The package structure according to claim 1, wherein the metal pad is a heat dissipation pad. 6. The packaging structure according to claim 1, wherein the solder resist layer also covers the first surface and partially exposes the first patterned metal layer, and the chip is arranged on the solder resist layer and electrically connect the exposed first patterned metal layer. 7. The package structure according to claim 1, wherein the substrate further comprises a plurality of vias disposed on the core layer to electrically connect the first patterned metal layer and the second patterned metal layer. Pattern the metal layer. 8. A method for manufacturing a packaging structure, comprising: A base material is provided, the base material includes a core layer, a first metal layer and a second metal layer, the core layer includes a first surface and a second surface opposite to each other, the first metal layer and the second metal layer respectively disposed on the first surface and the second surface; Patterning the first metal layer and the second metal layer to form a first patterned metal layer and a second patterned metal layer respectively, the second patterned metal layer includes a plurality of welding pads and metal pads, the pads have a first thickness, and the maximum thickness of the metal pads is greater than the first thickness; forming a solder resist layer, the solder resist layer covers the second surface, and has a first opening and a plurality of second openings, the first opening partially exposes the metal pad, and the second openings are partially exposed respectively out of these solder pads, and the maximum thickness of the solder resist layer is equal to the maximum thickness of the metal pad; A chip is disposed on the first surface, the chip is electrically connected to the first patterned metal layer, and the distribution range of the first opening is at least partly the same as the orthographic projection of the chip on the second surface overlap; and An encapsulant is formed on the first surface, and the encapsulant covers the chip and the first patterned metal layer. 9. The manufacturing method of the packaging structure according to claim 8, characterized in that, the step of performing the patterning treatment on the second metal layer further comprises: performing a first patterning process on the second metal layer to form metal pads connected to each other and a plurality of welding pads; and performing a second patterning process on the second metal layer to form a plurality of openings between the metal pad portion and the welding pad portions, so as to define the metal pad and the welding pads separated from each other , wherein the metal pad has a flange portion and a body portion, the flange portion has a first height relative to the second surface, the first height is equal to the first thickness, and the body portion has a first height relative to the second surface. The second surface has a second height equal to the maximum thickness of the metal pad. 10. The manufacturing method of the packaging structure according to claim 9, wherein the solder resist layer covers the flange portion of the metal pad and the first opening exposes the main body portion away from the The bottom surface of the second surface is coplanar with the lower surface of the solder resist layer away from the second surface. 11. The manufacturing method of the package structure according to claim 8, wherein the distribution range of the first openings is within the orthographic projection of the chip on the second surface. 12. The manufacturing method of the package structure according to claim 8, wherein the metal pad is a heat dissipation pad. 13. The manufacturing method of the package structure according to claim 8, wherein the solder resist layer also covers the first surface and partially exposes the first patterned metal layer, and the chip is arranged on the on the solder resist layer and electrically connect the exposed first patterned metal layer. 14. The manufacturing method of the packaging structure according to claim 8, further comprising: forming a plurality of via holes in the core layer, the via holes communicating the first metal layer and the second metal layer; and Electroplating is performed on the through holes to form a plurality of via posts, and the via posts are electrically connected to the first metal layer and the second metal layer.