CN106298706A - A kind of wafer bumps forming method - Google Patents
A kind of wafer bumps forming method Download PDFInfo
- Publication number
- CN106298706A CN106298706A CN201510259154.7A CN201510259154A CN106298706A CN 106298706 A CN106298706 A CN 106298706A CN 201510259154 A CN201510259154 A CN 201510259154A CN 106298706 A CN106298706 A CN 106298706A
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- Prior art keywords
- projection
- semiconductor substrate
- forming method
- wafer bumps
- bumps forming
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 238000010992 reflux Methods 0.000 claims abstract description 15
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 7
- 239000000956 alloy Substances 0.000 claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000002253 acid Substances 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 5
- 238000007654 immersion Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 18
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 abstract description 12
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 abstract description 6
- 235000019253 formic acid Nutrition 0.000 abstract description 6
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- NDVLTYZPCACLMA-UHFFFAOYSA-N silver oxide Chemical compound [O-2].[Ag+].[Ag+] NDVLTYZPCACLMA-UHFFFAOYSA-N 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910001923 silver oxide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- XVVLAOSRANDVDB-UHFFFAOYSA-N formic acid Chemical compound OC=O.OC=O XVVLAOSRANDVDB-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of wafer bumps forming method, and it comprises the steps: to provide Semiconductor substrate, forms projection on the semiconductor substrate；Described projection is formed solder ball；Described Semiconductor substrate is carried out, to remove the oxide of described solder surface；Perform high temperature reflux, so that described projection forms stable alloy.The wafer bumps forming method that the present invention proposes, after forming projection, before described projection is carried out high temperature reflux, described projection is carried out, to remove the oxide on tin-silver solder ball surface, follow-up oxide when carrying out high temperature reflux due to solder ball surface has been removed, thus decreases formic acid and react, with oxide, the grain defect produced, and improves product yield.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of wafer bumps side of being formed
Method.
Background technology
Along with portable and high-performance microelectronics product develop to short, little, light, thinning direction,
The encapsulation skill that tradition routing mode (Wire Bonding) is combined with various base material as wafer
Art can not meet the demand of present consumption electronic product, and instead projection is encapsulated into
The key technology of wafer-level packaging.In projection packaging technology, multiplex electric plating method is carried out
Forming projection, first the most traditional flow process as it is shown in figure 1, carry out step S101, sharp
Form copper seed layer with physical vaporous deposition (PVD) at crystal column surface, then walk
Rapid S102, coating photoresist on copper seed layer, by photoetching process, projection is formed district
Develop out in territory.Then, perform step S103, form metal coupling by electroplating technology
With stannum ping-pong ball solder.Then, perform step S104, perform high temperature reflux, so that projection
Alloy stable molding.Additionally, in the reflux course of flux-free (Flux), generally make
Carry out stannum ping-pong ball surface with formic acid (Formic Acid) to process, it is ensured that solder reflow is complete.
But at high temperature formic acid and stannum silver oxide easily produce grain defect, this defect is being produced
Product complete after inspection (OQC) in be very easy to find, as in figure 2 it is shown, it is deposited for projection
At the examination and test of products figure of grain defect, in figure, intermediate annular part represents grain defect, passes through
Defects detection can observe this grain defect, as shown in Figure 3.See Fig. 4, by
The elementary analysis of grain defect understands, and the essential element composition of grain defect is Sn, O and C,
This has also confirmed formic acid and stannum silver oxide when grain defect is backflow and has produced.
Therefore, how reducing backflow grain defect is step important during projection produces.
Backflow grain defect is reduced at present by increase refluxing unit maintenance program and number of times, but
This can reduce life cycle of the product, has a significant impact production efficiency.
Therefore, it is necessary to propose a kind of new manufacture method, with the problem solving above-mentioned existence.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, the present invention provides a kind of wafer bumps forming method,
It comprises the steps: to provide Semiconductor substrate, forms projection on the semiconductor substrate；
Described projection is formed solder ball；Described Semiconductor substrate is carried out, described to remove
The oxide of solder surface；Perform high temperature reflux, so that described projection forms stable alloy.
Preferably, form projection on the semiconductor substrate and specifically include following step: provide
Semiconductor substrate, forms copper seed layer on the semiconductor substrate；On described copper seed layer
Coating photoresist, and carry out exposed and developed, with definition for forming the region of projection；Institute
Projection is formed in stating the region for forming projection.
Preferably, by using the composite solution of pyrovinic acid and phosphoric acid to soak described quasiconductor lining
The end, realizes being carried out described Semiconductor substrate.
Preferably, the concentration of described pyrovinic acid is 3%～12%.
Preferably, the concentration of described phosphoric acid is 0.5%～2%.
Preferably, the composite solution using pyrovinic acid and phosphoric acid soaks described Semiconductor substrate
60～200 seconds.
Preferably, also comprise the steps: to remove described photoresist after forming described projection.
Preferably, also comprise the steps: to remove described projection both sides after forming described projection
Copper seed layer.
The wafer bumps forming method that the present invention proposes, after forming projection, to described convex
Before block carries out high temperature reflux, described projection is carried out, to remove tin-silver solder ball surface
Oxide, follow-up when carrying out high temperature reflux due to solder ball surface oxide
Remove, thus decrease formic acid and react, with oxide, the grain defect produced, improve product good
Rate.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 shows the flow chart of steps of wafer bumps forming method in prior art；
Fig. 2 shows the examination and test of products figure of the projection that there is grain defect；
Fig. 3 shows the grain defect on projection；
Fig. 4 shows the elementary analysis figure of projection grain defect；
Fig. 5 shows the step of wafer bumps forming method according to an embodiment of the present invention
Flow chart；
Fig. 6 A～Fig. 6 G shows wafer bumps forming method according to an embodiment of the present invention
Implement the generalized section of the obtained device of each step successively；
Fig. 7 shows what wafer bumps forming method according to an embodiment of the present invention was formed
The examination and test of products figure of wafer bumps.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to "
Or when " being coupled to " other element or layer, its can directly on other element or layer and
Adjacent, be connected or coupled to other element or layer, or element between two parties or layer can be there is.
On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other element or layer, the most there is not element between two parties or layer.Should
Understand, although can use term first, second, third, etc. describe various element, parts,
District, floor and/or part, these elements, parts, district, floor and/or part should be by these
Term limits.These terms be used merely to distinguish an element, parts, district, floor or part with
Another element, parts, district, floor or part.Therefore, under without departing from present invention teach that,
First element discussed below, parts, district, floor or part be represented by the second element, parts,
District, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... it
Under ", " ... on ", " above " etc., here can describe for convenience and used from
And shown in figure a element or feature and other element or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operating
In the different orientation of device.Such as, if the device upset in accompanying drawing, then, it is described as
" below other element " or " under it " or " under it " element or feature will orientations
For other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention describes in detail
As follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Below in conjunction with Fig. 5 and Fig. 6 A～Fig. 6 G, the projection method for packing of the present invention is done in detail
Describe.
As it is shown in figure 5, first, step S501 is performed, it is provided that Semiconductor substrate, described
Copper seed layer is formed in Semiconductor substrate.
As shown in Figure 6A, it is provided that Semiconductor substrate 600, Semiconductor substrate 600 is formed
Copper seed layer 601.Semiconductor substrate 600 can be at least in the following material being previously mentioned
Kind: stacking silicon (SSOI), insulator on silicon, germanium, silicon-on-insulator (SOI), insulator
Upper stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulator
Upper germanium (GeOI).Outward, Semiconductor substrate could be formed with other device, such as PMOS
And nmos pass transistor.Could be formed with isolation structure, described isolation in the semiconductor substrate
Structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
Semiconductor substrate can also be formed cmos device, cmos device e.g. transistor
(such as, NMOS and/or PMOS) etc..Equally, Semiconductor substrate can also be formed
Having conductive member, conductive member can be the grid of transistor, source electrode or drain electrode, it is also possible to is
The metal interconnection structure electrically connected with transistor, etc..As example, in the present embodiment,
Semiconductor substrate is crystal silicon.
Copper seed layer 601 can be formed by method commonly used in the art, such as physical vapour deposition (PVD)
(PVD), the method such as plating.As example, in the present embodiment, copper seed layer passes through PVD
Being formed, its thickness is
Then, perform step S502, described copper seed layer coats photoresist, and carries out
Exposed and developed, with definition for forming the region of projection
As shown in Figure 6B, copper seed layer 601 is formed photoresist layer 602, and exposes
Light and development, with definition for forming the region 603 of projection.This step is by commonly used in the art
Lithography step carry out, such as coat photoresist, be exposed with fixed by corresponding mask plate
Justice for forming the region 603 of projection, and with corresponding developer solution carry out developing with removal for
Form the photoresist in the region 603 of projection, expose this region.More than for being briefly described, this
Skilled person can take as required suitable material and technique to complete this step, at this
Repeat no more.
Then, perform step S503, in the described region for forming projection, form projection.
As shown in Figure 6 C, in the region 603 for forming projection, projection 604 is formed.?
In the present embodiment, projection 604 is copper, and it can be formed by electroplating technology, and it is that this area is normal
By method, do not repeat them here.
Then, perform step S504, described projection is formed solder ball
As shown in Figure 6 D, projection 604 forms solder ball 605.In the present embodiment,
Solder ball 605 is tin-silver solder ball, and it can be formed by electroplating technology, and it is commonly used in the art
Method, does not repeats them here.
Then, perform step S505, remove described photoresist layer.
As illustrated in fig. 6e, described photoresist layer 602 is removed.Photoresist layer 602 can be by dry
Method or wet method are removed, and are such as removed by Oxygen plasma ashing, or by suitable colloidal sol
Or the removal of stripper wet method, this repeats no more.
Then, perform step S506, remove the copper seed layer of described projection both sides.
As fig 6 f illustrates, the copper seed layer of projection 604 both sides is removed.
Then, perform step S507, described Semiconductor substrate is carried out, to remove
State the oxide of solder surface.
In the present embodiment, by using the composite solution of pyrovinic acid and phosphoric acid to soak described half
Conductor substrate realizes being carried out described Semiconductor substrate.Wherein, described pyrovinic acid
Concentration is 3%～12%, and the concentration of described phosphoric acid is 0.5%～2%, and described soak time is
60～200 seconds.
Then, perform step S508, perform high temperature reflux, so that projection forms stable alloy.
As shown in Figure 6 G, perform high temperature reflux, make projection 604 and solder ball 605 be formed surely
Determine alloy.Specifically, at a temperature of about 240 DEG C, such as process described Semiconductor substrate 600,
Make projection 604 and solder ball 605 reflux, to form stable alloy, backflow time during can
Formic acid is used tin-silver solder ball surface to be processed, to guarantee that solder reflow is complete.
So far the Overall Steps of the present embodiment wafer bumps forming method is completed, it is possible to understand that
It is in whole packaging technology, to may also include other desired step, or the present embodiment is above-mentioned
The order of step can be adjusted as required, and the such as cleaning to Semiconductor substrate can removed
Carry out before photoresist layer, or after removing photoresist layer, remove projection both sides copper seed layer
Carry out before.
The wafer bumps forming method that the present embodiment proposes, after forming projection, to described
Before projection carries out high temperature reflux, described projection is carried out, to remove tin-silver solder ball table
The oxide in face, follow-up when carrying out high temperature reflux due to solder ball surface oxide
Through removing, thus decrease formic acid and react, with oxide, the grain defect produced, improve product
Yield.As it is shown in fig. 7, the wafer bumps forming method formation that it is employing the present embodiment is convex
The examination and test of products figure of block, understands with Fig. 2 contrast, uses the wafer bumps side of being formed of the present embodiment
Method, the grain defect of projection greatly reduces, and product yield is greatly improved.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (8)
1. a wafer bumps forming method, it is characterised in that comprise the steps:
Semiconductor substrate is provided, forms projection on the semiconductor substrate；
Described projection is formed solder ball；
Described Semiconductor substrate is carried out, to remove the oxide of described solder surface；
Perform high temperature reflux, so that described projection forms stable alloy.
Wafer bumps forming method the most according to claim 1, it is characterised in that
Form projection in described Semiconductor substrate and specifically include following step:
Semiconductor substrate is provided, forms copper seed layer on the semiconductor substrate；
Described copper seed layer coats photoresist, and carries out exposed and developed, be used for definition
Form the region of projection；
Projection is formed in the described region for forming projection.
Wafer bumps forming method the most according to claim 1 and 2, it is characterised in that
It is right to be realized by the described Semiconductor substrate of composite solution immersion using pyrovinic acid and phosphoric acid
Described Semiconductor substrate is carried out.
Wafer bumps forming method the most according to claim 3, it is characterised in that institute
The concentration stating pyrovinic acid is 3%～12%.
Wafer bumps forming method the most according to claim 3, it is characterised in that institute
The concentration stating phosphoric acid is 0.5%～2%.
Wafer bumps forming method the most according to claim 3, it is characterised in that make
Described Semiconductor substrate 60～200 seconds is soaked with the composite solution of pyrovinic acid and phosphoric acid.
Wafer bumps forming method the most according to claim 2, it is characterised in that
Also comprise the steps: after forming described projection
Remove described photoresist.
Wafer bumps forming method the most according to claim 2, it is characterised in that
Also comprise the steps: after forming described projection
Remove the copper seed layer of described projection both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510259154.7A CN106298706A (en) | 2015-05-20 | 2015-05-20 | A kind of wafer bumps forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510259154.7A CN106298706A (en) | 2015-05-20 | 2015-05-20 | A kind of wafer bumps forming method |
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| Publication Number | Publication Date |
|---|---|
| CN106298706A true CN106298706A (en) | 2017-01-04 |
Family
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| CN201510259154.7A Pending CN106298706A (en) | 2015-05-20 | 2015-05-20 | A kind of wafer bumps forming method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5878943A (en) * | 1990-02-19 | 1999-03-09 | Hitachi, Ltd. | Method of fabricating an electronic circuit device and apparatus for performing the method |
| US6471115B1 (en) * | 1990-02-19 | 2002-10-29 | Hitachi, Ltd. | Process for manufacturing electronic circuit devices |
| CN202394889U (en) * | 2011-12-02 | 2012-08-22 | 日月光半导体（上海）股份有限公司 | Semiconductor packaging structure |
| CN102810522A (en) * | 2011-05-30 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Packaging structures and methods |
| CN107154388A (en) * | 2016-03-02 | 2017-09-12 | 三星电子株式会社 | Semiconductor package assembly and a manufacturing method thereof |
-
2015
- 2015-05-20 CN CN201510259154.7A patent/CN106298706A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5878943A (en) * | 1990-02-19 | 1999-03-09 | Hitachi, Ltd. | Method of fabricating an electronic circuit device and apparatus for performing the method |
| US6471115B1 (en) * | 1990-02-19 | 2002-10-29 | Hitachi, Ltd. | Process for manufacturing electronic circuit devices |
| CN102810522A (en) * | 2011-05-30 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Packaging structures and methods |
| CN202394889U (en) * | 2011-12-02 | 2012-08-22 | 日月光半导体（上海）股份有限公司 | Semiconductor packaging structure |
| CN107154388A (en) * | 2016-03-02 | 2017-09-12 | 三星电子株式会社 | Semiconductor package assembly and a manufacturing method thereof |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170104 |
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