CN106293616A - True Random Number Generator based on time delay feedback agitator - Google Patents

Abstract

The invention discloses a real random number generator based on a time-delay feedback oscillator, which mainly solves the problems of low rate and poor randomness of true random number generators in the prior art. It includes an oscillating circuit and a sampling circuit, the oscillating circuit is used to generate a random oscillating signal. It is composed of several time-delay feedback XOR oscillators and several time-delay feedback XOR oscillator groups. Each time-delay feedback XOR oscillator is composed of an XOR gate and three upper inverter groups. Each The time-delay feedback NOR oscillator consists of a NOR gate and three lower inverter groups, where each inverter group contains a different number of inverters; the sampling circuit is used for the random oscillation signal generated by the oscillator circuit Sampling is performed, which is composed of several D flip-flops and an XOR gate, and the outputs of all D flip-flops pass through the XOR gate to generate true random numbers with a rate above 100Mbit/s. The invention has simple structure, good randomness of entropy source, and can be used for secure communication.

Description

A True Random Number Generator Based on Delayed Feedback Oscillator

technical field

The invention belongs to the technical field of digital circuits, in particular to a true random number generator based on a delay feedback oscillator, which can be used for secure communication.

Background technique

In a cryptographic system, random numbers play an important role in encrypting text information, images or videos. There are two main types of existing random numbers, true random numbers and pseudorandom numbers. Pseudo-random numbers are easy to implement in software, and their security depends on the complexity of a given algorithm and the key seed. Although they have good statistical properties, they cannot be guaranteed to be unpredictable; true random numbers rely on uncertain Sources of entropy, such as analog phenomena in electronics, are very unpredictable. Therefore, for cryptographic systems with high security requirements, true random numbers have become a better choice.

Among the existing true random number generators, many rely on external noise sources to provide the randomness required by the system, such as the patent (patent publication number: CN201773390U) of Yuan Yidong, Zhang Haifeng, and Zhang Zhe based on resistance noise processing True random number generator, by extracting the noise signal to drive the structure of the voltage-controlled oscillator to generate an oscillating signal with large phase noise, and applying post-processing to obtain random numbers; Wu Xiaoyong and Wang Xinya's patent (patent publication number: CN103049243A) true random number The generation method and device generate random numbers through summing and amplifying the quantization error in the process of analog-to-digital conversion and digital-to-analog conversion, and then summing and amplifying the introduced thermal noise. However, the noise source is unstable, and an attacker can destroy the entire generator by attacking the noise source, so this method is not very safe. In addition, there are also many true random number generators based on oscillators, such as the patent of Feng Rui, Hu Yangchuan, and He Weiguo (patent publication number: CN103150138A), which is a true random number generator based on digital circuits. The circuit is connected to the frequency control end of the basic oscillation sampling circuit in the main oscillation sampling circuit, and then the post-processing circuit is used to sample at the output end of the basic oscillation sampling circuit to obtain a true random number; the patent of Bai Guoqiang, Zhang Xiaofeng, and Chen Hongyi (patent publication number: CN101819515A ) A true random number generating circuit based on a ring oscillator and a true random number generator, using two high-frequency ring oscillation circuits with input terminals and a low-frequency ring oscillation circuit to form a true random number generation circuit, and then post-processing it .

In the above method, the noise source is used as an external noise source, and the attacker can attack it by controlling the external noise source, so the security of the true random number generated by this method cannot be guaranteed; secondly, some methods are based on the traditional anti-corruption method. Oscillators composed of commutators to generate random numbers, because the phase randomness of the oscillation signal of this oscillator is extremely small in a short period of time, so

Sampling must wait long enough to ensure sufficient randomness in the sampled output, so these methods generate random numbers at a low rate.

Contents of the invention

The object of the present invention is to propose a true random number generator based on a time-delay feedback oscillator to avoid attacks on external input ports and improve the security of confidential communication.

To achieve the above object, the present invention includes:

an oscillating circuit for generating a random oscillating signal with a random phase offset;

The sampling circuit is used for sampling the random oscillating signal generated by the oscillating circuit, and converting the continuous analog signal into a discrete digital signal for output.

It is characterized by:

The oscillating circuit includes: N identical time-delay feedback XOR oscillators, M identical time-delay feedback XOR oscillators, N and M are both integers greater than 1, and satisfy N+M>3;

Each time-delay feedback XOR oscillator is composed of an XOR gate XOR and three up-inverter groups R, each up-inverter group R is composed of different even-numbered inverters, and the XOR gate XOR is set There are three input ports and one output port; the three input ports of the exclusive OR gate XOR are respectively connected to the output ports of the three upper inverter groups R; the output port of the exclusive OR gate XOR is connected to each upper inverter The input port connections of group R;

Each delay feedback NOR oscillator is composed of a NOR gate XNOR and three lower inverter groups B; each lower inverter group B is composed of a different odd number of inverters, and the NOR gate XNOR Each has three input ports and one output port, and the three input ports of the same-OR gate XNOR are respectively connected to the output ports of the three lower inverter groups B; the output port of the same-OR gate XNOR is connected to each lower inverter The input ports of Group B are connected.

The present invention has the following advantages as follows:

1. The generated true random number has strong stability and high output rate.

Because the present invention adopts the time-delay feedback XOR oscillator and the delay feedback XOR oscillator to form an oscillating circuit, it can generate stable chaotic oscillation, which has a very high oscillation frequency and a very wide frequency spectrum, and utilizes the stable chaotic oscillation Oscillation can generate stable and high-speed true random numbers.

2. Since the oscillating circuit of the present invention includes different numbers of time-delay feedback XOR oscillators and time-delay feedback XOR oscillators, the diversity and flexibility of design are increased.

3. In the present invention, since the entire random number generator is only realized by inverters, XOR gates and NOR gates, the circuit is easy to be integrated and miniaturized, and can be widely used in security-specific chips.

Description of drawings

Fig. 1 is a block diagram of the present invention;

Fig. 2 is a circuit structure diagram of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Referring to Fig. 1, the present invention includes an oscillating circuit and a sampling circuit. The oscillating circuit is composed of N identical time-delay feedback XOR oscillators and M identical time-delay feedback XOR oscillators for generating random oscillation signals; the sampling circuit is composed of N+M D flip-flops for The random oscillating signal generated by the oscillating circuit is sampled, the output of the sampling sub-circuit in the sampling circuit is XORed as an output port of the sampling circuit, and a true random number sequence is output.

With reference to Fig. 2, oscillation circuit and sampling circuit structure of the present invention are described as follows:

The oscillating circuit includes: N identical time-delay feedback XOR oscillators, M identical time-delay feedback XOR oscillators, where N and M are both integers greater than 1 and satisfy N+M>3;

Each time-delay feedback XOR oscillator is composed of an XOR gate XOR and three upper inverter groups R;

The three upper inverter groups R are respectively represented as the first upper inverter group R ₁ , the second upper inverter group R ₂ , and the third upper inverter group R ₃ , these three upper inverter groups R The number of inverters is different, which are: the first upper inverter group R ₁ is composed of 2 inverters in series, and the second upper inverter group R ₂ is composed of 6 inverters in series , the third upper inverter group R ₃ is composed of 18 inverters connected in series.

Each exclusive OR gate XOR has three input ports, namely the first input port, the second input port, the third input port and an output port;

The three input ports of the exclusive OR gate XOR are respectively connected to the output ports of the three upper inverter groups R, that is, the first input port of the exclusive OR gate XOR is connected to the output port of the _first upper inverter group R1 ; The second input port of the exclusive OR gate XOR is connected to the output port of the _second upper inverter group R2; the third input port of the exclusive OR gate XOR is connected to the output port of the third upper inverter group _R3 ; The output port of the exclusive OR gate XOR is connected with the input port of each upper inverter group R.

Each delay feedback NOR oscillator is composed of a NOR gate XNOR and three lower inverter groups B;

The three lower inverter groups B are respectively denoted as the first lower inverter group B ₁ , the second lower inverter group B ₂ , and the third lower inverter group B ₃ , these three lower inverter groups The number of inverters in inverter group B is different, which are: the first lower inverter group B ₁ is composed of 1 inverter in series, and the second lower inverter group B ₂ is composed of 7 inverters inverters in series, and the third lower inverter group B ₃ is composed of 17 inverters in series.

For each XNOR gate, there are three input ports, namely the first input port, the second input port, the third input port and an output port;

The three input ports of the same OR gate XNOR are respectively connected to the output ports of the three lower inverter groups B correspondingly, that is, the first input port is connected to the output port of the _first lower inverter group B1; the second input port It is connected to the output port of the _second lower inverter group B2; the _third input port is connected to the output port of the third lower inverter group B3. The output port of the XNOR gate is connected with the input port of each lower inverter group B.

The sampling circuit is composed of N ₊ M flip-flops D1, D2, D3, . It is connected to N exclusive OR gates XOR in the oscillation circuit, and the last M D flip-flops are respectively connected to M exclusive OR gates XNOR in the oscillation circuit. The N+M flip-flops D1, D2, D3, ..., DN The output of +M is used as the input of the N+1th XOR gate XOR _N +1, and the output of the N+1th XOR gate XOR _N+1 is used as the output of the sampling circuit. The N+M flip-flops D1, D2, D3, ..., DN+M and one exclusive OR gate, that is, the N+1th exclusive OR gate XOR _N+1 are all controlled by the same clock, which is provided by the external clock CLK.

Effect of the present invention can be further illustrated by the following test results:

1. Detection method:

Driven by an external clock frequency of 100MHZ, 1000 groups of 1M true random sequences are generated;

Use the SP800-22 random number test standard provided by the National Institute of Standards and Technology NIST to test the randomness of the above 1000 groups of 1M true random sequences. The test standard includes 15 test items, and the test results generated by each test Contains a P-value value and a pass rate Propotion value. When the P-value value is not lower than 0.001 and the pass rate value is not lower than 0.9806, it means that the test content is passed.

2. Test results:

The true random sequence of 1000 groups of 1M produced by the present invention is detected with the SP800-22 random number detection standard provided by the National Institute of Standards and Technology NIST of the United States, and the results are shown in Table 1:

Table 1 Test results

Statistical Test P-value Proposition Result Frequency 0.969688 0.9944 pass Block Frequency 0.456986 0.9861 pass Cumulative Sums 0.762645 0.9953 pass run 0.314654 0.9888 pass Longest Run 0.125744 0.9888 pass Rank 0.404423 0.9860 pass FFT 0.479815 0.9860 pass OverlappingTemplate 0.290965 0.9888 pass Universal 0.206718 0.9842 pass Linear Complexity 0.504632 0.9879 pass ApproximateEntropy 0.297427 0.9925 pass Serial 0.305762 0.9879 pass NonOverlappingTemplate 0.293816 0.9851 pass Random Excursions 0.173693 0.9876 pass RandomExcursionsVariant 0.707318 0.9892 pass

As can be seen from Table 1, each index of the true random sequence produced by the present invention has reached the requirement standard of random numbers, indicating that the random numbers produced by the present invention have good randomness.

Above-mentioned embodiment is only used for concrete implementation to illustrate the realization method of the present invention, does not constitute limitation to the present invention, obviously can have multiple deformations on this basis of the present invention, and this structural change based on the present invention is all included in the present invention within the scope of protection.

Claims (10)

1. True Random Number Generator based on time delay feedback agitator, including:

Oscillating circuit, for producing the Random Oscillation signal with random phase offset；

Sample circuit, for oscillating circuit produce Random Oscillation signal sample, continuous analog signal is converted into from Scattered digital signal exports.

It is characterized in that:

Described oscillating circuit, including: the individual identical time delay feedback of N number of identical time delay feedback XOR agitator, M is same or vibrates Device, N, M are the integer more than 1, and meet N+M > 3；

Each time delay feedback XOR agitator is constituted by upper reverser group R of an XOR gate XOR and three, each upper reverser Group R is made up of different even number reversers, and XOR gate XOR is provided with three input ports and an output port；This XOR gate Three input ports of XOR are corresponding with the output port of three upper reverser groups R respectively to be connected；The outfan of this XOR gate XOR Mouth is connected with the input port of each upper reverser group R；

Each time delay feedback is same or agitator is constituted by a same or door XNOR and three lower reverser groups B；Each lower reversely Device group B is made up of different odd number reversers, this with or door XNOR all have three input ports and an output port, with or Three input ports of door XNOR are corresponding with the output port of three lower reverser groups B respectively to be connected；This with or door XNOR defeated Go out port to be connected with the input port of each lower reverser group B.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: time delay is anti- The reverser number in 3 upper reverser groups R in feedback XOR agitator is respectively as follows: first upper reverser group R₁Anti-by 2 It is composed in series to device, second upper reverser group R₂It is composed in series by 6 reversers, the 3rd upper reverser group R₃Anti-by 18 It is composed in series to device.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: time delay is anti- Reverser number in the feedback 3 lower reverser groups B together or in agitator is respectively as follows: first lower reverser group B₁Anti-by 1 It is composed in series to device, second lower reverser group B₂It is composed in series by 7 reversers, the 3rd lower reverser group B₃Anti-by 17 It is composed in series to device.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: XOR gate Three input ports of XOR with the relation of the corresponding connection of output port of reverser groups R on three are respectively: first input port With first upper reverser group R₁Output port connect, the second input port with second go up reverser group R₂Output port Connect, the 3rd input port and the 3rd upper reverser group R₃Output port connect.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: same or door Three input ports of XNOR with the corresponding annexation of output port of three lower reverser groups B are respectively: first input port With first lower reverser group B₁Output port connect, the second input port and second lower reverser group B₂Output port Connect, the 3rd input port and the 3rd lower reverser group B₃Output port connect.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: all of Reverser, all utilizes the basic programmable logic cells of FPGA to realize, and this logical block is by reverse lookup tables LUT₁And depositor Composition, by look-up tables'implementation reverser pure digi-tal logic, preserves digital state by depositor.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: all of XOR gate XOR, all utilizes the basic programmable logic cells of FPGA to realize, and this logical block is by XOR look-up table LUT₂With deposit Device forms, and by look-up tables'implementation XOR pure digi-tal logic, preserves digital state by depositor.

True Random Number Generator based on time delay feedback agitator the most according to claim 1, it is characterised in that: all of With or door XNOR, all utilize the basic programmable logic cells of FPGA to realize, this logical block is by together or look-up table LUT₃With post Storage forms, and by look-up tables'implementation, same or pure digi-tal logic, preserves digital state by depositor.

Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 1, it is characterised in that: Described sample circuit is by N+M trigger D1, D2, D3 .., DN+M and 1 i.e. N+1 XOR gate XOR of XOR gate_N+1Composition, front N number of d type flip flop is connected with the N number of XOR gate XOR in oscillating circuit respectively, rear M d type flip flop respectively with the M in oscillating circuit Individual same or door XNOR is connected, and this N+M trigger D1, D2, D3 .., DN+M export as N+1 XOR gate XOR_N+1Input, The N+1 XOR gate XOR_N+1Output as the output of sample circuit.

Real random number generator based on double coupling Fibonacci oscillation rings the most according to claim 9, its feature exists In: N+M trigger D1, D2, D3 .., DN+M and 1 i.e. N+1 XOR gate XOR of XOR gate_N+1Controlled by identical clock System, this clock is provided by outer clock circuit.