CN106292815B - Low-Dropout Regulator and Output Buffer Including LDO - Google Patents

Abstract

A low-dropout voltage regulator comprises a first input terminal electrically connected to a first DC voltage source, a second input terminal electrically connected to a second DC voltage source, and an output terminal. The voltage value of the second DC voltage source is greater than the voltage value of the first DC voltage source. The low-dropout voltage regulator further comprises an amplification unit, a transduction unit, a current replication unit, and first to third resistors. The voltage value of a DC output voltage generated at the output terminal of the low-dropout voltage regulator is substantially equal to the voltage value of the second DC voltage source minus the voltage value of the first DC voltage source.

Description

Low-Dropout Regulator and Output Buffer Including LDO

technical field

The present invention relates to a low dropout voltage regulator and an output buffer including the low dropout voltage regulator.

Background technique

LDO Regulator (Low Drop-Out Regulator, LDO Regulator) has become the mainstream of low-power power management integrated circuits in recent years due to its low noise, small size, and the improvement of conversion efficiency. Low-dropout voltage regulators are widely used in portable systems powered by batteries and communication-related electronic products to provide a stable output voltage for the load.

FIG. 1 shows a circuit diagram of a prior art LDO regulator 10 . Referring to FIG. 1 , the low dropout regulator 10 includes a bandgap voltage generating circuit 101 , an error amplifier 102 , an output transistor 103 , resistors R1 and R2 , and an output capacitor C1 .

The source and drain of the output transistor 103 are respectively connected to the input terminal and the output terminal of the low dropout voltage regulator 10 . The resistor R1 and the resistor R2 form a voltage divider circuit to provide a feedback voltage VFB proportional to the output voltage VOUT to the positive input terminal of the error amplifier 102 . The error amplifier 102 is used to amplify the difference between a reference voltage VREF and the feedback voltage VFB provided by the bandgap voltage generating circuit 101 to the negative input terminal of the error amplifier 102, so as to generate an output voltage VD to the output transistor 103 grid. When the output voltage VOUT changes, the error amplifier 102 will properly adjust the output voltage VD to change the source-gate voltage of the power transistor 103 by detecting the difference between the feedback voltage VFB and the reference voltage VREF difference, so as to provide enough output current to the load RL to stabilize the output voltage VOUT.

In the prior art, the load RL is connected between the output terminal of the low dropout voltage regulator 10 and a ground terminal. Therefore, the low dropout voltage regulator 10 can provide sufficient source current to the load RL from the DC voltage source VCC through the power transistor 103 . However, limited by its configuration, the LDO regulator 10 can only provide a small sink current to the load RL.

Contents of the invention

One of the objectives of the present invention is to provide a low dropout voltage regulator for providing sink current to a load terminal.

According to an embodiment of the present invention, the low-dropout voltage regulator includes a first input terminal electrically connected to a first DC voltage source, a second input terminal electrically connected to a second DC voltage source, and used to generate constant An output terminal that flows the output voltage. The low dropout regulator further includes an amplifying unit, a transconducting unit, a current copying unit and first to third resistors. The amplifying unit is used for receiving a reference voltage and a feedback voltage to generate a DC output voltage to the output terminal. The transconducting unit is electrically connected to the first input end, and the transconducting unit is used to generate a first current according to the reference voltage. The first resistor is used to receive the first current to generate the reference voltage. The current replication unit is electrically connected to the second input end, and the current replication unit is used to generate a second current and a third current according to the feedback voltage. The second resistor is used for receiving the second current to generate the feedback voltage. The third resistor is electrically connected between the current replication unit and the output terminal, and the third resistor is used for receiving the third current to generate the DC output voltage. The voltage value of the second DC voltage source is greater than the voltage value of the first DC voltage source.

Description of drawings

FIG. 1 shows a circuit diagram of a prior art LDO regulator.

FIG. 2 shows a circuit diagram of a low dropout voltage regulator incorporating an embodiment of the present invention.

Figure 3 shows a schematic circuit diagram of a low dropout voltage regulator incorporating an embodiment of the present invention

FIG. 4 shows a block diagram of an output buffer incorporating an embodiment of the present invention.

Symbol Description

100 Low Dropout Voltage Regulator

101 Bandgap Voltage Generation Circuit

102 Error amplifier

103 output transistor

200 Low Dropout Voltage Regulator

22 amplifier unit

224 operational amplifier

24 transduction units

26 current replica unit

400 output buffer

42 output stage

44 voltage level shifter

46 Voltage Level Shifter

C1 output capacitance

M1～M6 Transistors

MN, MP, MX power transistors

R1～R6 resistance

Detailed ways

FIG. 2 shows a block diagram of a low dropout voltage regulator 200 incorporating an embodiment of the present invention. The LDO 200 includes a first input terminal electrically connected to a DC voltage source VCC, a second input terminal electrically connected to a DC voltage source VH, and an output terminal for providing a DC output voltage VOUT. The low dropout voltage regulator 20 further includes an amplifying unit 22 , a transconducting unit 24 , a current replicating unit 26 , a resistor R1 , a resistor R2 and a resistor R3 . The amplifying unit 22 is used for receiving a reference voltage VREF and a feedback voltage FB, so as to generate the DC output voltage VOUT to the output terminal. The transduction unit 24 is electrically connected to the DC voltage source VCC for generating a current I1 according to the reference voltage VREF. The resistor R1 is used to receive the current I1 to generate the reference voltage VREF.

The current replication unit 26 is electrically connected to the DC voltage source VH for generating a current I2 and a current I3 according to the feedback voltage FB. The resistor R2 is used to receive the current I2 to generate the feedback voltage FB. The resistor R3 is electrically connected between the current replication unit 26 and the amplification unit 22 . The resistor R3 is used to receive the current I3 to generate the DC output voltage VOUT.

FIG. 3 shows a schematic circuit diagram of an LDO regulator 20 according to an embodiment of the present invention. Referring to FIG. 3 , the amplifying unit 22 includes an operational amplifier 224 and a power transistor MX. The drain of the power transistor MX is electrically connected to the output terminal of the low dropout voltage regulator 20 . The positive input terminal of the operational amplifier 224 is used to receive the reference voltage VREF, and the negative input terminal is used to receive the feedback voltage. After the operational amplifier 224 amplifies the voltage difference between the reference voltage VREF and the feedback voltage FB, an output signal is generated at its output end to a gate of the power transistor MX to drive the power transistor MX.

As shown in FIG. 3 , the transduction unit 24 includes a resistor R4 and transistors M1 and M2 connected in series. The resistor R4 is electrically connected to the DC voltage source VCC. The source of the transistor M1 is electrically connected to the resistor R4, and the gate is used to receive the reference voltage VREF. The source of the transistor M2 is electrically connected to the drain of the transistor M1 , its gate is used to receive a bias voltage VB2 , and its drain is connected to the positive input terminal of the operational amplifier 224 .

As shown in FIG. 3 , the current replication unit 26 includes a resistor R5 , a resistor R6 , transistors M3 and M4 connected in series, and transistors M5 and M6 connected in series. The resistor R5 is electrically connected to the DC voltage source VH. The source of the transistor M3 is electrically connected to the resistor R5. The source of the transistor M4 is electrically connected to the drain of the transistor M3 , the gate is used to receive a bias voltage VB1 , and the drain is connected to the negative input terminal of the operational amplifier 224 . The resistor R6 is electrically connected to the DC voltage source VH. The source of the transistor M5 is electrically connected to the resistor R6, and the gate is electrically connected to the gate of the transistor M3. The source of the transistor M6 is electrically connected to the drain of the transistor M5 , its gate is used to receive the bias voltage VB1 , and its drain is electrically connected to the gate of the transistor M3 and the resistor R3 .

In order to enable those skilled in the art to implement the present invention through the teaching of this embodiment example, the operation method of the LDO voltage regulator 200 of the present invention will be described below with reference to FIG. 3 . As shown in FIG. 3, since the input current flowing into the operational amplifier 224 is substantially close to zero, the total voltage drop of the components in the path where the current I1 flows can be expressed as:

VCC-I1×(R4+R1)-∣VSG(M1)∣=0 (1)

Wherein, |VSG(M1)| is the voltage difference between the source and the gate of the transistor M1.

Referring to FIG. 3, the amplifying unit 22, the transconducting unit 24 and the current duplication unit 26 form a negative feedback loop, so that the positive input terminal voltage VREF of the operational amplifier 224 is substantially the same as the negative input terminal of the operational amplifier 224. Voltage FB. Therefore, when the resistance values of the resistor R1 and the resistor R2 are selected to be the same, the current I2 will be substantially the same as the current I1.

In the current replication unit 26, if the resistance values of the resistor R5 and the resistor R6 are selected to be the same, and the size of the transistor M3 is the same as that of the transistor M5, since the gates of these PMOS transistors M3 and M5 are connected to each other, the current flows through the PMOS transistor The current I2 of M3 is substantially the same as the current I3 flowing through the PMOS transistor M5. In an embodiment of the present invention, the sizes of the PMOS transistors M4 and M6 are the same, and their gates both receive a bias voltage VB1 . The design of the bias voltage VB1 is to make the PMOS transistors M4 and M6 work in the saturation region, so as to further strengthen the matching degree between the current I2 and the current I3.

Therefore, the current I1 flowing through the transconducting unit 24 and the currents I2 and I3 flowing through the current replicating unit 26 are substantially the same through the selection of the resistance value and the size of the transistor. The total voltage drop of the components in the current I3 flow path can be expressed as:

VH-I3×(R6+R3)-∣VSG(M5)∣＝VOUT (2)

Wherein, |VSG(M5)| is the voltage difference between the source and the gate of the transistor M5.

Since the current I3 is substantially the same as the current I1, and the size of the transistor M5 is designed to be the same as that of the transistor M1, therefore |VSG(M5)| is substantially the same as |VSG(M1)|. Therefore, equation (2) can be replaced by:

VH-I1×(R6+R3)-∣VSG(M1)∣＝VOUT (3)

When the resistance values of resistor R6 and resistor R4 are selected to be the same, and the resistance values of resistor R3 and resistor R1 are selected to be the same, equation (3) can be replaced as:

VH-I1×(R4+R1)-∣VSG(M1)∣＝VOUT (4)

After putting equation (1) into equation (4), it can be rearranged as:

VH-VCC=VOUT (5)

According to equation (5), the voltage value of the DC output voltage VOUT can be obtained as the voltage difference between the DC voltage source VH and the DC voltage source VCC.

In application, the low dropout voltage regulator 200 of the present invention can be used as a bias circuit for driving a voltage level shifter of an output stage. FIG. 4 shows a block diagram of an output buffer (outputbuffer) 400 according to an embodiment of the present invention. Referring to FIG. 4 , the output buffer 400 includes an output stage 42 , voltage level shifters 44 and 46 and the LDO regulator 200 . The output stage 42 includes a PMOS transistor MP and an NMOS transistor MN. The source of the PMOS transistor MP is electrically connected to the DC voltage source VH, and the source of the NMOS transistor MN is electrically connected to the ground terminal.

The voltage level shifter 44 is used for receiving the input signal IN with a voltage amplitude from VCC to 0V, so as to drive the NMOS transistor MN. The voltage level shifter 46 is used for receiving the input signal IN with a voltage amplitude from VH to VH-VCC, so as to drive the PMOS transistor MP. In this example, the voltage level of the DC voltage source VH is higher than the voltage level of the DC voltage source VCC. For example, the voltage level of the DC voltage source VH can be 12V, and the voltage level of the DC voltage source VCC can be 5V.

In operation, when the input signal IN is logic 0 (0V in this example), the voltage level shifter 44 outputs a logic 1 signal (5V in this example), so that the NMOS transistor MN is turned on. At the same time, the voltage level shifter 46 outputs a logic 1 signal (12V in this example), so that the PMOS transistor MP is turned off. Therefore, the output buffer 400 can output a logic 0 signal.

On the contrary, when the input signal IN is logic 1 (5V in this example), the voltage level shifter 44 outputs a logic 0 signal (0V in this example), so that the NMOS transistor MN is turned off. At the same time, the voltage level shifter 46 outputs a logic 0 signal (7V in this example), so that the PMOS transistor MP is turned on. Therefore, the output buffer 400 can output a logic 1 signal, but the voltage level has been converted from 5V to 12V.

When the input signal IN is converted from a logic 0 signal to a logic 1 signal, the voltage level shifter 46 has to pull down the output signal V1 from the amplitude VH to VH-VCC. Therefore, the LDO voltage regulator 200 can provide a sink current IS through the NMOS transistor MX therein (refer to FIG. 3 ), so as to pull down the voltage level of V1. Due to the negative feedback loop formed by the amplifying unit 22, the transconducting unit 24 and the current replicating unit 26, the low dropout voltage regulator 200 can effectively control the output voltage VOUT to be the relationship between the DC voltage source VH and the DC voltage source VCC. voltage difference.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the content disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the appended claims.

Claims (10)

1. A low dropout regulator comprising: a first input terminal electrically connected to a first DC voltage source; a second input terminal electrically connected to a second DC voltage source; an output terminal for generating a DC output voltage; An amplifying unit, which is used to receive a reference voltage and a feedback voltage to generate a DC output voltage to the output terminal; a transconductance unit electrically connected to the first input terminal, the transconductance unit is used to generate a first current according to the reference voltage; a first resistor for receiving the first current to generate the reference voltage; a current replication unit, electrically connected to the second input terminal, the current replication unit is used to generate a second current and a third current according to the feedback voltage; a second resistor for receiving the second current to generate the feedback voltage; and a third resistor electrically connected between the current replication unit and the output terminal, the third resistor is used to receive the third current to generate the DC output voltage; Wherein, the voltage value of the second DC voltage source is greater than the voltage value of the first DC voltage source. 2. The low dropout voltage regulator according to claim 1, wherein the amplifying unit comprises: a power transistor, the drain of which is electrically connected to the output terminal; and An operational amplifier is used for receiving the reference voltage and the feedback voltage to drive a gate of the power transistor. 3. The low dropout voltage regulator according to claim 1, wherein the transduction unit comprises: a fourth resistor electrically connected to the first input terminal; a first transistor, the source of which is electrically connected to the fourth resistor, and the gate of which is electrically connected to the first resistor; and A second transistor, its source is electrically connected to a drain of the first transistor, its gate is used to receive a first bias voltage, and its drain is electrically connected to the first resistor. 4. The low dropout voltage regulator according to claim 3, wherein the current replica unit comprises: a fifth resistor electrically connected to the second input terminal; a third transistor, the source of which is electrically connected to the fifth resistor; a fourth transistor whose source is electrically connected to a drain of the third transistor, and whose drain is electrically connected to the second resistor, and whose gate receives a second bias voltage; a sixth resistor electrically connected to the second input terminal; a fifth transistor, the source of which is electrically connected to the sixth resistor, and the gate of which is electrically connected to a gate of the third transistor; and A sixth transistor, its source is electrically connected to a drain of the fifth transistor, and its drain is electrically connected to the third resistor and the gate of the third transistor, and its gate receives the second bias voltage Voltage. 5. The low dropout voltage regulator according to claim 4, wherein resistance values of the first resistor, the second resistor and the third resistor are substantially the same. 6. The low dropout voltage regulator according to claim 5, wherein the resistance values of the fourth resistor in the transduction unit and the fifth resistor and the sixth resistor in the current replication unit are substantially the same, and the transduction unit The size of the first transistor in the conduction unit and the third transistor and the fifth transistor in the current replication unit are substantially the same. 7. The low dropout voltage regulator according to claim 6, wherein the currents flowing through the first resistor, the second resistor and the third resistor are substantially the same. 8. The low dropout voltage regulator according to claim 7, wherein the voltage value of the DC output voltage is substantially equal to the voltage value of the second DC voltage source minus the voltage value of the first DC voltage source. 9. An output buffer comprising: The low dropout voltage regulator according to claim 1, which is electrically connected to the first DC voltage source and the second DC voltage source, the low dropout voltage regulator is used to generate the DC output voltage, the voltage value of which is substantially equal to the second DC voltage source subtracting the voltage value of the first DC voltage source from the voltage value of the DC voltage source; a voltage level shifter powered by the second DC voltage source and the output of the low dropout regulator; and The source of the output transistor is electrically connected to the second DC voltage source, its gate is electrically connected to the voltage level shifter, and its drain is electrically connected to the output terminal of the output buffer. 10. The output buffer according to claim 9, wherein currents flowing through the first resistor, the second resistor and the third resistor are substantially the same.