CN106257689B

CN106257689B - Semiconductor device and method of manufacturing the same

Info

Publication number: CN106257689B
Application number: CN201610424289.9A
Authority: CN
Inventors: 李厚容; 金完敦; 宋在烈; 玄尚镇
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2015-06-16
Filing date: 2016-06-15
Publication date: 2021-05-18
Anticipated expiration: 2036-06-15
Also published as: CN106257689A; US20160372382A1; KR20160148795A

Abstract

A semiconductor device includes an active patterned gate structure through a substrate. The semiconductor device may include a gate dielectric pattern between the substrate and the gate electrode. The gate structure includes a gate electrode, a capping pattern on the gate electrode, and one or more low-k dielectric layers at least partially covering one or more sidewalls of the capping pattern. The gate structure may include spacers at opposite sidewalls of the gate electrode and a separate low-k dielectric layer between the capping pattern and the spacers. A width of the capping pattern may be smaller than a width of the gate electrode. The capping pattern has a first dielectric constant, and the one or more low-k dielectric layers have a second dielectric constant. The second dielectric constant is smaller than the first dielectric constant. The second dielectric constant may be greater than or equal to one.

Description

Semiconductor device and method for manufacturing the same

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2015-0085210, filed by the korean intellectual property office at 16.6.2015, the entire disclosure of which is incorporated herein by reference.

Technical Field

Example embodiments of the present inventive concept relate to a semiconductor device and/or a method of manufacturing the same, and particularly, to a semiconductor device having a field effect transistor and/or a method of manufacturing the same.

Background

Due to the small size and the characteristics of multifunction and/or low cost, semiconductor devices are widely used as important components in the electronics industry. The semiconductor device may be classified into at least one of a memory device for storing data, a logic device for processing data, and a hybrid device including both a memory element and a logic element. In some cases, in order to enable electronic devices to have fast and/or low power consumption, the complexity and/or integration density of semiconductor devices is increased to provide semiconductor devices having high reliability, high performance, and/or multiple functions.

Disclosure of Invention

Example embodiments of the inventive concepts provide a semiconductor device in which a field effect transistor having improved electrical characteristics is provided.

Some example embodiments of the inventive concepts provide a method of manufacturing a semiconductor device in which a field effect transistor having improved electrical performance is provided.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate including an active pattern; and a gate structure passing through the active pattern. The gate structure may include: a gate electrode; a cap pattern on the gate electrode; spacers extending parallel to opposite sidewalls of the gate electrode; and a low-k dielectric layer between the cap pattern and the spacer. The cap pattern may have a first dielectric constant, and the low-k dielectric layer may have a second dielectric constant. A bottom surface of each low-k dielectric layer may be located at a higher level than a bottom surface of the gate electrode, and the second dielectric constant may be greater than or equal to 1 and may be less than the first dielectric constant.

In some example embodiments, the semiconductor device may further include an interlayer insulating layer covering the gate structure. Each low-k dielectric layer may be surrounded by the interlayer insulating layer, a separate spacer of the spacers, the cap pattern, and the gate electrode.

In some example embodiments, each low-k dielectric layer may be in direct contact with separate ones of the cap patterns and the spacers.

In some example embodiments, the cap pattern, the spacer, and the low-k dielectric layer may have coplanar top surfaces.

In some example embodiments, the gate structure may further include a gate dielectric pattern between the substrate and the gate electrode, the gate dielectric pattern may include a first extension portion extending in a direction perpendicular to a top surface of the substrate, and the gate electrode may cover a top surface of the first extension portion.

In some example embodiments, the gate structure may further include a barrier pattern between the substrate and the gate electrode, the barrier pattern may include a second extension portion extending in a direction perpendicular to a top surface of the substrate, and the gate electrode may cover a top surface of the second extension portion.

In some example embodiments, the barrier pattern may include a first barrier layer and a second barrier layer sequentially stacked on the substrate, and the first barrier layer and the second barrier layer may include different materials.

In some example embodiments, a width of an upper portion of the gate electrode may be greater than a width of a lower portion of the gate electrode.

In some example embodiments, the gate electrode may include a first work function metal pattern and an electrode pattern on an upper portion of the first work function metal pattern, and a width of the electrode pattern may be smaller than a width of the upper portion of the first work function metal pattern.

In some example embodiments, the low-k dielectric layer may cover opposite sidewalls of the electrode pattern and a portion of a top surface of the first work function metal pattern.

In some example embodiments, a width of the electrode pattern may be substantially equal to a width of the cover pattern.

In some example embodiments, the gate electrode may include a first work function metal pattern and an electrode pattern on the first work function metal pattern, and a width of the electrode pattern may be greater than a width of the cover pattern.

In some example embodiments, the top surface of the electrode pattern may be located at a higher level than the bottom surface of the cap pattern.

In some example embodiments, the gate electrode may include a first work function metal pattern, a second work function metal pattern, and an electrode pattern on the first work function metal pattern and the second work function metal pattern, and a top surface of the first work function metal pattern may be coplanar with a top surface of the second work function metal pattern.

In some example embodiments, the first work function metal pattern may have a first resistance, the second work function metal pattern may have a second resistance, and the electrode pattern may have a third resistance. The second resistance may be less than the first resistance and greater than the third resistance.

In some example embodiments, the low-k dielectric layer may include at least one of a gaseous material and a silicon oxide material.

In some example embodiments, the semiconductor device may further include a device isolation layer disposed in the substrate to define the active pattern. The active pattern may include an upper portion protruding between the device isolation layers.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate including an active pattern; and a gate structure passing through the active pattern. The gate structure may include: a gate electrode; a cap pattern on the gate electrode; and a low-k dielectric layer covering both sidewalls of the cap pattern. The width of the cap pattern may be smaller than the width of the gate electrode, and the dielectric constant of the low-k dielectric layer may be in a range of 1 to 4. The gate electrode may have a first width, and the cap pattern may have a second width. The first width of the gate electrode may be a maximum width of the gate electrode.

In some example embodiments, the gate electrode may include a work function metal pattern and an electrode pattern on the work function metal pattern, and a width of an upper portion of the work function metal pattern may be greater than a width of a lower portion of the work function metal pattern.

In some example embodiments, the low-k dielectric layer may cover both sidewalls of the electrode pattern.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate; a device isolation layer in the substrate to define an active pattern; and a gate structure passing through the active pattern. The gate structure may include: a gate electrode and a gate dielectric pattern between the substrate and the gate electrode. The gate dielectric pattern may include a first extension portion extending in a direction perpendicular to a top surface of the substrate, and the gate electrode may cover a top surface of the first extension portion.

In some example embodiments, the gate structure may further include a barrier pattern between the gate dielectric pattern and the gate electrode. The barrier pattern may include a second extension portion extending in a direction perpendicular to a top surface of the substrate, and the gate structure may be disposed to cover the top surface of the second extension portion.

According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: forming a device isolation layer in the substrate to define an active pattern; forming a sacrificial gate pattern through the active pattern and a set of spacers covering opposite sidewalls of the sacrificial gate pattern; removing the sacrificial gate pattern to form a gate trench defined by the spacer; forming a gate electrode and a cap pattern sequentially filling the gate trench; and recessing an upper portion of the gate electrode using the cap pattern as an etch mask to form a set of recessed regions exposing opposite sidewalls of the cap pattern.

In some example embodiments, the cap patterns may have a first dielectric constant, and the recess regions may be respectively filled with low-k dielectric layers having a second dielectric constant. The second dielectric constant may be greater than or equal to 1 and may be less than the first dielectric constant.

In some example embodiments, the low-k dielectric layer may include a gaseous material.

In some example embodiments, the method may further comprise the step of: an interlayer insulating layer covering the cap pattern is formed. The interlayer insulating layer may include silicon oxide. The interlayer insulating layer may at least partially fill the recessed region such that the low-k dielectric layer includes silicon oxide.

In some example embodiments, before forming the gate electrode, the method may further include the steps of: forming a gate dielectric layer to partially fill the gate trench, a portion of the gate dielectric layer covering the spacer; and partially removing the gate dielectric layer covering the spacers to form a gate dielectric pattern.

In some example embodiments, the forming of the gate electrode may include: forming a work function metal layer; recessing an upper portion of the work function metal layer to form a work function metal pattern; and forming an electrode pattern covering a top surface of the work function metal pattern.

In some example embodiments, a semiconductor device includes: a substrate including an active pattern; and a gate structure passing through the active pattern. The gate structure may include: a gate electrode; a cap pattern on the gate electrode, the cap pattern having a first dielectric constant; and a low-k dielectric layer at least partially covering sidewalls of the cap pattern, the low-k dielectric layer having a second dielectric constant, the second dielectric constant being less than the first dielectric constant.

In some example embodiments, the gate electrode includes an extension portion covering a lower portion of a sidewall of the cap pattern.

In some example embodiments, the low-k dielectric layer includes a first portion and a second portion, the first portion and the second portion including different materials.

In some example embodiments, the first portion covers an upper portion of the sidewall and the second portion covers a lower portion of the sidewall.

In some example embodiments, the semiconductor device further includes an interlayer insulating layer covering the gate structure, wherein the first portion of the low-k dielectric layer is an extension of the interlayer insulating layer.

Drawings

Example embodiments will be more clearly understood from the following brief description in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments described herein.

Fig. 1 is a plan view schematically illustrating a semiconductor device according to some example embodiments of the inventive concept.

Fig. 2 is a plan view illustrating a portion of a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 3A is a sectional view taken along lines I-I 'and II-II' of fig. 2.

Fig. 3B is a sectional view taken along line III-III' of fig. 2.

Fig. 4A, 4B, 4C, and 4D are enlarged cross-sectional views illustrating a gate structure (e.g., of portion M of fig. 3B) according to some example embodiments of the inventive concept.

Fig. 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

Fig. 15 is a block diagram illustrating an example of an electronic system including a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 16 is a block diagram illustrating an example of an electronic device including a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 17 is an equivalent circuit diagram illustrating an SRAM cell according to some example embodiments of the inventive concepts.

Fig. 18, 19 and 20 are diagrams illustrating some examples of a multimedia device including a semiconductor device according to some example embodiments of the inventive concepts.

It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures and/or materials utilized in some example embodiments, and to supplement the written description provided below. The drawings are not necessarily to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or attributes encompassed by the example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the figures is intended to indicate the presence of similar or identical elements or features.

Detailed Description

Some example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. Some example embodiments of the inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. The same reference numerals in the drawings denote the same elements, and thus the description thereof will be omitted.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

Spatially relative terms such as "below … …," "below … …," "lower," "above … …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as shown. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both orientations of "above … …" and "below … …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "… …," "includes" and/or "including … …," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments of the present inventive concept are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the example embodiments. Thus, various changes to the shape of the illustrations, for example, due to manufacturing techniques and/or tolerances, are contemplated. Accordingly, example embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concept belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to fig. 1, a semiconductor device according to some example embodiments of the inventive concepts may include a plurality of logic cells C1, C2, C3, and C4 disposed on a substrate 100. Each of the logic cells C1, C2, C3, and C4 may include a plurality of transistors. As an example, the semiconductor device may include a first logic cell C1, a second logic cell C2 spaced apart from the first logic cell C1 in a first direction D1, a third logic cell C3 spaced apart from the first logic cell C1 in a second direction D2 crossing the first direction D1, and a fourth logic cell C4 spaced apart from the second logic cell C2 in the second direction D2. Each of the logic cells C1, C2, C3, and C4 may include a plurality of active regions separated from each other by a device isolation layer 104. Each of the logic cells C1, C2, C3, and C4 may include a PMOSFET region PR and an NMOSFET region NR separated from each other by a device isolation layer 104.

As an example, the PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1. The PMOSFET region PR of the first logic cell C1 may be disposed adjacent to the PMOSFET region PR of the second logic cell C2 in the first direction D1. In the following description, the term "logic unit" may refer to a unit circuit configured to perform a single logic operation. Furthermore, the number of logic cells may be different from that shown in the figures.

Fig. 2 is a plan view illustrating a portion of a semiconductor device according to some example embodiments of the inventive concepts. For example, fig. 2 is a plan view illustrating the first logic unit C1 of fig. 1. Hereinafter, various example embodiments of the inventive concept will be described with reference to the first logic cell C1 of fig. 1, but some logic cells may have substantially the same or similar structure as the first logic cell C1. Fig. 3A is a sectional view taken along lines I-I 'and II-II' of fig. 2. Fig. 3B is a sectional view taken along line III-III' of fig. 2.

Referring to fig. 2, 3A and 3B, a device isolation layer 104 may be disposed in the substrate 100 to define a PMOSFET region PR and an NMOSFET region NR. A device isolation layer 104 may be formed in the top of the substrate 100. In some example embodiments, device isolation layer 104 may include an insulating material, such as silicon oxide.

The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1 parallel to the top surface of the substrate 100 by the device isolation layer 104 interposed therebetween. Although each of the PMOSFET region PR and the NMOSFET region NR is illustrated as a single region, it may include a plurality of regions separated from each other by the device isolation layer 104.

A plurality of active patterns AP may be disposed on the PMOSFET region PR and the NMOSFET region NR to extend in a second direction D2 crossing the first direction D1. The active patterns AP may be arranged along the first direction D1. The active pattern AP may have a first conductive type. The device isolation layer 104 may be disposed at both sides of each active pattern AP to define the active pattern AP. Although the number of active patterns AP disposed on each of the PMOSFET region PR and the NMOSFET region NR is illustrated as three, example embodiments of the inventive concept are not limited thereto.

Each of the active patterns AP may include active fins AF protruding between the device isolation layers 104. For example, each active fin AF may have a structure protruding from the active pattern AP in a third direction D3 perpendicular to the top surface of the substrate. Each active fin AF may include source/drain SD and a channel region CHR interposed between the source/drain SD.

In some example embodiments, the gate structure GS may be disposed on the substrate 100 to intersect the active pattern AP. The gate structures GS may overlap the channel regions CHR of the active fins AF, respectively, when viewed in a plan view. In other words, the gate structure GS may be disposed to cross the active fin AF and extend parallel to the first direction D1, and may be a line-shaped structure. Each gate structure GS may include a gate spacer 125, a gate dielectric pattern 131, a barrier pattern 133, a gate electrode 135, a cap pattern 145, and one or more low-k dielectric layers 143 between the cap pattern 145 and the separated gate spacer 125. The gate structure GS will be described in more detail below.

The source/drain electrodes SD may be disposed on or in the active fin AF and disposed at both sides of each gate structure GS. The source/drain electrodes SD may be epitaxial patterns epitaxially grown from the active patterns AP. In some example embodiments, the top surface of the channel region CHR may be located at a higher level than the bottom surface of the source/drain SD when viewed in a vertical sectional view. In some example embodiments, the top surface of the source/drain SD may be located at the same level as or higher than the top surface of the channel region CHR.

The source/drain electrodes SD may include a semiconductor element different from that of the substrate 100. For example, the source/drain SD may be formed of or include a semiconductor material having a different (e.g., greater or less) lattice constant than the substrate 100. Accordingly, a compressive stress or a tensile stress may be applied to the channel region CHR. In some example embodiments, the substrate 100 is a silicon wafer and the source/drain electrodes SD may be formed of or include a silicon germanium (e.g., e-SiGe) layer or a germanium layer. In this case, the source/drain SD may exert a compressive stress on the channel region CHR (of the PMOS field effect transistor, preferably). In some example embodiments, the substrate 100 is a silicon wafer and the source/drain electrodes SD may be formed of or include a silicon carbide (SiC) layer. In this case, the source/drain SD may exert a tensile stress on the channel region CHR (of the NMOS field effect transistor, preferably). When the field effect transistor operates, the compressive stress or the tensile stress to be exerted on the channel region CHR by the source/drain SD may increase the mobility of carriers in the channel region CHR. The source/drain electrodes SD may have a second conductive type different from that of the active pattern AP.

The first interlayer insulating layer 150 may be disposed on the substrate 100. The first interlayer insulating layer 150 may be disposed to cover sidewalls of the source/drain electrodes SD and the gate structure GS. A top surface of the first interlayer insulating layer 150 may be substantially coplanar with a top surface of the gate structure GS. A second interlayer insulating layer 155 may be formed on the first interlayer insulating layer 150 to cover the gate structure GS.

In addition, contacts CA may be disposed at both sides of each gate electrode 135 and may be electrically connected to the source/drain electrodes SD through the first and second

interlayer insulating layers

150 and 155. Each contact CA may be connected to a corresponding one or more source/drains SD, but example embodiments of the inventive concept are not limited thereto. Each contact CA may include a conductive pillar CP and a contact barrier layer BL surrounding the conductive pillar CP. The contact barrier layer BL may be disposed to cover side and bottom surfaces of the conductive pillar CP. The conductive pillar CP may be formed of or include a metal material (e.g., tungsten). The contact barrier layer BL may be formed of or include at least one metal nitride (e.g., Ti/TiN).

Although not shown, metal silicide layers may be interposed between the source/drain electrodes SD and the contacts CA, respectively. For example, the contact CA may be electrically connected to the source/drain SD through a metal silicide layer. The metal silicide layer SC may be formed of or include at least one metal silicide material (e.g., titanium silicide, tantalum silicide, or tungsten silicide).

The gate contact CB and the wire CBL may be disposed on one gate electrode 135. The first via V1 may be disposed between the gate contact CB and the wire CBL. The wire CBL may be electrically connected to the one gate electrode 135 through the first via hole V1 and the gate contact CB to serve as a current path for applying a signal to the one gate electrode 135.

The first logic cell C1 may include a first conductive line PW1 disposed near an outer edge of the PMOSFET region PR and a second conductive line PW2 disposed near an outer edge of the NMOSFET region NR. As an example, the first conductor PW1 on the PMOSFET region PR may act on a current path that transmits a drain voltage Vdd (e.g., a power voltage). The second conductor PW2 on the NMOSFET region NR may serve as a current path for transmitting the source voltage Vss (e.g., ground voltage).

Referring back to fig. 1 and 2, the first wire PW1 and the second wire PW2 may extend parallel to the second direction D2, and the first wire PW1 and the second wire PW2 may be shared by a plurality of logic cells arranged adjacent to each other in the second direction D2. As an example, the first conductor PW1 may be shared by the first logic cell C1 and the third logic cell C3. In addition, the first conductive line PW1 may be shared by the PMOSFET regions PR of the first logic cell C1 and the second logic cell C2.

In some example embodiments, the second through hole V2 may be provided on one contact CA. Accordingly, the source/drain SD connected to the one contact CA may be electrically connected to the first wire PW1 through the one contact CA and the second via V2. Similarly, the source/drain SD on the NMOSFET region NR may also be electrically connected to the second wire PW2 through one contact CA and the third via V3.

Fig. 4A, 4B, 4C, and 4D are enlarged cross-sectional views illustrating some examples of the gate structure GS (e.g., of the portion M of fig. 3B) according to some example embodiments of the inventive concept. The gate structure GS according to some example embodiments of the inventive concept will be described in more detail with reference to fig. 4A, 4B, 4C, and 4D.

In some example embodiments, as shown in fig. 2, 3A, 3B, and 4A, the gate electrode 135 may have a line-shaped structure crossing the active pattern AP and extending in the first direction D1. For example, the gate electrode 135 may include a work function metal pattern WF and an electrode pattern EP on the work function metal pattern WR.

A set of gate spacers 125 may be disposed on opposing sidewalls of the gate electrode 135. It should be understood that the set of gate spacers 125 may include a pair of gate spacers 125 disposed on opposing sidewalls of the gate electrode 135. The gate spacers 125 may extend along the gate electrode 135 in parallel with at least opposite sidewalls of the cap pattern 145 or along the gate electrode 135 in the first direction D1. The top surface of each gate spacer 125 may be located at a higher level than the top surface of the gate electrode 135. In addition, each gate spacerThe top surface of 125 may be coplanar with the top surface of the first interlayer insulating layer 150. The gate spacers 125 may comprise SiO₂At least one of SiCN, SiCON or SiN. Alternatively, the gate spacer 125 may have a structure including SiO₂A multilayer structure of at least one of SiCN, SiCON or SiN.

The gate dielectric pattern 131 may be disposed between the gate electrode 135 and the substrate 100 and between the gate electrode 135 and the gate spacer 125. The gate dielectric pattern 131 may extend along a bottom surface of the gate electrode 135. For example, as shown in fig. 3A, the gate dielectric pattern 131 may be disposed to cover the top surface and the side surface of the channel region CHR. The gate dielectric pattern 131 may horizontally extend from the active fin AF to partially cover the top surface of the device isolation layer 104. In some example embodiments, the gate dielectric pattern 131 may be disposed to partially expose a top surface of the device isolation layer 104. The exposed portion of the top surface of the device isolation layer 104 may be covered with a first interlayer insulating layer 150 (e.g., see a cross section taken along line II-II' of fig. 3A).

In addition, as shown in fig. 4A, the gate dielectric pattern 131 may include a pair of first extension portions 125E. The first extension portion 125E may extend in the third direction D3 along the inner sidewall of the gate spacer 125. The top surface of the first extension portion 125E may be covered with the work function metal pattern WR of the gate electrode 135. For example, the top surface of the first extension portion 125E may be located between the top surface and the bottom surface of the work function metal pattern WF.

The gate dielectric pattern 131 may include a high-k dielectric material. For example, the gate dielectric pattern 131 may be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

The barrier pattern 133 may be interposed between the gate electrode 135 and the gate dielectric pattern 131. The barrier pattern 133 may extend along the bottom surface of the gate electrode 135 together with the gate dielectric pattern 131. Referring back to fig. 4A, the barrier pattern 133 may include a pair of second extension portions 133E. The second extension part 133E may extend along an inner sidewall of the first extension part 125E in the third direction D3. The top surface of the second extension portion 133E may be substantially coplanar with the top surface of the first extension portion 125E. In addition, the top surface of the second extension portion 133E may be covered with the work function metal pattern WF. For example, the top surface of the second extension portion 133E may be located between the top surface and the bottom surface of the work function metal pattern WF.

In addition, the barrier pattern 133 may include a first barrier layer 133a and a second barrier layer 133b sequentially stacked on the substrate 100. The first barrier layer 133a may prevent diffusion of the metal element from the work function metal pattern WF to the gate dielectric pattern 131. The second barrier layer 133b may protect the first barrier layer 133a and the gate dielectric pattern 131 during the etching process. In some example embodiments, the barrier pattern 133 may further include a third barrier layer 133c interposed between the second barrier layer 133b and the work function metal pattern WF. The diffusion of the metal element contained in the work function metal pattern WF can be more effectively prevented by the third barrier layer 133 c.

The first barrier layer 133a, the second barrier layer 133b, and the third barrier layer 133c may include metal layers formed of the same material or different materials. As one example, the first, second, and

third barrier layers

133a, 133b, and 133c may include binary metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and hafnium nitride (HfN)) and/or ternary metal nitrides (e.g., titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), and hafnium aluminum nitride (HfAlN)). In some example embodiments, the first barrier layer 133a may be formed of or include a titanium nitride layer (TiN), the second barrier layer 133b may be formed of or include a tantalum nitride layer (TaN), and the third barrier layer 133c may be formed of or include a titanium nitride layer (TiN).

In some example embodiments, the barrier pattern 133 may not cover the top surface of the first extension portion 125E of the gate dielectric pattern 131. In other words, since the work function metal pattern WF is in direct contact with the top surface of the first extension portion 125E, the metal element in the work function metal pattern WF may be diffused into the first extension portion 125E. However, due to the presence of the barrier pattern 133, such a metal element may be prevented from being diffused into a portion of the gate dielectric pattern 131 interposed between the first extension portions 125E or located on the channel region CHR. Therefore, even when the metal element is diffused into the first extension portion 125E, the electric and physical characteristics of the field effect transistor can be prevented from being deteriorated.

The work function metal pattern WF may include a metal material for controlling a work function of the channel region CHR. For example, the work function metal pattern WF may be formed of a conductive material having a specific work function to help control a threshold voltage of the field effect transistor. For example, the work function metal pattern WF may have a work function between about 4.1eV to about 5.2 eV.

The work function metal pattern WF may include a lower portion having a first width W1 and an upper portion having a second width W2 as measured in the second direction D2. Here, the second width W2 may be greater than the first width W1. The second width W2 may be substantially equal to the distance between a pair of gate spacers 125. The work function metal pattern WF may have a width that discontinuously increases in a bottom-up direction of the work function metal pattern WF. The sidewalls of the work function metal pattern WF may have a stepped profile. An interface between the lower portion and the upper portion of the work function metal pattern WF may be located at substantially the same level as the top surfaces of the first and

second extension portions

125E and 133E. The work function metal pattern WF may have a substantially flat top surface.

The work function metal pattern WF may be formed of or include at least one of a metal, for example, titanium (Ti), tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), or aluminum (Al), a nitride, carbide, silicon nitride, or silicide containing at least one of the above metals. In some example embodiments, the work function metal pattern WF may be formed of or include platinum (Pt), rubidium (Ru), iridium oxide (IrO), or rubidium oxide (RuO).

In some example embodiments, the work function metal pattern WF on the PMOSFET region PR may contain a different material from the work function metal pattern WF on the NMOSFET region NR. This may make a difference between work functions of channel regions disposed on the PMOSFET region PR and the NMOSFET region NR. In some example embodiments, the work function metal pattern WF on the PMOSFET region PR may have a double-layered structure, as will be described in more detail below.

The electrode pattern EP on the work function metal pattern WF may have a third width W3. The third width W3 may be less than the second width W2. The electrode pattern EP may be formed of or include at least one low-resistance metal material, such as aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta). In general, the work function metal pattern WF may be formed of a material having a resistance much higher than that of the electrode pattern EP. Therefore, the use of the work function metal pattern WF may cause an increase in the resistance of the gate electrode 135 and deterioration of the AC performance of the field effect transistor. However, since the electrode pattern EP has a relatively low resistance, it is possible to reduce the overall resistance of the gate electrode 135 and improve the AC performance of the field effect transistor.

The cap pattern 145 may be disposed on the gate electrode 135. The cap pattern 145 may extend along the gate electrode 135 or in the first direction D1. The cover pattern 145 may have a fourth width W4, and the fourth width W4 may be less than the second width W2 and may be substantially equal to the third width W3. The top surface of the cap pattern 145 may be located at the same level as the top surface of the gate spacer 125.

The cap pattern 145 may include a material having an etch selectivity with respect to the first and second

interlayer insulating layers

150 and 155. For example, the cap pattern 145 may include at least one of SiON, SiCN, SiCON, and SiN. In addition, the cover pattern 145 may have a first dielectric constant.

A recess region RE may be defined between the cap pattern 145 and the gate spacer 125. For example, each of the recessed regions RE may be a blank region defined or surrounded by the work function metal pattern WF, the electrode pattern EP, the cap pattern 145, the second interlayer insulating layer 155, and the gate spacer 125. The top surface of the recess region RE may be located at substantially the same level as the top surfaces of the gate spacer 125 and the cap pattern 145.

The low-k dielectric layer 143 may be formed to fill the recessed region RE. Accordingly, the low-k dielectric layer 143 may cover opposite sidewalls of the cap pattern 145 and opposite sidewalls 192 of the electrode pattern EP. The low-k dielectric layer 143 may be disposed to partially cover the top surface of the work function metal pattern WF. As shown in fig. 4A, for example, the low-k dielectric layer 143 may cover the opposite sidewalls 192 of the electrode pattern EP in addition to the opposite sidewalls 191 of the cover pattern 145. The low-k dielectric layer 143 may be disposed to at least partially cover the inner sidewalls of the gate spacers 125.

The low-k dielectric layer 143 may have a second dielectric constant equal to or higher than 1 and lower than the first dielectric constant. In some example embodiments, the first dielectric constant may be in a range of 4 to 8, and the second dielectric constant may be in a range of 1 to 4. The low-k dielectric layer 143 may comprise a variety of low-k dielectric materials. The low-k dielectric materials may constitute a mixture or may be separated from each other. The low-k dielectric layer 143 may be formed of or include one or more of a gaseous material and a silicon oxide material. In some example embodiments, the low-k dielectric layer 143 may include one or more gaseous materials. Since the dielectric constant of the low-k dielectric layer 143 is lower than that of the cap pattern 145, the parasitic capacitance between the gate electrode 135 and the contact CA may be reduced relative to the parasitic capacitance between the gate electrode 135 and the contact CA in a semiconductor device lacking the dielectric layer 143.

Accordingly, in the gate structure GS according to some example embodiments, the electrode pattern EP may cause the resistance of the gate structure GS and the low-k dielectric layer 143 to be reduced. The electrode pattern EP may enable the parasitic capacitance of the gate structure GS to be reduced. AC performance and RC delay properties of the semiconductor device can be improved.

As another example, referring to fig. 2, 3A, 3B and 4B, the work function metal pattern WF may include a first work function metal pattern WFa and a second work function metal pattern WFb sequentially stacked on the substrate 100. Here, top surfaces of the first and second work function metal patterns WFa and WFb may be substantially coplanar with each other. The first and second work function metal patterns WFa and WFb may include different materials. For example, the first work function metal pattern WFa may have a first resistance, the second work function metal pattern WFb may have a second resistance, and the electrode pattern EP may have a third resistance. The second resistance may be less than the first resistance and greater than the third resistance. Accordingly, the resistance of the gate electrode 135 can be reduced to improve the AC performance of the semiconductor device.

In addition, since the work function metal pattern WF has a double-layer structure, the use of the work function metal pattern WF may be able to variously control the work function of the field effect transistor. For example, the gate structure GS of fig. 4B may be applied to the PMOSFET region PR, and the gate structure GS of fig. 4A may be applied to the NMOSFET region NR. Thus, the work function of each region can be adaptively controlled.

As another example, referring to fig. 2, 3A, 3B, and 4C, the electrode pattern EP may have a fifth width W5. The fifth width W5 may be greater than the fourth width W4 and may be substantially equal to the second width W2.

The electrode pattern EP may include a pair of third extension portions EPE. The third extension portion EPE may extend along the inner sidewall of the gate spacer 125 in the third direction D3. For example, the third extension EPE may partially cover the sidewall of the cover pattern 145. As shown in fig. 4C, the third extension EPE may cover the lower portion 191b of the sidewall 191 of the cap pattern 145, and the low-k dielectric layer 143 may cover the upper portion 191a of the sidewall 191 of the cap pattern 145. The top surface of the third extension EPE may be located at a level higher than the bottom surface of the cap pattern 145. The bottom surface of the recessed region RE may be located at substantially the same level as the top surface of the third extension EPE. Accordingly, the top surface of the third extension EPE may be in direct contact with the low-k dielectric layer 143.

As another example, referring to fig. 2, 3A, 3B, and 4D, the electrode pattern EP may have a sixth width W6, and the cover pattern 145 may have a seventh width W7. The sixth width W6 may be less than the third width W3 described with reference to fig. 4A, and the seventh width W7 may be less than the fourth width W4 described with reference to fig. 4A.

As shown in fig. 4D, the low-k dielectric layer 143 may include a first portion 143a and a second portion 143 b. The first portion 143a may be or may include a gaseous material, and the second portion 143b may be or may include a silicon oxide material. In some example embodiments, the low-k dielectric layer 143 may include a gaseous material and a silicon oxide material sequentially stacked. As shown in fig. 4D, the second portion 143b of the low-k dielectric layer 143 may cover the upper portion 191a of the sidewall 191 of the cap pattern 145. The first portion 143a of the low-k dielectric layer 143 may cover the lower portion 191b of the sidewall 191 of the cap pattern and the sidewall 192 of the electrode pattern EP. In some example embodiments, the second portion 143b of the low-k dielectric layer 143 may cover the sidewall 191 of the cap pattern 145 and a first portion of the sidewall 192 of the electrode pattern EP, and the first portion 143a of the low-k dielectric layer 143 may cover a second portion of the sidewall 192 of the electrode pattern EP. The second portion 143b of the low-k dielectric layer 143, in combination with the second interlayer insulating layer 155, may constitute a single body. In other words, the second portion 143b of the low-k dielectric layer 143 may also be a portion of the second interlayer insulating layer 155 extending into the recessed region RE. This is because, when the sixth width W6 and the seventh width W7 are decreased, the width of the recessed region RE may be increased, and in this case, the recessed region RE may be partially filled with silicon oxide in the process of forming the second interlayer insulating layer 155. As described above, the second portion 143b of the low-k dielectric layer 143, in combination with the second interlayer insulating layer 155, may form a single body, but since the second portion 143b of the low-k dielectric layer 143 is located in the recessed region RE, the second portion 143b of the low-k dielectric layer 143 may be included in one or more low-k dielectric layers 143 according to some example embodiments.

Fig. 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. Fig. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A are sectional views taken along lines I-I 'and II-II' of fig. 2. Fig. 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are sectional views taken along a line III-III' of fig. 2.

Referring to fig. 2, 5A and 5B, the substrate 100 may be patterned to form device isolation trenches 105 defining the active pattern AP. The substrate 100 may be a semiconductor substrate (e.g., of silicon, germanium, or silicon germanium) or a compound semiconductor substrate. The active pattern AP may be doped with impurities to have the first conductive type.

The forming of the device isolation trench 105 may include: a mask pattern is formed on the substrate 100, and the substrate 100 is anisotropically etched using the mask pattern as an etching mask. Each mask pattern may include a first mask pattern 110 and a second mask pattern 115 sequentially stacked on the substrate 100 and formed to have an etch selectivity with respect to each other. Each device isolation trench 105 may be formed to have an aspect ratio of at least 5. In some example embodiments, each device isolation trench 105 may be formed to have a downward taper. Accordingly, each active pattern AP may be formed to have an upward taper.

Referring to fig. 2, 6A and 6B, a device isolation layer 104 may be formed to fill the device isolation trench 105. The forming of the device isolation layer 104 may include: forming an insulating layer (e.g., a silicon oxide layer) to fill the device isolation trench 105; and planarizing the insulating layer to expose a top surface of the first mask pattern 110. As a result of the planarization process, a device isolation layer 104 may be locally formed in the device isolation trench 105.

Referring to fig. 2, 7A, and 7B, the top of the active pattern AP (hereinafter, active fin AF) may be exposed. The exposure of the active fin AF may include: the top of device isolation layer 104 is recessed using, for example, a wet etch process. The recess of the device isolation layer 104 may be performed using an etch recipe having etch selectivity with respect to the active pattern AP. The recess of the device isolation layer 104 may be performed to remove the first mask pattern 110 to expose the top surface of the active fin AF.

A sacrificial gate pattern 106 and a gate mask pattern 108, which are sequentially stacked, may be formed on the active fin AF. Each of the sacrificial gate pattern 106 and the gate mask pattern 108 may be formed to intersect the active fin AF or to have a line-shaped or stripe-shaped structure extending in the first direction D1. For example, the formation of the sacrificial gate pattern 106 and the gate mask pattern 108 may include: sequentially forming a sacrificial gate layer and a gate mask layer on the active fin AF and the device isolation layer 104; and patterning the sacrificial gate layer and the sacrificial mask layer. The sacrificial gate layer may be formed of or include a polysilicon layer. The gate mask layer may be formed of or include a silicon nitride layer or a silicon oxynitride layer.

Gate spacers 125 may be formed on both sidewalls of each sacrificial gate pattern 106. The formation of the gate spacers 125 may include: conformally forming a spacer layer on the resulting structure of the sacrificial gate pattern 106; and anisotropically etching the spacer layer. The spacer layer may be made of SiO₂At least one of SiCN, SiCON and SiN. Alternatively, the spacer layer may be formed to have a thickness including SiO₂A multilayer structure of at least one of SiCN, SiCON or SiN.

Referring to fig. 2, 8A and 8B, source/drain electrodes SD may be formed at both sides of each sacrificial gate pattern 106. For example, the source/drain SD may be formed by a selective epitaxial growth process using the substrate 100 as a seed layer. The selective epitaxial growth process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process. Specifically, the active fin AF may be selectively etched using the gate mask pattern 108 and the gate spacer 125 as an etch mask. After etching the active fin AF, an epitaxial process may be performed to form the source/drain electrodes SD, with the exposed top of the active pattern AP serving as a seed layer. As a result of forming the source/drain SD, a channel region CHR may be defined between the source/drain SD.

The top surface of the source/drain SD may be located at a level higher than the channel region CHR. Further, the top surface of the source/drain SD may have a non-zero curvature. For example, the top surface of each source/drain SD may have an upwardly convex profile.

The source/drain electrodes SD may include a semiconductor element different from that of the substrate 100. For example, the source/drain SD may be formed of or include a semiconductor material having a different (e.g., greater or less) lattice constant than the substrate 100. This may enable applying a compressive stress or a tensile stress to the channel region CHR. In the case where the substrate 100 is a silicon wafer, the source/drain electrodes SD may be formed of or include a silicon-germanium (e.g., e-SiGe) layer or a germanium layer. In this case, the source/drain SD may exert a compressive stress on the channel region CHR (of the PMOS field effect transistor, preferably). In the case where the substrate 100 is a silicon wafer, the source/drain electrodes SD may be formed of or include a silicon carbide (SiC) layer. In this case, the source/drain SD may exert a tensile stress on the channel region CHR (of the NMOS field effect transistor, preferably). When the field effect transistor according to some example embodiments of the inventive concepts is operated, compressive stress or tensile stress to be exerted on the channel region CHR by the source/drain SD may enable carriers in the channel region CHR to have increased mobility.

The source/drain electrodes SD may be doped to have a second conductive type different from the first conductive type of the active pattern AP. As an example, dopants may be implanted in an in-situ manner to achieve the second conductivity type of the source/drain SD. As another example, an ion implantation process may be performed after the source/drain SD is formed to realize the second conductive type of the source/drain SD.

Next, the first interlayer insulating layer 150 may be formed to cover the source/drain electrodes SD. For example, the forming of the first interlayer insulating layer 150 may include: an insulating layer is formed on the substrate 100 to cover the sacrificial gate pattern 106 and the gate mask pattern 108. The first interlayer insulating layer 150 may include a silicon oxide layer, which may be formed by a Flow Chemical Vapor Deposition (FCVD) process.

Thereafter, the first interlayer insulating layer 150 may be planarized to expose the top surface of the sacrificial gate pattern 106. The planarization of the first interlayer insulating layer 150 may be performed using an etch-back process or a Chemical Mechanical Polishing (CMP) process. Planarization of the first interlayer insulating layer 150 may be performed to remove the gate mask pattern 108, thereby exposing the top surface of the sacrificial gate pattern 106. In addition, planarization of the first interlayer insulating layer 150 may be performed to remove an upper portion of the gate spacer 125. Accordingly, the first interlayer insulating layer 150 may have a top surface substantially coplanar with the sacrificial gate pattern 106 and the gate spacers 125.

The sacrificial gate pattern 106 may be removed to form the gate trench GT. The gate trench GT may be formed by an etching process that selectively removes the sacrificial gate pattern 106. The gate trench GT may expose the channel region CHR of the active fin AF.

Referring to fig. 2, 9A and 9B, a gate dielectric layer 131L, a barrier layer 133L and a dummy filler layer 113 may be sequentially formed to fill the gate trench GT. The gate dielectric layer 131L and the barrier layer 133L may be conformally formed to partially (but not completely) fill the gate trench GT.

The gate dielectric layer 131L may be formed by an Atomic Layer Deposition (ALD) process or a chemical oxidation process. The gate dielectric layer 131L may be formed of or include a high-k dielectric material. For example, the gate dielectric layer 131L may be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

The barrier layer 133L may be formed by an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process. As an example, barrier layer 133L may include binary metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and hafnium nitride (HfN)) and/or ternary metal nitrides (e.g., titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), and hafnium aluminum nitride (HfAlN)). The barrier layer 133L may include a plurality of different metal layers (see, for example, fig. 4A, 4B, 4C, and 4D), but example embodiments of the inventive concept are not limited thereto.

The dummy filler layer 113 may be formed to completely fill the remaining portion of the gate trench GT. In some example embodiments, the dummy filler layer 113 may include a carbon-containing organic compound. Here, the dummy filler layer 113 may be formed on the entire top surface of the substrate 100 through a transfer coating process. In some example embodiments, the dummy filler layer 113 may include a silicon oxide layer or a polysilicon layer. In the case where the dummy filler layer 113 includes a silicon oxide layer or a polysilicon layer, the dummy filler layer 113 may be formed by a Chemical Vapor Deposition (CVD) process.

Referring to fig. 2, 10A, and 10B, a planarization process may be performed on the gate dielectric layer 131L, the barrier layer 133L, and the dummy filler layer 113 to expose the first interlayer insulating layer 150. The planarization process may be performed using an etch-back or Chemical Mechanical Polishing (CMP) process. Accordingly, the gate dielectric layer 131L, the barrier layer 133L, and the dummy filler layer 113 may be located within the gate trench GT.

Referring to fig. 2, 11A, and 11B, upper portions of the gate dielectric layer 131L and the barrier layer 133L may be removed from a region between the gate spacer 125 and the dummy filler layer 113. For example, upper portions of the gate dielectric layer 131L and the barrier layer 133L may be etched using the gate spacers 125 and the dummy filler layer 113 as an etching mask to form the gate dielectric pattern 131 and the barrier pattern 133.

The gate dielectric pattern 131 may include a first extended portion 125E interposed between the gate spacer 125 and the dummy filler layer 113, and the barrier pattern 133 may include a second extended portion 133E interposed between the gate spacer 125 and the dummy filler layer 113 (see, for example, fig. 4A). A top surface of first extension 125E and a top surface of second extension 133E may be substantially coplanar with each other and located between the top and bottom surfaces of dummy filler layer 113.

Referring to fig. 2, 12A and 12B, the dummy filler layer 113 may be removed, and a work function metal pattern WF may be formed on the gate dielectric pattern 131 and the barrier pattern 133 to fill the gate trench GT. For example, the formation of the work function metal pattern WF may include: a work function metal layer is formed on the gate dielectric pattern 131 and the barrier pattern 133 to fill the gate trench GT, and then planarized to expose a top surface of the first interlayer insulating layer 150. Thereafter, the planarized upper portion of the work function metal layer may be selectively removed by an etching process. Accordingly, the work function metal pattern WF may be locally formed in each gate trench GT. The top surface of the work function metal pattern WF may be lower than the top surface of the first interlayer insulating layer 150. The work function metal pattern WF may be a line structure extending parallel to the first direction D1. The workfunction metal layer may be formed by a deposition process (e.g., a sputtering or CVD process).

The work function metal layer may be formed of or include at least one of a metal (e.g., titanium (Ti), tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), or aluminum (Al)), a nitride, carbide, silicon nitride, or silicide containing at least one metal. In some example embodiments, the work function metal pattern WF may be formed of or include platinum (Pt), rubidium (Ru), iridium oxide (IrO), or rubidium oxide (RuO). The work function metal layer may include a plurality of metal layers having work functions different from each other (e.g., see fig. 4B), but example embodiments of the inventive concept are not limited thereto.

Referring to fig. 2, 13A and 13B, an electrode pattern EP and a cap pattern 145 may be formed on the work function metal pattern WF to fill the gate trench GT, respectively. The work function metal pattern WF and the electrode pattern EP disposed in each gate trench GT may constitute the gate electrode 135. Specifically, an electrode metal layer may be formed on the work function metal pattern WF to partially fill the gate trench GT, and a capping layer may be formed on the electrode metal layer to fill the remaining region of the gate trench GT. Thereafter, the electrode metal layer and the cap layer may be planarized to expose the top surface of the first interlayer insulating layer 150, thereby forming an electrode pattern EP and a cap pattern 145.

The electrode metal layer may be formed through a deposition process, such as an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, or a sputtering process. The electrode metal layer may be formed of or include at least one low-resistance metal material, such as aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta).

The capping layer may be formed by an Atomic Layer Deposition (ALD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDCVD) process. The capping layer may be formed of a material having an etch selectivity with respect to the first and second

interlayer insulating layers

150 and 155. For example, the cap layer may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

Referring to fig. 2, 14A and 14B, the electrode pattern EP may be etched using the cap pattern 145 as an etching mask, and thus, a sidewall 191 recessed region RE of the cap pattern 145 may be formed to be exposed. Specifically, the etching of the electrode pattern EP may be performed by a wet or dry etching process using an etching selectivity of the electrode pattern EP with respect to the cap pattern 145, the gate spacer 125, and the first interlayer insulating layer 150. Accordingly, sidewall portions of the electrode pattern EP interposed between the cap pattern 145 and the gate spacer 125 may be removed to expose sidewalls 192 of the electrode pattern EP and form a recessed region RE between the cap pattern 145 and the gate spacer 125. Each recessed region RE may be a blank space defined or limited by the work function metal pattern WF, the electrode pattern EP, the cap pattern 145, and the gate spacer 125.

A low-k dielectric layer 143 may be formed to fill the recessed region RE. In this embodiment, the low-k dielectric layer 143 may be a gaseous material or air. The gate spacer 125, the gate dielectric pattern 131, the barrier pattern 133, the gate electrode 135, the cap pattern 145, and the low-k dielectric layer 143 may constitute a gate structure GS.

Referring to fig. 2, 3A and 3B, a second interlayer insulating layer 155 may be formed on the first interlayer insulating layer 150 and the gate structure GS. The second interlayer insulating layer 155 may be formed of or include a silicon oxide layer or a low-k oxide layer. The low-k oxide layer may include, for example, a carbon-doped silicon oxide layer (e.g., SiCOH). The second interlayer insulating layer 155 may be formed by a CVD process.

Thereafter, contact holes may be formed to pass through the second interlayer insulating layer 155 and the first interlayer insulating layer 150 and expose the source/drain electrodes SD. As an example, the contact hole may be formed in a self-aligned manner by the cap pattern 145 and the gate spacer 125.

Although not shown, a metal silicide layer may be formed on the source/drain electrodes SD exposed through the contact holes. The metal silicide layer may include, for example, at least one of titanium silicide, tantalum silicide, or tungsten silicide.

Next, contacts CA may be formed in the contact holes, respectively, to be in contact with the metal silicide layer. Each contact CA may include a conductive pillar CP and a contact barrier layer BL surrounding the conductive pillar CP. Specifically, the contact barrier layer BL may be formed to partially fill the contact hole. Thereafter, a conductive layer may be formed to completely fill the contact hole, and a planarization process may be performed to expose the top surface of the second interlayer insulating layer 155. The contact barrier layer BL may comprise a metal nitride layer (e.g., Ti/TiN) and the conductive layer may comprise a metal material (e.g., tungsten).

Referring to fig. 15, an electronic system 1100 according to some example embodiments of the inventive concepts may include a controller 1110, an input-output (I/O) unit 1120, a memory device 1130, an interface unit 1140, and a data bus 1150. At least two of the controller 1110, the I/O unit 1120, the memory device 1130, and the interface unit 1140 may communicate with each other through a data bus 1150. The data bus 1150 may correspond to a path through which electrical signals are transmitted.

The controller 1110 may include at least one of a microprocessor, digital signal processor, microcontroller, or other logic device configured to function similarly thereto. The I/O unit 1120 may include a keypad, a keyboard, or a display unit. The memory device 1130 may store data and/or commands. The memory device 1130 may include a non-volatile memory device (e.g., a FLASH memory device, a phase change memory device, a magnetic memory device, etc.). In addition, memory device 1130 may also include a volatile memory device. For example, the memory device 1130 may include a Static Random Access Memory (SRAM) device having a semiconductor device according to some example embodiments of the inventive concepts. The memory device 1130 may be omitted depending on the purpose of the electronic system 1100 or the type of electronic product using the electronic system 1100. The interface unit 1140 may transmit electrical data to the communication network or may receive electrical data from the communication network. The interface unit 1140 may operate in a wireless or wired manner. For example, the interface unit 1140 may include an antenna for wireless communication or a transceiver for wired and/or wireless communication. A semiconductor device according to some example embodiments of the inventive concepts may be provided as a part of the controller 1110 or the I/O unit 1120. Although not shown in the figures, the electronic system 1100 may also include a fast DRAM device and/or a fast SRAM device, which serve as a cache memory for improving the operation of the controller 1110.

Referring to fig. 16, the electronic device 1200 may include a semiconductor chip 1210. The semiconductor chip 1210 may include a processor 1211, an embedded memory 1213, and a cache memory 1215.

Processor 1211 may include one or more processor cores C1-Cn. One or more processor cores C1-Cn may be configured to process data and signals. The processor cores C1 to Cn may be configured to include semiconductor devices (e.g., a plurality of logic cells described with reference to fig. 1) according to some example embodiments of the inventive concepts.

The electronic device 1200 may be configured to perform its own functions using the processed data and signals. As an example, the processor 1211 may be an application processor.

The embedded memory 1213 may exchange first data DAT1 with the processor 1211. The first data DAT1 may be data processed or to be processed by one or more processor cores C1 to Cn. The embedded memory 1213 may manage the first data DAT 1. For example, the embedded memory 1213 may be used to buffer the first data DAT 1. In other words, the embedded memory 1213 may be used as a buffer memory or a work memory for the processor 1211.

In some example embodiments, the electronic device 1200 may be used to implement a wearable electronic device. In general, wearable electronic devices may be configured to perform operations that calculate small amounts of data rather than large amounts of data. In this sense, where the electronic device 1200 is used in a wearable electronic device, the embedded memory 1213 may be configured to have a relatively small buffer capacity.

The embedded memory 1213 may be a Static Random Access Memory (SRAM) device. SRAM devices may have faster operating speeds than Dynamic Random Access Memory (DRAM) devices. Therefore, in the case where the SRAM is embedded in the semiconductor chip 1210, the electronic device 1200 is likely to have a small size and a fast operation speed. Furthermore, in the case where the SRAM is embedded in the semiconductor chip 1210, active power of the electronic device 1200 may be reduced. As an example, the SRAM may include at least one of the semiconductor devices according to some example embodiments of the inventive concepts.

Cache memory 1215 may be mounted on semiconductor chip 1210 along with one or more processor cores C1-Cn. The cache memory 1215 may be configured to store cached data DATc to be used by or directly accessed by one or more processor cores C1-Cn. The cache 1215 may be configured to have a relatively small capacity and very fast operating speed. In some example embodiments, the cache memory 1215 may include an SRAM device including a semiconductor device according to some example embodiments of the inventive concept. In the case of using the cache memory 1215, the access frequency or access time of the embedded memory 1213 performed by the processor 1211 can be reduced. In other words, the use of the cache 1215 may allow the electronic device 1200 to have a fast operating speed.

To provide a better understanding of example embodiments of the inventive concepts, the cache memory 1215 is illustrated in FIG. 16 as a separate component from the processor 1211. However, the cache memory 1215 may be configured to be included in the processor 1211. Furthermore, example embodiments of the inventive concept are not limited to the example illustrated in fig. 16.

The processor 1211, embedded memory 1213 and cache 1215 may be configured to exchange data or transfer data based on at least one of various interface protocols. For example, the processor 1211, the embedded memory 1213, and the cache memory 1215 may be configured to exchange data or transfer data based on at least one of a Universal Serial Bus (USB), a Small Computer System Interface (SCSI), a Peripheral Component Interconnect (PCI), an Advanced Technology Attachment (ATA), parallel ATA (pata), serial ATA (sata), serial attached SCSI (sas), Integrated Device Electronics (IDE), or universal flash memory (UFS).

Fig. 17 is an equivalent circuit diagram illustrating an SRAM cell according to some example embodiments of the inventive concepts. The SRAM cell may be implemented by at least one of the semiconductor devices according to some example embodiments of the inventive concepts. SRAM cells may be used for embedded memory 1213 and/or cache 1215 of fig. 16.

Referring to fig. 17, the SRAM cell may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA 2. The first and second pull-up transistors TU1 and TU2 may be PMOS transistors, and the first and second pull-down transistors TD1 and TD2 and the first and second access transistors TA1 and TA2 may be NMOS transistors.

A first source/drain of the first pull-up transistor TU1 and a first source/drain of the first pull-down transistor TD1 may be connected to the first node N1. A second source/drain of the first pull-up transistor TU1 may be connected to a power supply line Vcc, and a second source/drain of the first pull-down transistor TD1 may be connected to a ground line Vss. The gate of the first pull-up transistor TU1 and the gate of the first pull-down transistor TD1 may be electrically connected to each other. Accordingly, the first pull-up transistor TU1 and the first pull-down transistor TD1 may constitute a first inverter. The interconnected gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 may serve as input terminals of the first inverter, and the first node N1 may serve as output terminals of the first inverter.

A first source/drain of the second pull-up transistor TU2 and a first source/drain of the second pull-down transistor TD2 may be connected to the second node N2. A second source/drain of the second pull-up transistor TU2 may be connected to the power supply line Vcc, and a second source/drain of the second pull-down transistor TD2 may be connected to the ground line Vss. The gate of the second pull-up transistor TU2 and the gate of the second pull-down transistor TD2 may be electrically connected to each other. Accordingly, the second pull-up transistor TU2 and the second pull-down transistor TD2 may constitute a second inverter. The interconnected gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 may serve as an input terminal of the second inverter, and the second node N2 may serve as an output terminal of the second inverter.

The first inverter and the second inverter may be coupled to each other to form a latch structure. In other words, the gate of the first pull-up transistor TU1 and the gate of the first pull-down transistor TD1 may be electrically connected to the second node N2, and the gate of the second pull-up transistor TU2 and the gate of the second pull-down transistor TD2 may be electrically connected to the first node N1. A first source/drain of the first access transistor TA1 may be connected to the first node N1, and a second source/drain of the first access transistor TA1 may be connected to the first bit line BL 1. A first source/drain of the second access transistor TA2 may be connected to the second node N2, and a second source/drain of the second access transistor TA2 may be connected to the second bit line BL 2. The gate of first access transistor TA1 and the gate of second access transistor TA2 may be electrically coupled to the word line WL. The SRAM cell according to some example embodiments of the inventive concepts may have the aforementioned structure, but example embodiments of the inventive concepts are not limited thereto.

Fig. 18, 19 and 20 are diagrams illustrating some examples of a multimedia device including a semiconductor device according to some example embodiments of the inventive concepts. The electronic system 1100 of fig. 15 and/or the electronic device 1200 of fig. 16 may be applied to the mobile phone or smartphone 2000 of fig. 18, the tablet or smart tablet 3000 of fig. 19, or the notebook 4000 of fig. 20.

According to some example embodiments of the inventive concepts, gate resistance and parasitic capacitance of a semiconductor device may be reduced, thereby improving electrical characteristics (e.g., AC performance and RC delay) of the semiconductor device. The process of manufacturing a semiconductor device can be simplified without increasing the number of steps.

While example embodiments of the present inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising:

a substrate including an active pattern; and

Through the gate structure of the active pattern, the gate structure includes:

gate electrode;

a cap pattern on the gate electrode, the cap pattern having a first dielectric constant;

spacers extending parallel to opposing sidewalls of the gate electrode; and

low-k dielectric layers, each low-k dielectric layer between separate respective sidewalls of the cap pattern and separate respective spacers of the spacers, the low-k dielectric layers having a second dielectric a constant, the bottom surface of each low-k dielectric layer is located at a level higher than the bottom surface of the gate electrode, and the second dielectric constant is greater than or equal to 1 and less than the first dielectric constant,

Wherein, the gate electrode includes a work function metal pattern and an electrode pattern on the upper portion of the work function metal pattern, the width of the electrode pattern is smaller than the width of the upper portion of the work function metal pattern, and

The low-k dielectric layer covers opposite sidewalls of the electrode pattern.

2. The semiconductor device of claim 1, further comprising:

an interlayer insulating layer covering the gate structure, wherein each low-k dielectric layer is surrounded by the interlayer insulating layer, separate ones of the spacers, the capping pattern, and the gate electrode .

3. The semiconductor device of claim 1, wherein each low-k dielectric layer is in direct contact with a separate one of the capping pattern and the spacers.

4. The semiconductor device of claim 1, wherein the capping pattern, the spacers, and the low-k dielectric layer have coplanar top surfaces.

5. The semiconductor device of claim 1, wherein

The gate structure further includes a gate dielectric pattern between the substrate and the gate electrode,

the gate dielectric pattern includes a first extension extending in a direction perpendicular to the top surface of the substrate, and

The gate electrode covers the top surface of the first extension portion.

6. The semiconductor device of claim 1, wherein

The gate structure further includes a barrier pattern between the substrate and the gate electrode, the barrier pattern including a second extension extending in a direction perpendicular to the top surface of the substrate, and

The gate electrode covers the top surface of the second extension portion.

7. The semiconductor device of claim 6, wherein

the barrier pattern includes a first barrier layer and a second barrier layer sequentially stacked on the substrate, and

The first barrier layer and the second barrier layer include different materials.

8. The semiconductor device of claim 1, wherein

The width of the upper portion of the work function metal pattern is greater than the width of the lower portion of the work function metal pattern.

9. The semiconductor device of claim 1, wherein

The low-k dielectric layer covers a portion of the top surface of the work function metal pattern.

10. The semiconductor device of claim 1, wherein a width of the electrode pattern is equal to a width of the capping pattern.

11. The semiconductor device of claim 1, wherein

the work function metal pattern includes a first work function metal pattern and a second work function metal pattern, and

The top surface of the first work function metal pattern is coplanar with the top surface of the second work function metal pattern.

12. The semiconductor device of claim 11, wherein

the first work function metal pattern has a first resistance, the second work function metal pattern has a second resistance, and the electrode pattern has a third resistance; and

The second resistance is smaller than the first resistance and larger than the third resistance.

13. The semiconductor device of claim 1, wherein the low-k dielectric layer comprises at least one of a gaseous material and a silicon oxide material.

14. A semiconductor device comprising:

a substrate including an active pattern; and

Through the gate structure of the active pattern, the gate structure includes:

gate electrode;

a cap pattern on the gate electrode; and

a low-k dielectric layer covering opposite sidewalls of the capping pattern, the low-k dielectric layer having a dielectric constant in the range of 1 to 4,

The low-k dielectric layer covers opposite sidewalls of the electrode pattern.

15. The semiconductor device of claim 14, wherein

16. A semiconductor device comprising:

a substrate including an active pattern; and

Through the gate structure of the active pattern, the gate structure includes:

gate electrode;

a capping pattern on the gate electrode, the capping pattern having a first dielectric constant; and

a low-k dielectric layer at least partially covering sidewalls of the capping pattern, the low-k dielectric layer having a second dielectric constant, the second dielectric constant being less than the first dielectric constant,

The low-k dielectric layer covers opposite sidewalls of the electrode pattern.

17. The semiconductor device of claim 16, wherein

the low-k dielectric layer includes a first portion and a second portion, and

The first part and the second part comprise different materials.

18. The semiconductor device of claim 17, wherein

the first portion covers an upper portion of the sidewall of the cover pattern, and

The second portion covers the lower portion of the sidewall of the cover pattern.

19. The semiconductor device of claim 18, further comprising:

An interlayer insulating layer covering the gate structure, wherein the first portion of the low-k dielectric layer is an extension portion of the interlayer insulating layer.