CN106253906A - There is the device for digital-to-analogue conversion and the correlation technique improving performance - Google Patents

Abstract

The present invention relates to that there is the device for digital-to-analogue conversion and the correlation technique improving performance.In one exemplary embodiment, a kind of device includes the DAC for digital input signals is converted to analog output signal.This DAC includes decoder, and this decoder digital input signal is decoded and provides first group of control signal and second group of control signal.This DAC also includes resistor DAC (RDAC), and this RDAC provides the first voltage and the second voltage in response to first group of control signal.This DAC farther includes interpolater, and this interpolater is coupled to receive the first voltage and the second voltage in response to second group of control signal and provide the first analogue signal.

Description

There is the device for digital-to-analogue conversion and the correlation technique improving performance

Cross-Reference to Related Applications

The application relates to and is incorporated by reference into for various purposes following patent application:

Entitled " the Apparatus for Gain Selection with that on June 6th, 2015 submits to Compensation for Parasitic Elements and Associated Methods (has parasitic antenna to mend Repay for gain select device and correlation technique) " U.S. Patent Application Serial Number 14/732,701 (attorney docket SILA362)；And

Entitled " the Apparatus for Offset Trimming and Associated that on June 6th, 2015 submits to Methods (for offseting device and the correlation technique of fine setting) " U.S. Patent Application Serial Number 14/732,702 (attorney docket SILA363).

Technical field

The disclosure relates generally to process the electronic installation of signal, and relates more specifically to have improvement The device for digital-to-analogue conversion of performance and correlation technique.

Background technology

Electronic signal process it is frequently necessary to process analogue signal and digital signal simultaneously, is sometimes referred to as mixing letter Number process.Some sensors or transducer and natural quality or characteristic, such as temperature, pressure etc., or Person constitutes analog quantity, or often produces analogue signal in the case of sensor.It addition, some transducings Device receives analogue signal as input.

On the contrary, as one of ordinary skill in the understanding, due to such as repeatability, stability, spirit The reasons such as activity, signal processing circuit and structure module are increasingly using digital signal and digital technology. In order to make signal processing circuit be connected by interface with analog circuit, use signaling conversion circuit.

A type of signaling conversion circuit constitutes digital analog converter (DAC).DAC generally by with In accepting digital signal as input, and provide analogue signal as output.Therefore, DAC can carry For the interface between digital processing circuit and analog circuit such as transducer or other circuit.

Several quality factor are used for characterizing or describing DAC in detail.These quality factor include that resolution is (defeated Enter the figure place of information in digital signal), noise level, monotonicity, differential nonlinearity (DNL), Cost, die area, power consumption, gain and offset level and stability etc..

The accompanying drawing with any correspondence that describes in the portion is included as background information material.In this portion Material in Fen is not taken as an admission that these materials constitute prior art for present patent application.

Summary of the invention

This application discloses and there is the device for digital-to-analogue conversion and the correlation technique improving performance.? In one exemplary embodiment, a kind of device includes DAC, and digital input signals is converted to by this DAC Analog output signal.This DAC includes decoder, and this decoder digital input signal is decoded and carries For first group of control signal and second group of control signal.This DAC also includes resistor DAC (RDAC), This RDAC provides the first voltage and the second voltage in response to described first group of control signal.This DAC Farther including interpolater, this interpolater is coupled to receive the first electricity in response to second group of control signal Pressure and the second voltage the first analogue signal is provided.

In another exemplary embodiment, a kind of device includes DAC.This DAC includes current source net Network and the first switching network, this Current Sources has the multiple current sources providing multiple electric currents, and this is first years old The multiple current selectives provided by multiple current sources are supplied to primary nodal point or second section by switching network Point.This DAC also includes the resistor network with multiple resistor, and this resistor network is coupled to carry For output signal.This DAC farther includes second switch network, and this second switch network is coupled to electricity Resistance device network is to be selectively coupled to primary nodal point by the resistor in multiple resistors of resistor network And secondary nodal point.

In another exemplary embodiment, a kind of method converting digital signals into analogue signal includes: It is decoded digital signal generating first group of control signal and second group of control signal；And in response to First group of control signal, by using RDAC to provide the first voltage and the second voltage.The method enters one Step includes: in response to second group of control signal, the first voltage and the second voltage carries out interpolation to provide One analogue signal.

Accompanying drawing explanation

Accompanying drawing only illustrates exemplary embodiment, and be therefore not construed as to the application or The restriction of the protection domain of claims.It will be recognized by one of ordinary skill in the art that disclosed concept Make itself to be applicable to other equally valid embodiments.In the accompanying drawings, use in more than one accompanying drawing Identical numeric indicator represent identical, similar or the function of equivalence, parts or module.

Fig. 1 illustrates the block diagram of DAC framework according to exemplary embodiment.

Fig. 2 describes the circuit arrangement for DAC according to exemplary embodiment.

Fig. 3 illustrates the conceptual schema of DAC framework according to exemplary embodiment.

Fig. 4 describes the circuit arrangement for DAC according to exemplary embodiment.

Fig. 5 illustrates the numerical value of the operation corresponding to DAC according to exemplary embodiment.

Fig. 6 describes the process flow diagram flow chart of the operation for DAC according to exemplary embodiment.

Fig. 7 illustrates the conceptual schema of DAC framework according to exemplary embodiment.

Fig. 8 illustrates the circuit arrangement of gain for finely tuning buffer according to exemplary embodiment.

Fig. 9 illustrates the circuit arrangement for finely tuning interpolater offset voltage according to exemplary embodiment.

Figure 10 describes the circuit arrangement for DAC according to the exemplary embodiment compensating parasitic antenna.

Figure 11 illustrates the circuit arrangement for providing skew fine setting in DAC according to exemplary embodiment.

Figure 12 illustrates the integrated circuit of DAC with the combination of other circuit modules according to exemplary embodiment (IC)。

Figure 13 describes the circuit arrangement using DAC to carry out information processing according to exemplary embodiment.

Figure 14 is shown with the control system of DAC according to exemplary embodiment.

Figure 15 illustrates the circuit arrangement of the feedback control loop with DAC according to exemplary embodiment.

Figure 16 describes to use the communication system of DAC according to exemplary embodiment.

Detailed description of the invention

One aspect of disclosed concept relates to DAC framework and the technology providing some advantage and benefit. The example of these benefits and advantage includes performance and the quality factor improved as described in detail later.

There is the DAC framework of various routine.Relatively stringent specification (such as, monotonicity and phase should be met To high-resolution such as 12) DAC generally include substantial amounts of device, such as resistor, capacitor With transistor (usually mos field effect transistor or MOSFET).Relatively easy Conventional DAC use N bit resolution framework 2^NIndividual element, this generally takes up relatively large tube core Area.

It addition, some specifications of DAC are usual and its other specifications competition.Such as, monotonicity specification warp Often compete with high-resolution.As another example, low-noise operation is the most competing with the overall power of DAC Strive.

Matching element is included for obtaining a kind of technology of monotonicity.In other words, various DAC devices or portion Part or element such as resistor, capacitor and MOSFET are matched to realize monotonicity.Therefore, use Parts match, it is possible to implement current-mode DAC is to realize monotonicity.

In such DAC, in order to realize good coupling, element is relatively large physically, its The most proportional to the square root of element area.Along with DAC resolution increases, the physical size of element is also Increase.It addition, along with DAC resolution increases, for each extra resolution bits, the quantity of element Double.In simple binary system embodiment, for each extra resolution bits, total element area Increase to 8 times.More specifically, use the so much element of twice, and each element be four times big.

It practice, although the technology of the area reducing DAC-circuit can be used, but along with resolution increases, Element area is still significantly increased.A kind of for reduce improve in DAC performance carry out mating required The technology of parts amount is to use thermometer decoder to select higher-order bits (wherein to mate to consider to tend to account for and prop up Join status) and the simple binary of relatively low component level is decoded.But, for implementing thermometer decoder It is much bigger that die area ratio is used for implementing binary-coded area, this partly counteract have less The advantage of integral member area.

Another type of conventional DAC does not relies on element coupling, and the most each input code increment will add One element, thus not the weight of tube elements how, output voltage or electric current are all by rising.DNL is by absolutely Component variation is determined so that if the value of each element meansigma methods ± 100% in, then obtain ± 1 Least significant bit (LSB) (or relatively low order) (LSB) DNL.The brute-force realizing dull DAC calculates method (brute Force approach) use the element (2 with simple non-monotonic DAC equal number^N), but at DAC The decoding logic of middle use and switch trend towards more complicated.Reason is all of 2^NIndividual element is by unique number Word signal rather than the N number of signal for simple binary DAC are controlled.

The quantity of DAC element and decoding circuit is reduced according to the DAC in the various embodiments of the disclosure Complexity.Therefore, according to the DAC offer of various embodiments, there is the most high-resolution dull operation.

More specifically, the resolution of 12, relatively low can be provided according to the DAC of exemplary embodiment The operation of noise and monotonicity (DNL of ± 1LSB) and relatively small die-size.(for quiet State operates, and DAC output is maintained at voltage by programming aperiodically (that is, corresponding to the numeral of DAC The analog output voltage of the DAC of input) and without applying one or more clock signal.) the most detailed Carefully describe the details of DAC framework and operating technology.

In certain embodiments, multiple resistor, switch and electric current are included according to the DAC use of the disclosure The framework in source.Fig. 1 illustrates the block diagram of the framework of this DAC.More specifically, Fig. 1 illustrates DAC 100 Framework, DAC 100 includes Current Sources 103, switching network 106, switching network 109 and resistance Device network 112, resistor network 112 includes multiple resistor.

Current Sources 103 includes that the multiple current sources being respectively labeled as CS0-CSn are (in the example illustrated In be n+1 source).The output electric current of the current source in Current Sources 103 is provided to switching network 106.Switching network 106 promotes the output electric current of the current source in Current Sources 103 to be provided to node (or circuit branch (leg) or circuit branch (branch) or circuit path) 106A or node (or electricity Road branch road or circuit branch or circuit path) 106B.

As it is shown in figure 1, relatively low order (LSB) the driving decoder of the digital input signals to DAC The input of 118.LSB is decoded generating the control letter for switching network 106 by decoder 118 Number.In response to these control signals, switching network 106 can be by the output electric current of Current Sources 103 It is supplied to node 106A or node 106B.Viewed another way, switching network 106 is by current source net It is directed to node 106A and 106B the output current selective of network 103.Switching network 106 guides defeated Go out electric current to keep the monotonicity of DAC 100.

Node 106A-106B is coupled to switching network 109.Digital input signals higher to DAC Significance bit (MSB) drives the input of decoder 121.MSB is decoded generating by decoder 121 Control signal for switching network 109.In response to these control signals, switching network 109 is by node 106A and 106B is couple to resistor network 112.Therefore, according to these control signals, node is flow through The selected part of the current flows through resistor network 112 of 106A-106B.Switching network 109 is by node 106A-106B is couple to resistor network 112, in order to keep the monotonicity of DAC 100.As response, Resistor network 112 provides simulation output.

In the exemplary embodiment, decoder 118 and decoder 121 can be implemented or real in every way Existing, and various configuration or topology can be used.In certain embodiments, decoder 118 may be constructed Thermometer-decoder, and decoder 121 constitutes binary decoder.

It should be noted that Fig. 1 eliminates the certain module of DAC 100 for the ease of showing.Such as, resistance The simulation output of device network 112 can be coupled to buffer or amplifier (not shown), to provide DAC The analog output signal of 100, described analog output signal can be used for driving external loading.As another Individual example, the most not shown biasing circuit.

Fig. 2 describes the circuit arrangement for DAC 100 according to exemplary embodiment.DAC 100 in Fig. 2 It is similar to the DAC shown in Fig. 1 operate.With reference to Fig. 2, DAC 100 include Current Sources 103, Switching network 106, switching network 109 and resistor network 112.

Being similar to Fig. 1, the Current Sources 103 in Fig. 2 includes being respectively labeled as the multiple of CS0-CSn Current source (being n+1 source in the illustrated example).The output of the current source in Current Sources 103 Electric current is provided to switching network 106.

Switching network 106 includes multiple switch 106A1-106N2.In the illustrated example, switch 106A1-106N2 constitutes p-channel mosfet.But, as it will be appreciated by the skilled addressee that Other kinds of switch can be used.As it will be appreciated by the skilled addressee that, the selection of switch is depended on In some factors, such as can technology, for giving the specification etc. of embodiment.

Reference switch network 106, switch 106A1-106N2 is arranged as pairs and is couple to current source net Respective current sources in network 103.Therefore, switch 106A1 and switch 106A2 is coupled to current source CS0. It is coupled to current source CS1 as another example, switch 106B1 and switch 106B2, like this.

Switch 106A1-106N2 is controlled by the signal being labeled as B0 to Bnb.Switch recited above is right In switch by complementary signal control.Such as, the control signal i.e. signal B0 being used for switching 106A1 is to use The control signal i.e. logical complement of signal B0b in switch 106A2.As another example, it is used for out The control signal i.e. signal B1 closing 106B1 is for switching the control signal of 106B2 i.e. signal B1b Logical complement, like this.

Switching network 106 promotes the output electric current of the current source in Current Sources 103 to be provided to node 106A or node 106B.To DAC digital input signals LSB drive decoder 118 input. LSB is decoded generating the switch 106A1-106N2 in switching network 106 by decoder 118 Control signal, in response to described control signal, the corresponding output electric current of current source is directed into two joints In point one.

More specifically, as in figure 2 it is shown, the LSB arriving the digital input signals of DAC drives decoder 118 Input.LSB is decoded generating for switching network 106 i.e. for switching by decoder 118 The control signal of 106A1-106N2.Responding described control signal, switching network 106 can be by current source The output electric current of network 103 is supplied to node 106A or node 106B.

More specifically, the output current selective of Current Sources 103 is directed to by switching network 106 Node 106A and 106B, thus keep the monotonicity of DAC 100.For example, it is contemplated that signal B0 and letter Number B0b is respectively provided with the situation of low and high logical value.Therefore, switch 106A1 is switched on, and opens Close 106A2 to be turned off.Therefore, the output electric current of current source CS0 is transmitted to node by switch 106A1 106A。

On the contrary, it is assumed that signal B0 and signal B0b is respectively provided with high and low logical value.Therefore, switch 106A1 is turned off, and switchs 106A2 and be switched on.Therefore, switch 106A2 is by current source CS0's Output electric current is transmitted to node 106B.

Node 106A-106B is coupled to switching network 109.Switching network 109 is included in Fig. 2 acceptance of the bid It is designated as multiple switches of 109-0 to 109-m.Higher significance bit to the digital input signals of DAC (MSB) promote to switch 109-0 to 109-m to selectively turn on (according to MSB position, as detailed below Describe), and therefore node 106A-106B is couple to resistor network 112.

MSB position drives the input of decoder 121.MSB position is decoded and raw by decoder 121 Become to be labeled as (m+1) individual output signal of A0-Am.Driver 124 generates and is used for switching 109-0 extremely The switch controlling signal of 109-m+1, i.e. it generates (m+2) individual switch controlling signal.

More specifically, driver 124 derives switch from the i.e. signal A0-Am of the output signal of decoder 121 Control signal.Signal A0 and Am respectively control switch 109-0 and 109-m+1, do not have any further Change.But, switch 109-1 to 109-m uses patrolling according to the output execution to decoder 121 Collect the switch controlling signal that operation obtains.

Such as, the switch controlling signal being used for switching 109-1 isWherein symbol "” Represent logic or (OR) operation.As another example, for switching the switch controlling signal of 109-2 It isEtc..In general, the switch controlling signal being used for switching 109-i has Form, wherein i represents integer.For as shown in Figure 2 include joining of (m+2) individual switch Putting, switch 109-m hasThe switch controlling signal of form.

By node 106A-106B, the electric current received from switching network 106 is provided by switching network 109 To resistor network 112.More specifically, as it has been described above, MSB is decoded with life by decoder 121 Become the control signal of the switch being used in switching network 109.In response to these control signals, switching network Node 106A and 106B is couple to resistor network 112 by the switch in 109.

Therefore, as detailed below, according to described control signal, flow through the electricity of node 106A-106B Stream flows through the selected part of resistor network 112.Node 106A-106B is couple to by switching network 109 Resistor network 112, in order to keep the monotonicity of DAC 100.There is provided in response to by switching network 109 Electric current, resistor network 112 provide simulation output.

Resistor network 112 includes multiple resistor.In the embodiment shown in Figure 2, resistor network 112 include (m+1) the individual resistor being labeled as R0 to Rm.According to the switch in switching network 109 State, whether i.e. corresponding switch turns on, be provided in resistor network 112 one of electric current or Multiple resistors.The flowing of electric current forms voltage at resistor network 112 two ends, and this voltage is by simulation Output 115 provides.

Accordingly, in response to the numeral input to DAC 100, DAC 100 is formed at simulation output 115 Output voltage.For example, it is contemplated that the numeral input of DAC 100 is arranged to zero from all positions and starts to be incremented by Situation to its maximum.Described below, as response, DAC 100 is at simulation output 115 Generate signal.

When MSB is arranged to zero, decoder 121 makes signal A0 effective at its output.As Response, driver 124 promotes to be couple to the switch 109-0 of resistor R0 and switch 109-1 conducting.When When LSB is arranged to zero, decoder 118 makes signal B0, B1 ..., Bn, and effectively (this causes signal B0b, B1b ..., Bnb invalid).

Therefore, switch 106A1,106B1 ..., 106Bn conducting, and by current source CS0-CSn Output electric current be supplied to node 106A.Flow into the electric current in node 106A and flow through switch 109-0 to electricity Road ground wire.Therefore, DAC 100 provides zero volt at simulation output 115.

Along with LSB code is incremented by, the output electric current of current source CS0-CSn will be suitable by switching network 106 Sequence is supplied to node 106B.Then, it is provided that resistor R0 will be flow through to circuit to the electric current of node 106B Ground wire, therefore promotes the output voltage at simulation output 115 to increase.

When the output electric current of all of current source CS0-CSn has been provided to node 106B, MSB code Being incremented by starting, such as, it will change into 0...01 from 0...00.Therefore, decoder 121 promotes signal A1 effectively and makes signal A0 invalid.But, the output voltage at simulation output 115 will not change, Because all electric currents at this point flow through the switch controlling signal provided by driver 124 The switch 109-1 controlled.

Along with LSB code is incremented by further, the switch in switching network 106 changes state along contrary order. In other words, the output of current source CS0-CSn is by sequential flowing to node 106A rather than node 106B. Therefore, electric current LSB is switched to resistor R1 from the upper node of resistor R0 by each yard of increment Upper node.Therefore, the output voltage at simulation output 115 rises.

Along with the numeral input of DAC 100 is incremented to maximum code value (such as, all binary ones), Process above repeats.At that point, all output electric currents of current source CS0-CSn will flow into electricity In the upper node of resistance device Rm.Therefore, the output voltage at simulation output 115 will have corresponding to applying The value inputted to the maximum number of DAC 100.

Electric current bootstrapping architecture described above is kept separate from being supplied to the constant of the numeral input of DAC 100 Electric current.Because each step in numeral input from the given resistor of resistor network 112 remove from One elementary current of current source CS0-CSn and this elementary current is supplied to above-mentioned resistor (such as, from Resistor R (m-1) arrives resistor Rm), so DAC framework keeps monotonicity.As long as current value is not As long as reducing and at the resistor discussed, there is positive resistance, in response to the code increment of the input of DAC 100, Voltage at simulation output 115 just will rise.

In the exemplary embodiment, driver 124 can be implemented in every way.Such as, implement at some In example, driver 124 can include logic circuit, such as disjunction gate (OR door), is used for generate The switch controlling signal of the switch in switching network 109.However, it is possible to otherwise implement driver 124.As it will be appreciated by the skilled addressee that the selection of embodiment depend on such as can technology, Some factors such as available die area, specification.

It should be noted that and be similar to Fig. 1, for the ease of showing, Fig. 2 eliminates the certain module of DAC 100. Such as, the simulation output of resistor network 112 can be coupled to buffer or amplifier (not shown), To provide the analog output signal of DAC 100, described analog output signal can be used for driving outside bearing Carry.As another example, biasing circuit is not shown in FIG. 2.

As set forth above, it is possible to be practiced or carried out decoder 118 and decoder 121 in every way, and can To use various configurations or topology.In the embodiment shown in Figure 2, decoder 118 may be constructed temperature Meter decoder, and decoder 121 constitutes binary decoder.As it will be appreciated by the skilled addressee that Other types and/or the configuration of decoder can be used.

In order to control switching network 106 compared with switching network 109, an aspect of this disclosure relates to number The distribution of word input bit.In other words, the distribution of numeral input bit includes the phase selecting or determining m and n To value, m and n determines in quantity and the resistor network 112 of the current source in Current Sources 103 The quantity of resistor.

Consider to use Thermometer-decoder as decoder 118 and to use binary decoder as decoder The embodiment of 121, the distribution i.e. m value of position (bit) and the selection of n value can attributes based on decoder. Especially, the size of Thermometer-decoder be typically binary decoder size approximately twice as (i.e., It consumes the die area of twice in IC).If resistor is similar with current source element size, The most less position can be assigned to current source.Such as, resistor network 112 uses 6 and current source Network 103 uses 5 production to have decoder (that is, decoder 118 and the decoding of about the same size The die area that device 121 uses is about the same).(it should be noted that be generally basede on DAC 100 to Determine the integral nonlinearity (INL) of embodiment and noise requirements to select DAC component size).

Another aspect of the disclosure relates to increasing dividing of DAC 100 by modifying switching network Resolution.More specifically, by controlling the grid voltage of current steering switches rather than they can be biased The resolution of DAC 100 is increased for simple current steering switches.If by would correspond to given electricity Two of two switches (such as, corresponding to switch 106N1 and 106N2 of current source CSn) in stream source Grid voltage is set to be equal or approximately equal and by the two switch connection, corresponding current source is (such as, The previously CSn in example) output electric current will be equably or approximately uniformly at node 106A-106B Between divide.In other words, switch is biased to conduct the current source (example of correspondence the most between which Such as, the previously CSn in example) output electric current.

This configuration adds extra resolution bits to DAC 100, retains monotonicity simultaneously.Exemplary In embodiment, it is possible to use XOR gate (XOR gate) implements the switch in switching network 106 Digital control, with determine which switch corresponding to control program above applied to constant current source.

It should be noted that except using XOR gate to be controlled, it is also possible to use other mechanism and circuit arrangement. Such as, in certain embodiments, control mechanism can be built in Thermometer-decoder.It should be noted that Extra bias level can be that cost adds more resolution with loss monotonicity (or monotonicity deterioration) Rate position.Therefore, as it will be appreciated by the skilled addressee that, existence is compromise, and it can be based on such as using The factors such as the specification in given application.

In some applications, relatively low noise level is desired.An aspect of this disclosure relates to carrying For the DAC (such as, compared with conventional DAC) of relatively low noise level, retain monotonicity simultaneously. Fig. 3 illustrates the block diagram of low noise DAC 200 according to exemplary embodiment.

DAC 200 includes resistor network 203, switching network 206, switching network 209, interpolater net Network 212 and output stage 215, wherein resistor network 203 includes multiple resistor.It addition, DAC 200 Including decoder 218, the numeral input being applied to DAC 200 is decoded and raw by decoder 218 Become for switching network 206 and the control signal of switching network 209.

Resistor network 203 is coupled to reference voltage V_ref.Therefore, current flows through resistor network 203. Causing generating multiple voltage by the flowing of the electric current of resistor network 203, the plurality of voltage is provided To switching network 206.

As it has been described above, the numeral input of DAC 200 is decoded by decoder 218, and generation is used for Control signal 218A of switching network 206.More specifically, from higher the having of the numeral input of DAC 200 Effect position (MSB) obtains control signal 218A.In response to control signal 218A, switching network 206 selects The voltage of selecting property ground self-resistance device network 203 in the future is couple to be labeled as V_evenAnd V_oddNode.More Body ground, based on control signal 218A, a voltage from resistor network 203 is coupled to node V_even, and a voltage is coupled to node V_odd。

Switching network 209 is optionally by node V_evenAnd V_oddIt is couple to interpolater network 212.As Response, signal such as electric current is supplied to output stage 215 by interpolater network 212.Based on from interpolater network The signal of 212, output stage 215 generates output signal at simulation output 221.In an illustrated embodiment, The output of simulation output 221 composition DAC 200.

Switching network 209 operates in response to control signal 218B.More specifically, based on control signal 218B, switching network 209 is optionally by node V_evenAnd V_oddIt is couple to interpolater network 212.Solve Code device 218 is to the numeral input decoding to DAC 200, and generates the control for switching network 209 Signal 218B.Control signal 218B is the relatively low order (LSB) of the numeral input from DAC 200 Obtain.

Generally, inputting in response to numeral, DAC 200 uses the switching network 206 and 206 will be from resistance Two output signals that the output of device network 203 obtains are routed to interpolater network 212.Therefore, DAC 200 It is considered generation to be coupled to drive interpolater (the interpolater network driven by switching network 209 212) two outputs are (at node V_evenAnd V_oddPlace) RDAC (drive switching network 206 Resistor network 203) combination or cascade.

In the exemplary embodiment, interpolater network 212 can be implemented in every way.Such as, at some In embodiment, interpolater network 212 can use multiple mutual conductance (g_m) level or amplifier.Therefore, interior Plugging in device network 212 can be g_mInterpolater network.

Fig. 4 describes the circuit arrangement for DAC 200 according to exemplary embodiment.It is similar to shown in Fig. 3 Embodiment, the DAC 200 in Fig. 4 includes resistor network 203, switching network 206, switching network 209, interpolater network 212 and output stage 215.It addition, DAC 200 includes decoder 218, decoding The numeral input being applied to DAC 200 is decoded and generates for switching network 206 He by device 218 The control signal of switching network 209.

Resistor network 203 includes being coupled in series in reference voltage (V_ref) and ground potential between multiple Resistor (is labeled as R0 to RN).In certain embodiments, resistor R0-RN can have identical (or approximately uniform) resistance value.Resistor is applied reference voltage and will cause current flows through resistor String.Therefore, each same resistors two ends in the multiple resistors in resistor network 203 are formed Multiple voltages.Consequent multiple voltage is fed to switching network 206.

Switching network 206 includes multiplexer (MUX) 206A and MUX 206B.MUX 206A-206B operates respectively responsive to control signal 218A1-218A2.Resistor R0-RN is to hand over The mode replaced is coupled to MUX 206A-206B.More specifically, the upper node of each resistor is replaced Be couple to MUX 206 and MUX 206B.Such as, the upper node of resistor R0 is coupled to MUX The input of 206A, and the upper node of resistor R1 is coupled to the input of MUX 206B, etc..

In response to the numeral input of the input signal being applied for DAC 200, decoder 218 generates and controls letter Number 218A1-21A2.Control signal 218A1-21A2 forms control signal 218A together.Based on DAC 200 The value of higher significance bit (MSB) of numeral input, decoder 218 generates control signal 218A1-21A2. In other words, control signal 218A1-21A2 is obtained from MSB to control MUX 206A-206B respectively.

Control signal 218A1-21A2 promotes MUX 206A-206B optionally by resistor R0-RN It is couple to be labeled as V_evenAnd V_oddTwo nodes in one.Therefore, based on MSB, MUX The output voltage of resistor network 203 is optionally supplied to node V by 206A-206B_evenAnd V_odd。 In an illustrated embodiment, node V_evenAnd V_oddIn each be coupled to by switching network 206 Half resistor in resistor network 203, and described in couple be staggered.Therefore, node V_even And V_oddCross over resistor string or the scope of ladder, but by resistor that is different or that replace, the most occasionally The upper node of number resistor is couple to V_evenNode, and the upper node of odd number resistor is couple to V_oddNode (or vice versa as the same).

Node V_evenAnd V_oddIt is couple to the input of switching network 209.Switching network 209 includes MUX 209-0 to 209-k.Node V_evenIt is couple to an input of MUX 209-0 to 209-k.Node V_odd It is couple to another input of MUX 209-0 to 209-k.The output of MUX 209-0 to 209-k drives The corresponding input of interpolater network 212.

Switching network 209 is optionally by node V_evenAnd V_oddIt is couple to interpolater network 212.Specifically Ground, switching network 209 operates in response to control signal 218B.Therefore, based on control signal 218B, Switching network 209 is by node V_evenAnd V_oddIt is selectively coupled to interpolater network 212.

Decoder 218 provides control signal 218B.Specifically, the decoder 218 numeral to DAC 200 Input is decoded and generates control signal 218B for switching network 209.Control signal 218B It is that the relatively low order (LSB) that the numeral from DAC 200 inputs obtains.

Switching network 209 is by node V_evenAnd V_oddIt is selectively coupled to interpolater network 212.Institute In the embodiment shown, the interpolater in interpolater network 212 constitutes multiple mutual conductance (g_m) level or amplifier, Therefore it is g_mInterpolater network.G in interpolater network 212_mInterpolater is marked as g_moTo g_mk。

As it has been described above, each g in interpolater network 212_mAn input in interpolater is as noninverting defeated Enter to be coupled to the corresponding of the MUX among MUX 209-0 to 209-k to export.Interpolater network 212 In g_mAnother input such as anti-phase input in interpolater is coupled to include resistor 224 and resistor The feedback network of 226.Specifically, by resistor 224 and resistor 226, in interpolater network 212 G_mInterpolater receives (in the embodiment shown in fig. 4, press relevant with the signal at simulation output 221 Scale smaller) signal.By selecting resistor 224 and the appropriate value of resistor 226, interpolater net The overall gain of network 212 and output stage 215 can be programmed to desired value.

In response to the output of MUX 209-0 to 209-k, g_mInterpolater g_m0To g_mkOutput signal is provided, Described output signal sues for peace to generate the output signal (example for interpolater network 212 at node 212A As, current signal).Signal at node 212A drives the input of output stage 215.As response, Output stage 215 generates output signal at simulation output 221.In an illustrated embodiment, simulation output 221 outputs constituting DAC 200.

Output stage 215 can be implemented in every way.Such as, in certain embodiments, output stage can be wrapped Include (multiple) transconductance stage and amplifier, such as class ab ammplifier.Output stage 215 is in simulation output 221 Place provides analogue signal, and this analogue signal can drive external loading.

As the DAC in Fig. 2, some positions of the numeral input of DAC 200 can be assigned to control Switching network 206, and remaining bit can be assigned to drive switching network 209.For example, it is contemplated that according to one 12 DAC of individual embodiment, wherein 5 LSB realizing DAC 200 of the numeral input of DAC. In such DAC, the resistor string in resistor network 203 realizes 7 MSB (128 of DAC Individual element).In such embodiments, controlled by 6 or select signal 218A1 and 218A2 respectively Control MUX 206A and MUX 206B.

The residue 5 of the numeral input of DAC 200 realizes LSB.Therefore, DAC includes switching network 209 In 2⁵Or 32 MUX.The output of 32 MUX drives the interpolater in interpolater network 212 One input.In such embodiments, interpolater network 212 includes 32 interpolaters, i.e. k=31.

In order to illustrate the operation of such DAC, it should be noted that MUX 206A and 206B is by resistor net The tap in resistor string in network 203 is couple to V_evenAnd V_oddNode or bus.Because DAC's 7 MSB in numeral input are raised to 1111111 from 0000000 slope, so from resistor tap Voltage changes with " leapfroging " mode or over-over mode.Fig. 5 exemplifies present node V_evenAnd V_oddPlace Some voltages.

As shown in the form in Fig. 5, at node V_evenAnd V_oddThe voltage at place depends on reference voltage V_ref With MSB input code (being indicated column headings " code " is lower).It should be noted that and change in response to continuation code, At node V_evenAnd V_oddVoltage phase difference (1/128) V at place_refOr 0.0078125 V_refVoltage.If V_refThere is the value of 1.2 volts, then V_evenAnd V_oddBetween difference will be about 10mV.It should be noted that as Really MSB code is even number, then V_oddV will be compared_evenHigh 10mV.On the contrary, if MSB code has odd number Value, then V_evenV will be compared_oddHigh 10mV.The output of input code and reference voltage value is depended on by generation (V_evenAnd V_odd), the combination of resistor string and switching network (with corresponding decoder circuit) is permissible It is considered as RDAC.

In example discussed above, interpolater network 212 realizes relatively low 5 LSB.As its name suggests, Interpolater network 212 uses 32 g_mInterpolater is at V_evenAnd V_oddInterpolation between voltage at node. As it has been described above, control signal 218B that the LSB from the numeral input of DAC obtains controls at V_even Place voltage and at V_oddWhich each phase of being provided in interpolater network 212 in the voltage at place Answer interpolater.

In order to illustrate the operation of interpolater network 212, it is assumed that 7 MSB have value 0000000, the most all It is 0.In this case, V_evenIt is 0V, and V_oddThere is the value (seeing Fig. 5) of about 10mV. When 5 LSB are 0 (i.e. 00000), 32 g_mTheir non-inverting input is connected by interpolater To V_evenI.e. 0V or ground potential.Assume that output stage 215 has the gain of 3V/V, in simulation output Signal at 221 will have 0V value (ground potential).

Along with LSB from 00000 slope liter (ramp up) or is incremented to 11111, each increment (LSB of code Value) cause being supplied to g by switching network 209_mInterpolater g_m0-g_mkOne of input from V_even(0V) It is switched to V_odd(≈10mV).When LSB is binary one (code 11111), switching network 209 By V_odd(≈ 10mV) provides 32 g_mIn interpolater 31 are as input.In this case, Voltage at simulation output 221 will have value 3 × (31/32) × 10mV, or about 29mV.

For the LSB code value between 00000 and 11111, switching network 209 is by node V_even The voltage at place is supplied to some g_mInterpolater, and by voltage V_oddIt is supplied to remaining g_mInterpolater. Therefore, based on receiving node V_oddThe voltage at place is as a part of g of input signal_mInterpolater, in simulation Export the interpolated value that the signal at 221 will have between 0V and about 29mV.V_evenAnd V_oddIt Between small voltage difference the linear or approximately linear interpolation performed by interpolater network 212 is provided.

When 12 inputs (i.e. arriving the numeral input of DAC) are incremented to next after 000000011111 During individual value, there is " leapfroging " character recited above or alternating property.7 MSB in numeral input It is incremented to 0000001 from 0000000, and 5 LSB change into 00000 from 11111.Decoder Control signal 218B is respectively supplied to MUX 209-0 to 209-k by 218 so that when MSB code is strange Position incoming during number is changed, thus all of 32 g_mInterpolater receiving node V_oddThe voltage at place is made For input (it still has the value of ≈ 10mV).

When in inputting in DAC numeral, incoming LSB code is incremented to 00001,31 g_mInterpolater is still So it is coupled to (via switching network 209) to receive at node V_oddThe voltage at place as input, and one Individual g_mInterpolater receiving node V_evenThe voltage at place is as input, and it has ≈ 20mV rather than 0V now Value.In this way, along with incoming LSB is incremented by further, more g_mInterpolator stage receives at joint Point V_evenPlace voltage rather than at node V_oddThe voltage at place.Therefore, interpolated signal is (at outfan 212A Place) and therefore export the output signal continuation rising at 221 in simulation.Finally, all of g_mInterpolation Device receives at node V_evenThe voltage at place is as input.At that point, MSB code is incremented by again, and should Process repeats.

Although it should be noted that and describing DAC operation according to exemplary embodiment above with reference to 12 DAC, But similar description and operation are applicable to the DAC according to other exemplary embodiments.Therefore, such as this area Ordinarily skilled artisan will understand that, described concept can be applied to having different resolution, different number The DAC of the element etc. of amount.

Fig. 6 describes the process flow diagram flow chart of the operation for DAC according to exemplary embodiment.At 253, Receive the digital input signals being provided to DAC.At 256, digital input signals be decoded for from The higher significance bit (MSB) of digital input signals obtains one group of control signal.From digital input signals Relatively low order (LSB) obtains another group control signal.

At 259, the one group of control signal obtained from MSB is used for driving RDAC, in order to generate V_oddAnd V_even.At 262, the one group of control signal obtained from LSB is used for driving interpolater, with From V_oddAnd V_evenObtain analog output signal.Such as, as it has been described above, by using output stage, simulation Output signal can be cached or processed further.

Many benefits and advantage is provided in conjunction with the DAC disclosed in Fig. 3-Fig. 5.Such as, with conventional DAC Comparing, an advantage relates to the operation of relatively low noise, keeps monotonicity and described above simultaneously Other characteristics.Another advantage relates to relatively easily arranging relatively accurate gain for DAC.

An aspect of this disclosure relates to the gain in electronic installation such as DAC and selects or regulation.Hereinafter retouch State use DAC as example to illustrate concept, but such as it will be appreciated by the skilled addressee that disclosed Concept can be applied to the various electronic installations with selectable or adjustable gain.

As it has been described above, depend on reference voltage (V according to the gain of the DAC of exemplary embodiment_ref) Value.In order to illustrate various value such as V_refThe gain with the output stage impact on overall DAC characteristic, Fig. 7 The conceptual schema of the DAC 200 according to exemplary embodiment is provided.

In an illustrated embodiment, reference voltage (the i.e. V used in DAC_ref) can be original base Quasi-voltage (V_r) scaling or divide version.Optionally or additionally, master reference voltage can be in outside It is applied to DAC 200, such as, by including that pin in the IC of DAC 200 is by voltage V_EXTApply To DAC 200.As it will be appreciated by the skilled addressee that, such as outside reference source, various source can carry Voltage supplied V_ExT.As detailed below, in such an arrangement, DAC 200 include for process and Use the signal provided by a reference source to generate V_refMechanism.

In either case, by using the appropriate value for scaling or divide the factor, it is possible to obtain overall Expectation DAC yield value.Desired zoom factor is applied to V by scaling circuit 303_r, in order at scaling The outfan 303A of circuit 303 generates the zoom version being applied to buffer 306.Scaling circuit 303 Zoom factor can have one expectation the value or set of values, and can be as required programmable or Adjustable.Buffer 306 is V_rZoom version caching is provided or amplifies, and at its outfan DAC reference voltage V is provided at 306A_ref.Buffer 306 has the fine gains allowing to finely tune its gain Input 306B.

As it has been described above, reference voltage V_refIt is applied to RDAC 309.As described in detail above, response In control signal 218A and V_ref, RDAC 309 provides voltage V at its output_evenAnd V_odd。 As it has been described above, decoder 218 carries by being decoded the digital input signals being applied to DAC 200 For control signal 218A.

Interpolater 312 accepts to be labeled as V_evenAnd V_oddVoltage as input.As described in detail above, Interpolater 312 can include switching network and some interpolator stage.As described in detail above, in response to Control signal 218B, interpolater 312 is formed as voltage V at outfan 312A_evenAnd V_oddLetter The output voltage of number.As it has been described above, decoder 218 is by the numeral input letter being applied to DAC 200 Number it is decoded providing control signal 218B.

Interpolater 312 has skew fine setting input 312B.Signal in input 312B place's applying can be by For finely tuning the offset voltage of interpolater 312B.As it will be appreciated by the skilled addressee that, do so will Improve the overall performance of DAC 200.As described in detail above, output stage 215 receives interpolater 215 Output signal, and at outfan 221 generate DAC 200 simulation output.In exemplary enforcement In example, output stage 215 can have programmable or adjustable gain.This feature allows to arrange DAC The overall gain of 200 or full range voltage.

Scaling circuit 315 scales the analog output voltage of DAC 200 to generate V at outfan 315A_r Zoom version.Scaled voltage at outfan 315A is provided to interpolater 312 as from interpolater The feedback signal that the output voltage of 312 obtains.The zoom factor of scaling circuit 315 can have an expectation The value or set of values, and can be programmable or adjustable as required.Therefore, output stage has Effect gain (more specifically, interpolater 312 and overall gain of output stage 215) can be programmed to expectation Value.

Reduce voltage V_rMany benefits can be provided, the most easy to implement.In certain embodiments, N-shaped In the switching network (not shown in Fig. 7) that MOS (nMOS) device can be used in DAC 200. Reduce V_rAllow to reduce or limit the amplitude of oscillation of the input voltage of the interpolator stage being applied in interpolater 312. Additionally, scaled voltage V_rAllow overall gain or the Full-span output voltage of DAC 200 are programmed or are set Put.

In the exemplary embodiment, buffer 306 has a gain of unit one (unity), but buffer 306 can be used to provide for programmable gain set-point with the combination scaling circuit 303.Programmable increasing Benefit setting value can have various expected value, such as, 1/2,1/2.4 and 1/3.Programmable gain sets Value allows to arrange or the overall gain of programming DAC 200.As example, it is considered to have the output that gain is 3 The DAC of level 215.If it is desire to DAC has the overall gain of unit one, then can use the scaling of 1/3 The factor is for scaling circuit 303, i.e. V_ref=(1/3) × V_r.Overall gain will have 1/3 × 3 or single The value of position one.

Buffer 306 also has fine gains ability, and this allows to eliminate (or approximation eliminates) buffer 306 Output offset voltage.If not eliminating output offset voltage, then as gain during it appears in DAC Error, and its penalty will be made.In the exemplary embodiment, the gain of buffer 306 is micro- Tune can correct (or approximate correction) temperature and change effect, mains voltage variations etc..

The fine setting of the gain of buffer 306 can be carried out in many ways.In certain embodiments, producing Fine setting is carried out during test after the process during product test.In certain embodiments, as required, During use as periodically or carried out fine setting when powering on and/or carrying out fine setting according to other schemes.Figure 8 illustrate the circuit arrangement 350 of gain for finely tuning buffer 306 according to exemplary embodiment.(below Other aspects of skew fine setting are discussed in conjunction with Figure 11.)

With reference to Fig. 8, the output signal of scaling circuit 303 is applied to switch 353.The use of switch 353 It is optional.If using this switch under the control of controller 359, then switch 353 permission selectivity Ground uses V_rZoom version or another gain-adjusted voltage, carry out with the gain to buffer 306 Fine setting (another part of controller 359 or DAC can generate the voltage for fine gains).Pass through The voltage of switch 353 selection is applied to the input of buffer 306.The output of buffer 306 is applied in To switch 356.Under the control of controller 359, switch 356 can be optionally by buffer 306 Output 306A is supplied to RDAC 309 or controller 359.

In the normal operation period (i.e. when not to the fine gains of buffer 306), switch 356 will Output 306A is couple to RDAC 309.During fine gains operates, switch 356 will export 306A It is couple to controller 359.Actual output voltage according to buffer 306 and expection output voltage are (based on executing It is added to the input voltage of buffer 306), one or more control signals are applied to delay by controller 359 The fine gains input 360B of storage 306.Therefore, the gain of buffer 306 is fine-tuning to expected value (example As, it is unit one (unity) in the exemplary embodiment).

It should be noted that as it has been described above, in certain embodiments, DAC (or other equipment, circuit, module Deng) user controller 359 can be promoted to perform fine gains at one or more desired time points. It is further to be noted that in certain embodiments, DAC can be configured to as required one or more As powered on or automatically carrying out fine gains during the reset of DAC at desired time point.Additionally, it is each Kind of other circuit arrangement be possible and be it is contemplated that.Such as, in certain embodiments, controller The 359 outside realizations that partly or wholly can reside at IC thereon at DAC, are such as performing behaviour Make the production test instrument of the test after processing such as IC and fine setting realizes.Such as those of ordinary skill in the art It will be appreciated that in certain embodiments, such as switch 353 and/or switch 356 can be omitted, but logical The output (instead of using switch 356) etc. crossing sensing RDAC 309 uses the extra of buffer 306 Input or parallel input (replacing switch 353).

Similarly, the output offset voltage of interpolater 312 can be trimmed off.In the exemplary embodiment, The fine setting of the output offset voltage of interpolater 312 can correct (or approximate correction) temperature change effect, Mains voltage variations etc..

The fine setting of the output offset voltage of interpolater 312 can be performed in many ways.Implement at some In example, perform fine setting when product test during test after the process.In certain embodiments, As required, during use as periodically or performed when powering on to finely tune and/or hold according to other schemes Row fine setting.Fig. 9 illustrates the circuit for being finely adjusted interpolater offset voltage according to exemplary embodiment Arrange 400.(other aspects of skew fine setting are discussed below in conjunction with Figure 11.)

With reference to Fig. 9, voltage V_evenAnd V_oddIt is respectively applied to switch 403A and 403B.It should be noted that The use of switch 403A-403B is optional.If using this switch under the control of controller 359, Then switch 403A-403B allows optionally to use V_evenAnd V_oddOr another group skew trim voltage is come The skew of interpolater 312 is finely adjusted that (DAC of controller 359 or another part can generate use Voltage in skew fine setting).

The voltage selected by switch 403A-403B is applied to the input of interpolater 312.As it has been described above, The output of interpolater 312 is applied to scale circuit 315.The output 315A of scaling circuit 315 is provided To controller 359.The output signal of scaling circuit 315 is used for the skew of the output voltage to interpolater 312 It is finely adjusted.

Under the control of controller 359, switch 406 can be optionally by (as detailed above Generated by decoder 218) control signal 218B or by controller 359 generate (at outfan At 306A available) control signal 359A is supplied to interpolater 312.Controller 359 is based on to interpolation The input signal of device 312 generates control signal 359A so that interpolater 312 has desired output voltage (such as, 0V), so that it is determined that and the output offset voltage of fine setting interpolater 312.

In the normal operation period (i.e. when offset voltage to interpolater 312 is not finely adjusted), open Close 403A-403B by voltage V_evenAnd V_oddIt is couple to interpolater 312.It addition, switch 406 general (by Decoder 218 generates) control signal 218B is supplied to interpolater 312.Therefore, as it has been described above, DAC Analog output signal is generated in response to numeral input.

But, as it has been described above, during skew fine setting operation, switch 403A-403B couples V_evenWith V_oddOr another group skew trim voltage, is finely adjusted with the skew to interpolater 312.Additionally, switch 406 provide control signal 359A to interpolater 312.The output 315A of scaling circuit 315 is by interpolater The zoom version of the output voltage of 312 is supplied to controller 359.

Actual output voltage according to interpolater 312 and expection output voltage are (based on being applied to interpolater 312 Input voltage) (or scaling circuit 315 outfan 315A at down-scaled version), controller The 359 skew fine setting input 312B that one or more control signals are applied to interpolater 312.Therefore, The skew of interpolater 312 is fine-tuning to expected value (such as, zero or be approximately zero).

It should be noted that as it has been described above, in certain embodiments, DAC (or other equipment, circuit, module Deng) user can promote controller 359 perform at one or more desired time points skew fine setting. It is further to be noted that in certain embodiments, DAC can be configured to as required one or more As powered on or automatically carrying out skew fine setting during the reset of DAC at desired time point.Additionally, it is each Kind of other circuit arrangement be possible and be it is contemplated that.Such as, in certain embodiments, controller The 359 outside realizations that partly or wholly can reside at IC thereon at DAC, are such as performing behaviour Make the production test instrument of the test after processing such as IC and fine setting realizes.Such as those of ordinary skill in the art It will be appreciated that in certain embodiments, such as switch 403A-403B and/or switch 406 can be omitted, But by sensing the voltage at outfan 221 and using interior by 312B applying correction voltage Insert the inclined of the extra of device 312 or parallel input (replacing switch 403A-403B) regulation interpolater 312 Move voltage (instead of using switch 406) etc..

The various alternative configuration of the circuit arrangement in Fig. 8-Fig. 9 be possible and it is contemplated that.Such as, In certain embodiments, the some or all of functions of decoder 218 can be entered with the function of controller 359 Row combination, or vice versa as the same.Use in a particular application as it will be appreciated by the skilled addressee that The selection of circuit arrangement depends on that some factors are such as the specification of this application.

As it has been described above, in the exemplary embodiment, more than one source can be used for generating reference voltage V_ref。 Do so is directed to use with the switch allowing to select described source.Switch has limited parasitic antenna, such as posts Raw resistance (such as, on-state resistance).It addition, as it has been described above, change V_refValue cause DAC Overall gain or output full scale value change.

In order to keep or provide desired gain or full scale value, the actual gain of output stage can be programmed Or it is set to correspond to selected V_refThe value of value.Actual gain (interpolater and the output stage of output stage The overall gain of 215) can be programmed by scaling circuit 315.The actual gain of output stage is compiled Journey relates to using switch in scaling circuit 315.These switches also have limited parasitic antenna, such as Dead resistance (such as, on-state resistance).An aspect of this disclosure relates to electronic installation such as DAC In gain and skew fine setting or regulation.

An aspect of this disclosure relates to compensating parasitic antenna or effect, such as in electronic installation is such as DAC The dead resistance of above-mentioned switch.Figure 10 depict for compensate parasitic antenna according to exemplary embodiment The circuit arrangement of DAC 200.

DAC 200 in Figure 10 includes module same or similar with some shown in Fig. 7 or electricity Road.Scaling circuit 303 in Figure 10 provides and is used for generating V for selection_refThe machine in one or two source System.In an illustrated embodiment, from the external voltage (V in the source outside DAC 200_EXT) or another Individual voltage V_r(source such as, being internally generated) can be used for generating V_ref。

Voltage V_EXTIt is applied to be respectively provided with R₁And R₂(tapped) resistance of band tap of resistance value Device 450A-450B.Resistor 450B is couple to ground wire by switch 456D.Phase when scaling circuit 303 When should partly be not used by or when DAC 200 is not used by etc., switch 456D allows to pass through resistor 450A-450B is from V_EXTFlowing to the current interruptions of ground wire, this causes power consumption to reduce.Controller 359 is controlled The operation of system switch 456D.

Tap in resistor 450A-450B is coupled to switch 456A and 456C respectively.Switch 456B It is couple to one end of resistor 450A or terminal and one end of resistor 450B.Controller 359 controls The operation of each switch 456A-456C.Such as, controller 359 can promote switch 456A-456B to beat Open and switch 456C Guan Bi.Being switched by control, controller 359 can promote at scaling circuit 303 Outfan 303A1 at provide voltage V_EXTPart able to programme or expectation part.

Similarly, voltage V_rIt is applied to be respectively provided with R₁And R₂The resistor 453A-453B of resistance value. Resistor 453B is couple to ground wire by switch 459D.When the appropriate section of scaling circuit 303 is not used by Time or when DAC 200 is not used by etc., switch 459D allows by resistor 453A-453B from V_r Flowing to the current interruptions of ground wire, this causes power consumption to reduce.Controller 359 controls the operation of switch 459D.

Tap in resistor 453A-453B is coupled to switch 459A and 459C respectively.Switch 459B It is couple to one end of resistor 453A or terminal and one end of resistor 453B.Controller 359 controls The operation of each switch 459A-459C.Such as, controller 359 can promote switch 459A-459B to beat Open and switch 459C Guan Bi.By controlling these switches, controller 359 can promote at scaling circuit Voltage V is provided at the outfan 303A2 of 303_rPart able to programme or expectation part.As it can be seen, it is defeated Go out 303A1 and 303A2 and flow into the input of buffer 306.

As it has been described above, scaling circuit 315 (can at outfan 221 by be used for providing output stage 215 ) zoom version of output signal (is expressed as V_o) mechanism be supplied to interpolater 312.Voltage V₀ It is applied to be respectively provided with M R₁With M R₂The resistor 462A-462B of resistance value, wherein M represents Positive integer.Resistor 462B is couple to ground wire by switch 465D.Appropriate section when scaling circuit 303 When being not used by or when DAC 200 is not used by etc., switch 465D allows to pass through resistor 462A-462B is from V_nFlowing to the current interruptions of ground wire, this causes power consumption to reduce.Controller 359 controls The operation of switch 465D.

Tap in resistor 462A-462B is coupled to switch 465A and 465C respectively.Switch 465B It is couple to one end of resistor 462A or terminal and one end of resistor 462B.Controller 359 controls The operation of each switch 465A-465C.Such as, controller 359 can promote switch 465A-465B to beat Open and switch 465C Guan Bi.By controlling these switches, controller 359 can promote voltage V₀'s Part able to programme or expectation part are provided to interpolater 312, to realize the output stage to DAC 200 Gain programming.

In actual embodiment, the circuit arrangement shown in Figure 10 includes various parasitic antenna, such as opens Close the dead resistance of 456A-456D, 459A-459D and 465A-465D.When the increasing arranging DAC 200 When benefit or Full-span output value, the dead resistance of switch 456D, 459D and 465D may cause error. By suitably by the size of the element in given size design scaling circuit 303 and 315, error is permissible It is cancelled or approximates counteracting.

Specifically, as it has been described above, the corresponding resistor of resistor 462A-462B is resistor 450A-450B M times of resistance big.In addition, it is assumed that switch 456D and 459D has for R_SWDead resistance, then Switch 465D is scaled or is designed as having M R by given size_SWDead resistance.Part dimension sum The selection of value is offset or approximation offsets gain error discussed above, and condition is actual gain G of output stage_out (that is, interpolater 312 and the overall gain of output stage 215) is the effective of reference voltage gain setting circuit Gain G_refThe inverse of (that is, scaling circuit 303 and the overall gain of buffer 306).

Below equation represents the overall gain of DAC 200 in this case:

G_ref·G_out={ (R₂+R_sw)/(R₁+R₂+R_sw)·{1+(M·R₁)/((M·R₂)+(M·R_sw)) [equation 1]

It should be noted that if meeting condition reciprocal described above, then G_ref·G_out=1.

If moreover, it is noted that G_refAnd G_outBe not arranged to reciprocal value, then gain error will be by part Ground is offset.Therefore, G_refAnd G_outValue closer to the inverse being arranged to each other, the counteracting of gain error The best.

Describe the described technology for offsetting the gain error because of parasitic antenna generation with reference to DAC.So And, it will be appreciated by the skilled addressee that these concepts can be applied to other by modifying Electronic installation.

It is various that another aspect of the present disclosure relates to finely tuning in (trim) or correcting electronic device such as DAC Offset error.Figure 11 illustrates the circuit for providing skew fine setting in DAC according to exemplary embodiment Arrange.Electric current I is supplied to be coupled to the resistor 506 of resistor string and resistor 512 by constant-current source 503. The voltage level for finely tuning skew is caused by the flowing of resistor 506 and the electric current of resistor 512.

More specifically, resistor 506 and resistor 512 have some taps.Such as ordinary skill It will be appreciated that such as, in certain embodiments, resistor 506 can have 31 taps to personnel, and Resistor 512 can have 31 taps, but can use the tap of other quantity.In resistor 506 Tap be coupled to switch 509.The lower end of resistor 506 or terminal are used as extra tap, And it is coupled to switch in 509 one.Therefore, provide logical by the electric current flowing of resistor 506 Cross the tap in resistor 506 can some voltage levels.

The tap of resistor 506 is selectively coupled to node 509A by switch 509.Controller 359 is controlled The operation of system switch 509.Specifically, controller 359 can cause one or more switch 509 to be connected. By this way, some voltage levels can be supplied to node 509A by controller 359.Such as, pass through A single switch in ON switch 509, controller 359 may cause being couple to taking out of this switch Voltage level at Tou is available at node 509A.

Similarly, the tap in resistor 512 is coupled to switch 515.The lower end of resistor 512 or end Son is used as extra tap and is coupled to the switch switching in 515.Therefore, pass through The electric current flowing of resistor 512 provides some available voltage levels by the tap in resistor 512.

The tap of resistor 512 is selectively coupled to node 515A by switch 515.Controller 359 is controlled The operation of system switch 515.Specifically, controller 359 can cause one or more switch 515 to be connected. By this way, some voltage levels can be supplied to node 515A by controller 359.Such as, pass through A single switch in ON switch 515, controller 359 can cause being couple to taking out of this switch Voltage level at Tou is available at node 515A.

Resistor 509 is couple to ground wire by switch 518.Therefore, when offseting fine adjustment function and being not used by Or when DAC is not used by etc., switch 518 allows by resistor 506 and 509 from current source 503 Flowing to the current interruptions of ground wire, this causes power consumption to reduce.Controller 359 controls the operation of switch 518.

Voltage at node 509A is used for being finely adjusted the output offset of interpolater 312.More specifically, Voltage at node 509A drives mutual conductance (g_m) level or the input of amplifier 312-2.g_mLevel 312-2's Output electric current is provided to the outfan 312A of interpolater 312.As it has been described above, interpolater 312 includes leading to Cross switching network and receive voltage V_evenAnd V_oddSome g_mLevel (being labeled as 312-1).As response, g_mLevel 312-1 generates output electric current, and these output electric currents are provided to the outfan of interpolater 312 together 312A。

In other words, available at the outfan 312A of interpolater 312 electric current is constituted by g_mLevel 312-1 There is provided electric current and by g_mThe summation of the electric current that level 312-2 provides.By changing by g_mLevel 312-2 provides The value of electric current and/or polarity, the output offset electricity of the output offset of interpolater 312 and therefore DAC Pressure can be trimmed off or offset or approximate counteracting.

In the exemplary embodiment, g_mLevel 312-2 compares g_mLevel 312-1 has lower electric current and drives or drive Kinetic force (or intensity) or transconductance value.Therefore, g_mLevel 312-2 and g_mLevel 312-1 compares less Electric current is injected in node 312A.In other words, can be with the output to interpolater 312 of the finer granularity Skew is finely adjusted.

As set forth above, it is possible to perform the fine setting of the output offset voltage to interpolater 312 in many ways. In certain embodiments, fine setting is performed when product test during test after the process.Based on this A little results, the control level for switch 509 can be stored (such as, in memory), with The fine setting to the skew of interpolater 312 in retrieval further and use.Additionally, as it has been described above, at some In embodiment, as required, during use as periodically or performed when powering on to finely tune and/or root Fine setting is performed according to other schemes.

With reference to Figure 11, the voltage at node 515A is used for finely tuning the output offset of buffer 306.Micro- The output offset adjusting buffer 306 provides fine gains for overall DAC.

Voltage at node 515A is used for being finely adjusted the output offset of interpolater 312.More specifically, Voltage at node 515A drives mutual conductance (g_m) level or the input of amplifier 306-2.g_mLevel 306-2's Output electric current is provided to the outfan 306A of buffer 306.Buffer 306 also includes receiving from contracting The g of the voltage of the outfan 303A on electric discharge road 303_mLevel 306-1.As response, g_mLevel 306-1 generates Output electric current, described output electric current is output a grade 306-3 and is converted to V_ref。

In other words, available at the outfan 306A of buffer 306 electric current is constituted by g_mLevel 306-1 There is provided electric current and by g_mThe summation of the electric current that level 306-2 provides.By changing by g_mLevel 306-2 provides The value of electric current and/or polarity, the overall gain of the output offset of buffer 306 and therefore DAC can To be trimmed off.

In the exemplary embodiment, g_mLevel 306-2 compares g_mLevel 306-1 has lower electric current and drives or drive Kinetic force (or intensity) or transconductance value.Therefore, g_mLevel 306-2 and g_mLevel 306-1 compares less Electric current is injected in node 306A.In other words, can be with defeated to buffer 306 of finer granularity Go out skew to be finely adjusted.

As set forth above, it is possible to perform the fine setting of the output offset voltage to buffer 306 in many ways. In certain embodiments, fine setting is performed when product test during test after the process.Based on this A little results, the control level for switch 515 can be stored (such as, in memory), with The fine setting to the skew of buffer 306 in retrieval further and use.Additionally, as it has been described above, at some In embodiment, as required, during use as periodically or performed when powering on to finely tune and/or root Fine setting is performed according to other schemes.

Such as, according to exemplary embodiment, by DAC and signal processing or counting circuit are integrated in IC In, DAC can be combined with other circuit.Figure 12 according to exemplary embodiment illustrate by DAC with The integrated circuit (IC) 550 that other circuit modules are combined, such as, micro controller unit (MCU).

IC 550 includes some modules (such as, processor 565, the data using link 560 to communicate with one another Transducer 605, I/O circuit 585 etc.).In the exemplary embodiment, link 560 may be constructed and couples Mechanism, be such as used for passing on the bus of information (such as data, order, status information etc.), one group lead Body or quasiconductor.

IC 550 can include being couple to one or more processor 565, clock circuit 575 and power management The link 560 of circuit 580.In certain embodiments, processor 565 can include for providing calculating merit The circuit of energy or module, such as, CPU (CPU), ALU (ALU) etc.. In certain embodiments, additionally or alternatively, processor 565 can include one or more numeral letter Number processor (DSP).As required, DSP can provide various signal processing function, such as arithmetic Function, filtration, Postponement module etc..

Clock circuit 575 can generate and just promote or controlling the operation of the one or more modules in IC 550 Time one or more clock signals.Clock circuit 575 can also control the operation of use link 560 Timing.In certain embodiments, clock circuit 575 can be by link 560 by one or more clocks Signal is supplied to other modules in IC 550.

In certain embodiments, management circuit 580 can reduce device (such as, IC 550) time Clock rate degree, close clock, reduce power, close power or about the part of circuit or the institute of circuit There is above-mentioned every any combination of parts.Further, management circuit 580 can open clock, Increase clock rate, open power, increase power or in response to from unactivated state to state of activation Change (such as when processor 565 is made from low-power or idling or sleep state to normal operating state During transformation) carry out above-mentioned every any combination.

Link 560 can be couple to one or more circuit 600 by serial line interface 595.Pass through serial interface Mouth 595, the one or more circuit being couple to link 560 can communicate with circuit 600.As this area is general Leading to and skilled artisan will appreciate that, circuit 600 can use one or more serial protocol such as SMBUS, I₂C、 SPI etc. communicate.

Link 560 can be couple to one or more ancillary equipment 590 by I/O circuit 585.Pass through I/O Circuit 585, one or more ancillary equipment 590 can be couple to link 560, and therefore can be with coupling Other modules such as (multiple) processor 365, memory circuitry 625 etc. receiving link 560 communicate.

In the exemplary embodiment, ancillary equipment 590 can include various circuit, module etc..Example bag Include I/O equipment (keypad, keyboard, speaker, display device, storage device, timer etc.).Should Noting, in certain embodiments, some ancillary equipment 590 can be outside IC 550.Example includes little Keyboard, speaker etc..

In certain embodiments, relative to some ancillary equipment, I/O circuit 585 can be bypassed.At this In the embodiment of sample, some ancillary equipment 590 can be couple to link 560 and communicate with link 560 and Do not use I/O circuit 585.It should be noted that as it has been described above, in certain embodiments, such ancillary equipment It can be the outside at IC 550.

Link 560 can be couple to analog circuit 620 by data converter 605.Data converter 405 One or more ADC 615 and/or one or more DAC 200 can be included.ADC 615 is from simulation Circuit 620 receives analogue signal, and converts analog signals into number format, so they with couple One or more module communications to link 560.

On the contrary, (multiple) DAC 200 receives one from the one or more modules being couple to link 560 Or multiple digital signal, and (multiple) digital signal is converted to analog format.As required, (many Individual) circuit (such as, analog circuit 620) that can be provided in IC 550 of analogue signal or IC 550 Outside circuit.

Analog circuit 620 can include the various circuit providing and/or receiving analogue signal.As this area is general Leading to and skilled artisan will appreciate that, example includes sensor, transducer etc..In certain embodiments, according to need , analog circuit 620 can be with the circuit communication outside IC 550, to form more complicated system, son System, control module and message processing module.

Control circuit 570 is couple to link 560.Therefore, control circuit 570 can be couple to link The various module communications of 560 and/or control are couple to the operation of the various modules of link 560.Additionally or make For substituting, control circuit 570 can promote communication or the conjunction being couple between the various modules of link 560 Make.In certain embodiments, as required, (such as, the above-mentioned control of the control circuit in DAC 200 Device 359) function or circuit can be with the function of control circuit 570 or line combination, or DAC 200 In the function of control circuit (such as, controller noted above 359) or circuit can be contained in control circuit In the function of 570 or circuit.

Referring again to Figure 12, in certain embodiments, control circuit 570 can start or respond reset behaviour Make.As it will be appreciated by the skilled addressee that, the operation that resets can cause being couple to the link of IC 550 One or more modules of 560 etc. reset.Such as, control circuit 570 can cause (multiple) DAC 200 Reset to original state.

In the exemplary embodiment, control circuit 570 can include various types of circuit and various circuit Module.In certain embodiments, control circuit 570 can include logic circuit, finite state machine (FSM) Or other circuit, to perform various operation, such as operations described above.

Telecommunication circuit 640 is couple to link 560, and also is couple to the circuit outside IC 550 or module (not shown).By telecommunication circuit 640, it is couple to link 560 (or in general IC 550) Various modules can be communicated with external circuit or module (not shown) by one or more communication protocols. Example includes USB (universal serial bus) (USB), Ethernet etc..As it will be appreciated by the skilled addressee that In the exemplary embodiment, according to some factors such as the specification of given application, it is possible to use other Communication protocol.

As it has been described above, memory circuitry 625 is couple to link 560.Therefore, memory circuitry 625 is permissible Be couple to link 560 one or more modules such as (multiple) processor 365, control circuit 570, I/O circuit 585 communication such as grade.In an illustrated embodiment, memory circuitry 625 include control circuit 610, Memory array 635 and DASD (DMA) 630.

Control circuit 610 controls or supervises the various operations of memory circuitry 625.Such as, control circuit 619 can provide a kind of mechanism to perform memorizer read or write operation by link 360.Exemplary In embodiment, as required, control circuit 610 can support various agreement, such as double data rate (DDR), DDR2, DDR3 etc..

In certain embodiments, memorizer read and/or be directed to use with in IC 550 one of write operation or Multiple modules such as (multiple) memorizer 565.DMA 630 allows to improve in some cases memorizer The performance of operation.More specifically, DMA 630 provide for directly data source or data destination with Between memory circuitry 625 rather than perform memorizer by module such as (multiple) processor 565 to read Go out the mechanism with write operation.

Memory array 635 can include various memory circuitry or module.In an illustrated embodiment, Memory array 635 includes volatile memory 635A and non-volatile (NV) memorizer 635B.? In some embodiments, memory array 635 can include volatile memory 635A.In some embodiments In, memory array 635 can include NV memorizer 635B.

NV memorizer 635B can be used for storage with IC 550 in one or more modules performance or The information that configuration is relevant.Such as, as it has been described above, NV memorizer 635B can store and (multiple) DAC The configuration information that the skew of 200 or fine gains are correlated with.

According to exemplary embodiment, there is the DAC of the most above-mentioned advantage may certify that and be in various applications Useful.Example includes the application specifying some or all of attribute listed above, and described attribute is such as Monotonicity and relatively high resolution such as 12.

The application of a kind of example includes the data handling utility processing analog input signal, such as the circuit in Figure 13 Arrange that 700 are described.More specifically, process circuit 705 (or in general derived digital signal, such as, MCU, CPU, microprocessor etc.) digital signal is provided at outfan 705A.Digital signal is carried Supply DAC 200.This digital signal is converted to analogue signal and at outfan 221 by DAC 200 Described analogue signal is provided.Analogue signal flow into simulation destination 710 (such as, transducer, driver, Amplifier etc.).Therefore, digitized source such as processes circuit 708 DAC 200 can be used to control mould Intend destination 710 or communicate with simulation destination 710.

In another kind is applied, can be used for implementing such as Figure 14 institute according to the DAC of exemplary embodiment The control system 750 shown.Control system 750 includes that process 765, described process 765 include simulation source 755 With simulation destination 710.Analogue signal is supplied to ADC by simulation source 755 such as sensor or transducer 760.ADC 760 converts analog signals into digital signal and digital signal is supplied to control circuit 760。

Such as, control circuit 760 processes digital signal by filter, amplify or scale, delay etc..Control Circuit 760 processed provides digital output signal and described digital output signal is supplied to DAC 200.DAC The digital output signal of control circuit 760 is converted to analogue signal by 200, and described analogue signal is at outfan It is available at 221.Analogue signal at the output of DAC 200 is provided to simulate destination, Such as, transducer, driver, motor or other electromechanical equipments etc..Therefore, shown in system 750 The combination of module realizes a feedback control loop.

In general, according to various embodiments, feedback control loop (such as, servosystem) uses one Individual or multiple DAC application can be benefited from using DAC.Figure 15 is exemplified with illustrating such configuration Circuit arrangement 780.More specifically, feedback control loop includes the source that output signal is supplied to control circuit 760 785.As response, control circuit 760 generates digital signal and described digital signal is supplied to DAC 200。

DAC 200 changes the digital signal received from control circuit 760 and generates mould at outfan 221 Intend signal.The analog output signal of DAC 200 flows into driver 790.Driver 790 (such as, is passed through One or more driving signal is provided) drive source 785, so complete loop.

The more specifically example using the feedback control loop of DAC according to exemplary embodiment can be communication system. More specifically, DAC can be used in the feedback loop to control the light source of use in optical communication system Intensity.Figure 16 is shown with this type of communication system 800 of the program.

More specifically, communication system 800 includes source 805, medium 830 and destination 835.It is typically to send out Information signal is supplied to medium 830 by the source 805 of emitter (or transceiver), such as, and optical fiber or optical fiber Set.Described information is supplied to destination 835 by medium 830, destination 835 be typically receptor (or Transceiver) and it is usually located at the distant place in source 805.

In an illustrated embodiment, source 805 includes that laser instrument 810, laser instrument 810 generate light beam and by light Bundle is supplied to beam splitter 815.It should be noted that the extra circuit module (not shown) information pair that generally uses Light beam from laser instrument 810 is modulated (opening and closing according to digital bit pattern).As it has been described above, A part for input light from laser instrument 810 is supplied to medium 830 by beam splitter 815, and medium 830 will Light is supplied to destination 835.

It addition, a part for the input light from laser instrument 810 is supplied to controller 820 by beam splitter 815. In other words, controller 820 receives the instruction optical signal from the intensity of the light beam of laser instrument 810 output. In response to the input light from beam splitter 815, controller 820 generates digital signal, described digital signal It is eventually used to drive laser instrument 810.

More specifically, DAC 200 will be converted to analogue signal from the digital signal of controller 820, This analogue signal is provided at outfan 221.The analog output signal of DAC 200 flows into driver 825.Make For response, bias is supplied to laser instrument 810 by driver 825, has the phase to promote laser instrument 810 to provide Hope the output beam of intensity.

As it has been described above, by receiving signal from beam splitter 815, controller 820 receives laser instrument 810 and carries Estimating of the intensity of the light beam of confession.By by the signal from beam splitter 815 compared with reference signal, Digital signal is supplied to DAC 200 by controller 820, and this ultimately results in driver 825 increases or drop The low bias being supplied to laser instrument 810, in order to regulate the intensity of the output light from laser instrument 810.

With reference to accompanying drawing, those of ordinary skill in the art are it will be noted that shown various modules can mainly be described Conceptual function and signal stream.Side circuit embodiment can comprise or can not comprise for various The independent discernible hardware of functional module, and can use or shown particular electrical circuit can not be used. Such as, as required, can be by the function combinations of various modules a to circuit module.Additionally, root According to needs, the function of individual module can be realized in several circuit modules.The selection of circuit implementation Depend on various factors, such as particular design and the specification of given embodiment.Except Other amendments and alternate embodiment beyond these those described to those skilled in the art will It is apparent from.Therefore, this specification instructs those skilled in the art to implement the side of disclosed concept Formula, and should be read as only having illustrative.As it will be appreciated by the skilled addressee that applicable In the case of, accompanying drawing can be drawn to scale or can be not drawn to scale.

Illustrated should be considered illustrative embodiment with described form and embodiment.This area skill The shape of part, size and layout can be made various change by art personnel, without departing from institute in this article The protection domain of disclosed concept.Such as, those skilled in the art can replace institute here with equivalence element The element illustrated and describe.Additionally, in the case of the protection domain without departing from disclosed concept, this Skilled person can be independent of some feature made for using disclosed concept of other features.

Claims (20)

1. a device, comprising:

Digital analog converter i.e. DAC, digital input signals is converted to analog output signal by it, described DAC includes:

Decoder, it is decoded and provides first group of control signal and to described digital input signals Two groups of control signals；

Resistor DAC i.e. RDAC, its in response to described first group of control signal provide the first voltage and Second voltage；And

Interpolater, its be coupled in response to described second group of control signal receive described first voltage and Described second voltage also provides the first analogue signal.

Device the most according to claim 1, wherein said DAC provides the described simulation with monotonicity Output signal.

Device the most according to claim 1, wherein said RDAC includes being couple to the first switching network Resistor network, described first switching network includes that first group controlled by described first group of control signal is opened Close.

Device the most according to claim 3, wherein by described decoder by described numeral input letter Number higher significance bit i.e. MSB be decoded generating described first group of control signal.

Device the most according to claim 4, wherein said decoder includes binary decoder, described The described MSB of described digital input signals is decoded generating described first group of control by binary decoder Signal.

Device the most according to claim 1, wherein said interpolater includes being couple to multiple interpolator stage Second switch network, described second switch network includes second group controlled by described second group of control signal Switch.

Device the most according to claim 6, wherein by described decoder by described numeral input letter Number relatively low order i.e. LSB be decoded generating described second group of control signal.

Device the most according to claim 7, wherein said decoder includes Thermometer-decoder, described The described LSB of described digital input signals is decoded generating described first group of control by Thermometer-decoder Signal.

Device the most according to claim 6, farther includes output stage, and described output stage is couple to institute State interpolater to receive described first analogue signal and to provide described analog output signal.

10. a device, comprising:

Digital analog converter i.e. DAC, comprising:

Current Sources, it includes that multiple current source is to provide multiple electric currents；

First switching network, its plurality of current selective ground that will be provided by the plurality of current source It is supplied to primary nodal point or secondary nodal point；

Resistor network, it is coupled to provide output signal, and described resistor network includes multiple electricity Resistance device；And

Second switch network, it is coupled to described resistor network with by the institute of described resistor network State the resistor in multiple resistor and be selectively coupled to described primary nodal point and described secondary nodal point.

11. devices according to claim 10, wherein said DAC provides has the described defeated of monotonicity Go out signal.

12. devices according to claim 10, wherein said first switching network includes that multiple switch is right, The plurality of switch respective current sources to being coupled in described Current Sources, with will be by the plurality of electricity It is supplied to described primary nodal point or described secondary nodal point the described current selective that stream source provides.

13. devices according to claim 10, wherein said first switching network include being coupled to from The switch that current source in described Current Sources receives electric current is right, and electric current is uniform in described switch centering Ground flowing is to increase the resolution of described DAC.

14. devices according to claim 10, wherein said resistor network is coupled in described DAC Outfan and the ground nodes of described DAC between.

15. 1 kinds of methods converting digital signals into analogue signal, described method includes:

It is decoded described digital signal generating first group of control signal and second group of control signal；

In response to described first group of control signal, by using resistor DAC i.e. RDAC to provide the first voltage With the second voltage；And

In response to described second group of control signal, described first voltage and described second voltage are carried out interpolation with First analogue signal is provided.

16. methods according to claim 15, wherein perform digital signal to analogue signal with monotonicity Conversion.

17. methods according to claim 15, wherein use described RDAC to provide described first voltage Include with described second voltage, in response to described first group of control signal, by the resistor in resistor network It is selectively coupled to that there is described first voltage and the node of described second voltage.

18. methods according to claim 17, wherein are decoded wrapping further to described digital signal Include the higher significance bit i.e. MSB to described digital signal to be decoded generating described first group of control signal.

19. methods according to claim 15, wherein enter described first voltage and described second voltage Row interpolation includes, in response to described second group of control signal, by described first voltage and described second voltage choosing Selecting property it is supplied to multiple interpolator stage.

20. methods according to claim 19, wherein are decoded wrapping further to described digital signal Include the relatively low order i.e. LSB to described digital signal to be decoded generating described second group of control signal.