CN106253655A - DC DC changer adaptive dead zone based on zero voltage start-up produces circuit - Google Patents

Abstract

The invention belongs to electronic circuit technology field, relate to DC DC changer adaptive dead zone based on zero voltage start-up and produce circuit.This adaptive dead zone is produced circuit and is sampled the load current of DC DC changer by current sampling circuit, and changes into information of voltage, obtains the sampled voltage input voltage as integrator circuit；The integration of integrator circuit is controlled by integral control circuit；Last waveform processing circuit obtains the power tube grid containing adaptive dead zone after processing the output waveform of integrator circuit and drives signal.Beneficial effects of the present invention is, effectively can provide optimum Dead Time for power tube adaptively according to the load situation of change of DC DC changer, it is ensured that the no-voltage of power tube is opened.Compared with this circuit fixes dead-zone circuit with tradition, the conduction loss of its switching tube is approximately zero, and output waveform is more stable under different loading conditions, can be effectively improved the efficiency of DC DC changer.

Description

A DC-DC Converter Adaptive Dead Zone Generation Circuit Based on Zero Voltage Startup

technical field

The invention belongs to the technical field of electronic circuits, and relates to a DC-DC converter self-adaptive dead zone generation circuit based on zero-voltage startup.

Background technique

In the DC-DC converter, the on-resistance of the power tubes is very small. If two power tubes are turned on at the same time, there will be a low-resistance path from the power supply to the ground, and the current flowing through the power tubes will be very large. The current can reach The ampere level will greatly increase the power consumption of the chip, and in severe cases, the power tube and even the entire chip will be seriously damaged. Therefore, a dead time is generally added between the two power tubes to prevent simultaneous conduction of the high and low end power tubes of the same arm during operation. The usual practice is to use a fixed length of dead time, which has the advantages of convenient and simple design and high reliability, but its disadvantages are also obvious: fixed dead time will cause high and low power tubes to be turned off for a long time at the same time under light load. In this case, it will affect the driven load voltage and current waveform, which will further lead to problems of low efficiency and poor stability.

Contents of the invention

What the present invention aims to solve is to propose an adaptive dead zone generation circuit for a DC-DC converter based on zero-voltage startup.

To achieve the above object, the present invention adopts the following technical solutions:

DC-DC converter adaptive dead zone generation circuit based on zero-voltage startup, including load current sampling circuit, integrator circuit, integral control circuit and waveform processing circuit; the input terminal of load current sampling circuit is connected to the output of DC-DC converter The output terminal of the voltage and load current sampling circuit is connected to the first input terminal of the integrator circuit; the second input terminal of the integrator circuit is connected to the output terminal of the integral control circuit, and the third input terminal of the integrator circuit is connected to the PWM input signal, and the integrator The output terminal of the circuit is connected to the first input terminal of the waveform processing circuit and the first input terminal of the integral control circuit; the second input terminal of the integral control circuit is connected to the PWM input signal; the second input terminal of the waveform processing circuit is connected to the PWM input signal, and the waveform The output terminal of the processing circuit outputs a gate driving signal including an adaptive dead time.

Wherein the PWM input signal is the power tube grid control signal without dead time in the DC-DC converter, and the output of the waveform processing circuit is the output signal of the present invention.

In the general technical solution of the present invention, the load current of the DC-DC converter is sampled by the current sampling circuit, and converted into voltage information, and the sampled voltage is obtained as the input voltage of the integrator circuit, and the integral control circuit carries out integration of the integrator circuit. control, and finally the waveform processing circuit processes the output waveform of the integrator circuit to obtain a power tube gate drive signal with an adaptive dead zone.

The load current sampling circuit is composed of a third resistor RL, a fourth resistor Rsense and an operational amplifier; one end of the third resistor RL is connected to the output end of the DC-DC converter, and the other end of the third resistor RL is connected to the fourth resistor Rsense The other end of the fourth resistor Rsense is grounded; the positive input terminal of the operational amplifier is connected to the common terminal of the third resistor RL and the fourth resistor Rsense, its negative input terminal is short-circuited with the output terminal, and the output terminal of the operational amplifier is said The output end of the load current sampling circuit;

The waveform processing circuit is composed of the third comparator COMP3, the fourth comparator COMP4, two-input AND gate AND2, and two-input OR gate OR3; the positive input terminal of the third comparator COMP3 is connected to the bias voltage signal Vref3, and its negative The input terminal is connected to the output terminal of the integrator circuit, and its output terminal is connected to the first input terminal of the two-input AND gate AND2; the positive input terminal of the fourth comparator COMP4 is connected to the output terminal of the integrator circuit, and its negative input terminal is connected to the bias voltage Signal Vref4, its output terminal is connected to the second input terminal of the two-input OR gate OR3; the second input terminal of the two-input AND gate AND2 is connected to the PWM signal, and its output terminal is the first output terminal of the waveform processing circuit; the two-input OR The first input terminal of the gate OR3 is connected to the PWM signal, and the output terminal thereof is the second output terminal of the waveform processing circuit.

Further, the integrator circuit is composed of a first resistor R1, a second resistor R2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a capacitor C and an operational amplifier; one end of the first resistor R1 is connected to the output end of the load current detection circuit, and the other end is connected to the drain end of the first NMOS transistor MN1; one end of the second resistor R2 is connected to the drain end of the second PMOS transistor MP2, The other end is grounded; the gate of the first NMOS transistor MN1 is connected to the PWM signal, and its source is connected to the drain of the second NMOS transistor MN2; the gate of the second NMOS transistor MN2 is connected to the output Vc of the integral control circuit, and its source is connected to The negative input terminal of the operational amplifier; the gate of the third NMOS transistor MN3 is connected to the PWM signal, its source is grounded, and its drain is connected to the positive input terminal of the operational amplifier; the gate of the first PMOS transistor MP1 is connected to the PWM signal, and its source connected to the output terminal of the load current detection circuit, its drain connected to the positive input terminal of the operational amplifier; the gate of the second PMOS transistor MP2 connected to the PWM signal, its source connected to the source of the first NMOS transistor MN1, and its drain connected to the ground; The positive plate of the capacitor C is connected to the negative input terminal of the operational amplifier, and its negative plate is connected to the output of the operational amplifier; the output terminal of the operational amplifier is the output terminal of the integrator circuit.

Further, the integral control circuit is composed of a first comparator COMP1, a second comparator COMP2, an inverter INV, a first two-input OR gate OR1, a second two-input OR gate OR2, and a two-input AND gate AND1; The positive input terminal of a comparator COMP1 is connected to the bias voltage signal Vref1, its negative input terminal is connected to the output terminal of the integrator circuit, and its output terminal is connected to the first input terminal of the first two-input OR gate OR1; the second comparator COMP2 The positive input terminal is connected to the output terminal of the integrator circuit; its negative input terminal is connected to the bias voltage signal Vref2, and its output terminal is connected to the second input terminal of the second two-input OR gate OR2; the input terminal of the inverter INV is connected to the PWM signal, Its output terminal is connected to the first input terminal of the second two-input OR gate OR2; the second input terminal of the first two-input OR gate OR1 is connected to the PWM signal, and its output is connected to the first input terminal of the two-input AND gate AND1; The output terminal of the input OR gate OR2 is connected to the second input terminal of the two-input AND gate AND1; the output terminal of the two-input AND gate AND1 is the output Vc of the integral processing circuit.

Further, the bias voltages Vref1, Vref2, Vref3 and Vref4 have the following relationship, Vref1>Vref4>Vref3>Vref2; and (Vref1-Vref2)>2|Vref3-Vref2| and Vref1-Vref4=Vref3-Vref2; Vref1 The values of –Vref4 and Vref3 –Vref2 are determined by the output voltage of the DC-DC converter, the equivalent capacitance of the SW point, and the size of the integral capacitance C. Specifically, the product of Vref1-Vref4 and the integral capacitance is equal to the equivalent capacitance of the SW point and The product of the output voltage of the DC-DC converter, where the potential of the SW point is the common drain potential of the two switching power transistors in the DC-DC converter.

The beneficial effect of the present invention is that it can effectively and adaptively provide the optimal dead time for the power tube according to the load variation of the DC-DC converter, so as to ensure the zero-voltage turn-on of the power tube. Compared with the traditional fixed dead zone circuit, the conduction loss of the switching tube is approximately zero, and the output waveform is more stable under different load conditions, which can effectively improve the efficiency of the DC-DC converter.

Description of drawings

Fig. 1 is the structural block diagram of the DC-DC converter self-adaptive dead zone circuit based on zero voltage startup of the present invention;

Figure 2 is a schematic diagram of the load current sampling circuit;

Fig. 3 is the schematic diagram of the integrator circuit;

Figure 4 is a schematic diagram of the integral control circuit;

Fig. 5 is a schematic diagram of the waveform processing circuit;

FIG. 6 is a schematic waveform diagram of an adaptive dead zone circuit of a DC-DC converter based on zero voltage startup.

detailed description

Fig. 1 is the structural block diagram of the DC-DC converter self-adaptive dead zone circuit structure based on zero voltage startup of the present invention, as shown in Fig. 1, the load current sampling circuit samples the load current of the DC-DC converter and uses the sampled current signal as Input to the Integrator Circuit. The integrator circuit uses this current as the charging and discharging current of the integrating capacitor C, and its charging, discharging, and stop charging and discharging states are jointly controlled by the PWM signal and the Vc signal, where the Vc signal is determined by the integral control unit through logic after the integral state of the integrator produce. After the above steps, the integrator module inputs the output trapezoidal voltage signal to the waveform processing circuit, and the slope of the trapezoidal voltage signal is determined by the magnitude of the load current of the DC-DC converter, so it is adaptive. Finally, the waveform processing circuit processes the trapezoidal voltage signal to generate the upper and lower power tube grid driving signals with adaptive dead zones. The present invention designs the mentioned load current sampling circuit, integrator circuit, integral control circuit and waveform processing circuit.

Fig. 2 Schematic diagram of the load current sampling circuit, RL is the load of the DC-DC converter, Rsense is the sampling resistor, and the resistance value of the resistor Rsense should be much smaller than that of the resistor RL. According to the principle of virtual short and virtual break of the operational amplifier, the output voltage Vsense of the current sampling circuit is the voltage at both ends of the sampling resistor Rsense. In the subsequent circuit, a resistor with the same resistance value as Rsense can be connected to the output terminal of the load current sampling circuit. To obtain a current equivalent to the load current of the DC-DC converter, that is, to complete the sampling of the load current.

Figure 3 and Figure 4 are the schematic diagrams of the integrator circuit and the integral control circuit respectively, the initial value of Vc is set to be high level, when the PWM is high level, the MN1, MN2 and MN3 tubes in the integrator circuit are turned on, and the operation The positive input terminal of the amplifier is grounded. According to the principle of virtual short and virtual break, its negative input terminal is also at 0 potential. The voltage Vsense is converted into a current equivalent to the load current of the DC-DC converter through the resistor R1 and charges the capacitor. At this time, Vout starts to discharge. When Vout is lower than the voltage Vref2, the second comparator in the integral control circuit outputs COMP2 output a low level to the second input end of the second two-input OR gate OR2, so that the second two-input OR gate OR2 outputs a low level, and finally Vc is set to a low level after passing through the two-input AND gate AND1, and the MN2 tube is cut off. The discharge stops. At this time, PWM is still at a high level, and before its low level comes, the capacitor is neither charged nor discharged. When PWM is low level, the first two-input OR gate OR1 and the second two-input OR gate OR2 of the integral control circuit both output high level, and Vc is reset to high level at this time. The tubes MN2, MP1 and MP2 in the integrator circuit are turned on, and the positive input terminal of the operational amplifier is connected to the potential Vsense. According to the principle of virtual short and virtual break, its negative input terminal is also at the potential of Vsense, and the voltage Vsense of the negative input terminal is connected to the potential Vsense through the resistor R2. After grounding, it is converted into a current equivalent to the load current of the DC-DC converter and discharges the capacitor. At this time, Vout starts to discharge. When Vout is higher than the voltage Vref1, the first comparator COMP1 in the integral control circuit outputs a low level to The first input terminal of the first two-input OR gate OR1 makes the first two-input OR gate OR1 output a low level, and finally Vc is set to a low level after passing through the two-input OR gate, the MN2 tube is turned off, and the charging stops. At this time, PWM is still at low level, and before its high level comes, the capacitor is neither charged nor discharged. When PWM becomes high level, the first two-input OR gate OR1 and the second two-input OR gate OR2 of the integral control circuit both output high level, at this time Vc is reset to high level, that is, returns to the initial assumed value; Wherein the bias voltage signal Vref1 is greater than the bias voltage signal Vref2, and (Vref1-Vref2)>2|Vref3-Vref2|. Thus, through the integrator circuit and the integral control circuit, the forward integral, reverse integral, and terminated integral of the integral signal can be controlled, and then the required standard trapezoidal wave can be obtained to prepare for the next wave processing.

Figure 5 is a schematic diagram of the waveform processing circuit, and Figure 6 is a schematic diagram of the waveform of the DC-DC converter adaptive dead zone circuit based on zero-voltage startup. The input terminal of the waveform processing circuit is connected to the output of the integrator circuit, which is the output of the integrator circuit in Figure 6. Integral signal. As shown in Figure 6, the waveform processing circuit processes the integral signal as follows: when the PWM signal is at a high level and the voltage value of the integral signal is higher than the bias voltage Vref3, the first output terminal GH of the waveform processing circuit outputs a high level, Output low level in other cases; when the PWM signal is high level or the integrated signal voltage value is higher than the bias voltage Vref4, the second output terminal GL of the waveform processing circuit outputs high level, and outputs low level in other cases; The set voltage signal Vref4 is greater than the bias voltage signal Vref3, that is, Vref1>Vref4>Vref3>Vref2, and Vref1−Vref4=Vref3−Vref2. In order to ensure the zero-voltage turn-on of the power tube, the values of Vref1–Vref4 and Vref3–Vref2 are determined by the output voltage of the DC-DC converter, the equivalent capacitance of the SW point, and the size of the integral capacitor C, specifically expressed as Vref1-Vref4 and the integral The product of the capacitance is equal to the product of the equivalent capacitance of the SW point and the output voltage of the DC-DC converter. Through the waveform processing circuit, the power tube gate drive signals GH and GL with adaptive dead time tdr and tdf are generated. According to different load conditions, the dead time tdr and tdf will change adaptively. In the figure, load1 and load2 are For two different load conditions, since the input integral current of the integrator circuit is the sampling current for the load current of the DC-DC converter, the slope of the integral trapezoidal signal changes due to the change of the load condition. Thus, in the case of load1, the resulting dead zone lengths are tdr1 and tdf1; in the case of load load2, the resulting dead zone lengths are tdr2 and tdf2.

Claims (4)

1. DC-DC converter adaptive dead zone based on zero voltage start-up produces circuit, including load current sample circuit, integration Device circuit, integral control circuit and waveform processing circuit；The output of the input termination DC-DC converter of load current sample circuit Voltage, the first input end of the output termination integrator circuit of load current sample circuit；Second input of integrator circuit Connect the outfan of integral control circuit, the 3rd input termination PWM input signal of integrator circuit, the outfan of integrator circuit Welding wave processes first input end and the first input end of integral control circuit of circuit；Second input of integral control circuit Connect PWM input signal；Second input termination PWM input signal of waveform processing circuit, the outfan output of waveform processing circuit Grid containing the adaptive dead zone time drive signal；

Described load current sample circuit is made up of the 3rd resistance RL, the 4th resistance Rsense and operational amplifier；3rd electricity The outfan of the one termination DC-DC converter of resistance RL, one end of another termination the 4th resistance Rsense of the 3rd resistance RL；4th The other end ground connection of resistance Rsense；Positive input termination the 3rd resistance RL's and the 4th resistance Rsense of operational amplifier is public End, its negative input end and outfan short circuit, the outfan of operational amplifier is the outfan of described load current sample circuit；

Described waveform processing circuit is by the 3rd comparator COMP3, the 4th comparator COMP4, two inputs and door AND2, two inputs Or door OR3 is constituted；The positive input termination biasing voltage signal Vref3 of the 3rd comparator COMP3, its negative input termination integrator electricity The outfan on road, its output termination two input and first input end of door AND2；The positive input termination of the 4th comparator COMP4 is long-pending Divide the outfan of device circuit, its negative input termination biasing voltage signal Vref4, its output termination two input or the second of door OR3 Input；Two inputs and the second of door AND2 the input termination pwm signal, its outfan is the first defeated of described waveform processing circuit Go out end；The first input end of two inputs or door OR3 connects pwm signal, and its outfan is the second output of described waveform processing circuit End.

DC-DC converter adaptive dead zone based on zero voltage start-up the most according to claim 1 produces circuit, its feature Be, described integrator circuit by the first resistance R1, the second resistance R2, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the first PMOS MP1, the second PMOS MP2, electric capacity C and operational amplifier are constituted；One end of first resistance R1 Connect the outfan of load current detection circuit, its another terminate the drain terminal of the first NMOS tube MN1；One termination the of the second resistance R2 The drain terminal of two PMOS MP2, its other end ground connection；The grid of the first NMOS tube MN1 connects pwm signal, and its source electrode meets the 2nd NMOS The drain terminal of pipe MN2；The grid of the second NMOS tube MN2 meets the output Vc of integral control circuit, and its source electrode connects the negative of operational amplifier Input；The grid of the 3rd NMOS tube MN3 connects pwm signal, its source ground, and its drain electrode connects the positive input terminal of operational amplifier； The grid of the first PMOS MP1 connects pwm signal, and its source electrode connects the outfan of load current detection circuit, and its drain electrode connects computing and puts The positive input terminal of big device；The grid of the second PMOS MP2 connects pwm signal, and its source electrode connects the source electrode of the first NMOS tube MN1, its leakage Pole ground connection；Electric capacity C positive plate connects the negative input end of operational amplifier, and its negative plate connects the output of operational amplifier；Operation amplifier The outfan of device is the outfan of described integrator circuit.

DC-DC converter adaptive dead zone based on zero voltage start-up the most according to claim 2 produces circuit, its feature Be, described integral control circuit by the first comparator COMP1, the second comparator COMP2, phase inverter INV, first liang input or Door OR1, second liang of input or door OR2, two inputs are constituted with door AND1；The positive input termination biased electrical of the first comparator COMP1 Pressure signal Vref1, the outfan of its negative input termination integrator circuit, its first liang of input of output termination or the first of door OR1 Input；The outfan of the positive input termination integrator circuit of the second comparator COMP2；Its negative input termination biasing voltage signal Vref2, its second liang of input of output termination or second input of door OR2；The input termination pwm signal of phase inverter INV, it is defeated Go out termination second liang input or the first input end of door OR2；First liang of input or the second input termination pwm signal of door OR1, its Output connects the first input end of two inputs and door AND1；Output termination two input of second liang of input or door OR2 is with door AND1's Second input；Two inputs and the output Vc that outfan is described Integral Processing circuit of door AND1.

DC-DC converter adaptive dead zone based on zero voltage start-up the most according to claim 3 produces circuit, its feature Being, described bias voltage Vref1, Vref2, Vref3 and Vref4 have following relation, Vref1 > Vref4 > Vref3 > Vref2；And (Vref1-Vref2) > 2 | Vref3-Vref2 | and Vref1 Vref4=Vref3 Vref2；Vref1 Vref4 with The value of Vref3 Vref2 is determined by the size of the output voltage of DC-DC converter, SW point equivalent capacity and integrating capacitor C, It is embodied in the Vref1-Vref4 product with integrating capacitor equal to SW point equivalent capacity and DC-DC converter output voltage Product.