CN106251905A - Multi-port SRAM module and control method thereof - Google Patents

Abstract

The invention discloses a multiport SRAM module and its control method, the module includes: a memory cell array including a plurality of rows of memory cells, each memory cell including at least a first control port and a second control port; a first word line coupled to a plurality of memory cells in a target row for controlling whether the first control port is turned on; a second word line coupled to the memory cells of the target row for controlling whether the second control port is turned on; and a switch element coupled to the first word line and the second word line for determining whether to couple the second word line to a reference potential according to the potential of the first word line.

Description

Multi-port SRAM module and its control method

technical field

The present invention relates to static random access memory (static random access memory, referred to as SRAM), in particular to multi-port (multi-port) SRAM module.

Background technique

FIG. 1 is a circuit diagram of a conventional dual port (dualport) SRAM module. The figure shows a plurality of dual-port memory cells 110 located in the same row in the memory cell array of the dual-port SRAM module, and these dual-port memory cells 110 are connected to the same set of word lines (word line) WLA and WLB, but Each is connected to a different bit line pair PBLA and bit line pair PBLB, each of which actually includes two bit lines. 2 is a circuit diagram of a dual-port memory unit 110, usually implemented with 8 transistors, 4 of which constitute a latch 112, and two transistors 113 and 114 constitute one of the ports of the dual-port memory unit 110 , which is connected to the word line WLA to control whether the latch is connected to the bit line pair PBLA (composed of bit lines BLA and /BLA), and the other two transistors 115 and 116 constitute another port, which is connected to the word line The bit line WLB is connected to control whether the latch is connected to the bit line pair PBLB (composed of bit lines BLB and /BLB). Returning to FIG. 1, the word lines WLA and WLB are respectively driven by inverters 120 and 130, the output of the inverter 120 is coupled to one of the ports of the dual-port memory unit 110, and the output of the inverter 130 is coupled to Another port of the dual-port memory unit 110 . The benefit of dual-port SRAM is to increase the access speed of SRAM, but it faces some disadvantages at the same time, such as (a) when a dual-port memory unit 110 is simultaneously read through the bit line pair PBLA and PBLB, it will cause damage to The 2 times read disturbance (read disturbance) of the latch makes the read static noise margin (read static noisemargin, referred to as RSNM) worse; (b) simultaneously read and write to a dual-port memory unit 110 During operation, the write current competes with the read current, making the write margin worse; (c) when the two word lines WLA and WLB of the same column are turned on at the same time, the dual-port in the data saving state The possibility of data loss of the latch due to the increased leakage current of the memory unit 110 increases.

Contents of the invention

In view of the shortcomings of the prior art, an object of the present invention is to provide a multi-port SRAM module and a control method of the multi-port SRAM module, so as to improve the stability of read and/or write operations.

The invention discloses a multi-port SRAM module, comprising: a memory cell array, including multiple columns of memory cells, each memory cell includes at least a first control port and a second control port; a first word line , coupled to a plurality of memory cells of a target row, used to control whether the first control port is open; a second word line, coupled to a plurality of memory cells of the target row, used to control the second control port whether the port is open; and a switch element, coupled to the first word line and the second word line, which determines whether to couple the second word line to a reference potential according to the potential of the first word line ; Wherein, when the first word line is disabled and the second word line is enabled, the second word line has a first enable potential, when the first word line and the second word line When the lines are simultaneously enabled, the second word line has a second enable potential different from the first enable potential. For example, the first enabling potential is greater than the second enabling potential; or the first enabling potential can also be lower than the second enabling potential.

The present invention also discloses a multi-port SRAM module, which is characterized in that it includes: a memory cell array, including multiple columns of memory cells, each memory cell includes at least a first control port and a second control port ; a first word line, coupled to a plurality of memory cells of a target row, used to control whether the first control port is opened; a second word line, coupled to a plurality of memory cells of the target row, used to control whether the second control port is turned on; and a detection circuit, coupled to the first word line and the second word line, for detecting the potential of the first word line and the second word line , to generate a detection result; wherein, the detection result is used to change the voltage of the memory cells of the target column, or to change a bit connected to the first control port or the second control port The voltage of the element line.

The invention also discloses a control method of a multi-port SRAM module, the multi-port SRAM module includes a first word line and a second word line, the first word line and the second word line are respectively used To control whether a first control port and a second control port of a plurality of memory cells in the same row are turned on, the control method includes: changing the potential of the second word line according to the potential of the first word line; wherein , when the first word line is disabled and the second word line is enabled, the second word line has a first enable potential, and when the first word line and the second word line are simultaneously When enabled, the second word line has a second enable potential different from the first enable potential.

The multi-port SRAM module and the control method of the multi-port SRAM module of the present invention can determine when the voltage of the multi-port SRAM needs to be adjusted, such as the voltage of the word line, the voltage of the bit line and/or the memory cell, by using a simple circuit voltage, etc., to increase the stability of the read and/or write operation of the multi-port SRAM module. And the multi-port SRAM module of the present invention also has asynchronous operation (that is, allows clock skew (clock skew) between different ports), does not need additional address positioning (address matching) circuit and/or arbitration (arbiter) circuit and Advantages such as small circuit area.

The features, implementation and effects of the present invention are described in detail as follows with reference to the accompanying drawings.

Description of drawings

Fig. 1 is the circuit diagram of existing dual-port SRAM module;

Fig. 2 is the circuit diagram of dual-port memory unit;

Fig. 3 is the partial circuit diagram of the multi-port SRAM module of an embodiment of the present invention;

FIG. 4 is a timing diagram of two word lines with dependencies;

5 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention;

FIG. 6 is a timing diagram of two word lines with dependencies;

7 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention;

8 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention;

9 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention; and

FIG. 10 is a flowchart of an embodiment of the control method of the multi-port SRAM module of the present invention.

Among them, reference signs:

110 dual port memory cells

120, 130, 210, 220 inverters

230, 240, 810, 820 switching elements

610 detection circuit

710 voltage adjustment circuit

720 multi-port memory unit

612, 614, 712, 714 NMOS

620 control line

630, 640 write control circuit

650, 660 reset circuit

655, 665, 832, 834, 836, 838 transistors

830 logic circuits

831 NAND gate

Steps from S910 to S930

detailed description

The technical terms in the following explanations refer to the customary terms in this technical field. If some terms are explained or defined in this manual, the explanations or definitions of this part of the terms shall prevail. The disclosed content of the present invention includes the multi-port SRAM module and the control method of the multi-port SRAM module, so as to improve the stability of read and/or write operations. Since some components included in the multi-port SRAM module of the present invention may be known components individually, on the premise of not affecting the full disclosure and practicability of the device invention, the details of the known components will be described below Abridged.

FIG. 3 is a partial circuit diagram of a multi-port SRAM module according to an embodiment of the present invention. The present invention is applicable to SRAMs with more than 2 ports (inclusive), that is, any column of a multi-port SRAM includes more than 2 word lines, and the word lines WLA and WLB shown in the figure are any 2 of them, respectively composed of Inverters 210 and 220 are driven. The word line WLB is coupled to a reference potential at its output end at the inverter 220 through the switching element 230, and the reference potential is higher or lower than when the word line WLB is enabled (for example, a high logic level is set as Enable) potential, in one embodiment, the reference potential may be the ground potential. The switch element 230 is turned on or off according to the level of the word line WLA, so the level of the word line WLB will be affected by the level of the word line WLA, that is to say, the word line WLA is actually connected to the word line WLA. The level of the word line WLB has a dependency (in this embodiment, it is a one-way dependency, that is, the level of the word line WLB is affected by the level of the word line WLA, but the level of the word line WLA is not affected by the level of the word line WLA. The influence of the level of the word line WLB). As shown in the figure, when the switching element 230 is implemented as a P-type metal oxide semiconductor field effect transistor (referred to as PMOS), the gate of the PMOS is coupled to the input terminal of the inverter 210, so when the word line WLA is enabled (the input end of the inverter 210 is at a low logic level), the switch element 230 is turned on, and the potential on the word line WLB changes. When the word line WLA is disabled and the word line WLB is enabled, the word line WLB has a first enable potential, and when the word line WLA and the word line WLB are simultaneously enabled, the word line WLB has a voltage different from A second enabling potential of the first enabling potential, that is, the first enabling potential can be greater than or smaller than the second enabling potential. Taking the second enabling potential lower than the first enabling potential as an example, as shown in FIG. 4 , the word line WLB in the interval T1 to T2 has a decrease of ΔV. The resulting word line under-drive (WLUD) on the word line WLB helps to reduce the read disturbance to avoid data error or loss. In one embodiment, for the memory cells connected to the word lines WLA and WLB, the control port corresponding to the word line WLA (that is, the control port coupled to the output terminal of the inverter 210) can be dedicated to write operations, and The control port corresponding to the word line WLB (ie, the control port coupled to the output terminal of the inverter 220 ) can be dedicated to the read operation, ie to reduce the read disturb.

The switch element 230 mentioned above can also be implemented by using an N-type metal oxide semiconductor field effect transistor (NMOS for short). At this time, the gate of the NMOS is coupled to the output terminal of the inverter 210 . The switch element 230 can also be more than one NMOS and/or PMOS and combinations thereof, and such changes are well known to those skilled in the art, so examples will not be illustrated one by one.

FIG. 5 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention. In this embodiment, in addition to the word line WLB coupled to the reference level through the switch element 230, the word line WLA is also coupled to the reference level through the switch element 240, and the switch element 240 is turned on/off. The non-conduction state is controlled by the logic level of the word line WLB. Therefore, the levels of the word line WLA and the word line WLB are dependent, that is, the levels of the two word lines will affect each other. Assuming that the reference potential coupled to the switching elements 230 and 240 is lower than the potential when the word line WLB is enabled, as shown in FIG. is forced to drop by ΔV1; similarly, the potential on the word line WLB is forced to drop by ΔV2 because the switching element 230 is turned on. The voltage drop amplitudes ΔV1 and ΔV2 are related to the sizes of the switching element 240 and the switching element 230 respectively. Likewise, the switch element 240 is not limited to be implemented by PMOS, and can be NMOS and/or PMOS and combinations thereof. It can be seen that, when the word line WLA and the word line WLB are simultaneously enabled, both can obtain the effect of word line drive suppression; compared with the previous embodiment, this embodiment can further suppress read disturb.

FIG. 7 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention. In this embodiment, the word line WLA and the word line WLB are coupled to the detection circuit 610 at the same time, and the detection circuit 610 generates the control signal CS according to the potentials of the word line WLA and the word line WLB. In this embodiment, when the word line WLA and the word line WLB are simultaneously enabled, the detection circuit 610 outputs the control signal CS with a low logic level. The control signal CS is coupled to the writing control circuits 630 and 640 through the control line 620 . The write control circuit 630 is used to drive the bit line pair BLA, and the write control circuit 640 is used to drive the bit line pair BLB. The reset circuits 650 and 660 are coupled to the control line 620 and respectively reset the potential on the control line 620 according to the signal LCA and the signal LCB. Signal LCA and signal LCB are related to the operating frequency of the SRAM module, so that at least one of the reset circuits 650 and 660 will be between the same set of word lines (ie, the word line coupled to the detection circuit 610, in this example The potential of the intermediate reset control line 620 is enabled twice consecutively for the word lines WLA and WLB). In this embodiment, the reset circuits 650 and 660 set the potential of the control line 620 to a high logic level during reset. The reset circuit 650 (660) can be implemented simply by coupling the transistor 655 (665) to a voltage source. When the control signal CS indicates that the word lines WLA and WLB are enabled at the same time, the write control circuits 630 and 640 can selectively lower the level of the bit lines controlled by them to cause a negative bit line (negative bit line, referred to as NBL) to increase the stability of write operations. The detection circuit 610 can simply be realized by a combination of transistors (for example, two NMOSs 612 and 614 connected in series), the purpose is that when the word lines WLA and WLB are simultaneously enabled, the control signal CS will cause level conversion.

FIG. 8 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention. In this embodiment, the word line WLA and the word line WLB are coupled to the voltage adjustment circuit 710 at the same time, and the voltage adjustment circuit 710 determines whether to connect the multi-port memory unit 720 according to whether the word line WLA and the word line WLB are enabled or not. One of the nodes is coupled to the negative voltage level -V. In one embodiment, the node can be the coupling point of the latch of the multi-port memory unit 720 and the low voltage level; more specifically, if the latch is composed of 2 PMOSs and 2 NMOSs, then This node is the source of the NMOS and is normally coupled to ground during operation. The voltage adjustment circuit 710 of this embodiment is composed of two NMOSs 712 and 714 connected in series. When the word line WLA and the word line WLB are enabled at the same time, the voltage of the node of the multi-port memory unit 720 is forcibly pulled down to Negative voltage level -V. The advantage of this design is that when the low voltage of the latch of the multi-port memory unit 720 is pulled lower (lower than normal operation), the read disturbance encountered by the multi-port memory unit 720 becomes lower, so The RSNM of the multi-port memory unit 720 can be increased. In other embodiments, the voltage adjustment circuit 710 may not be directly connected to the word lines WLA and WLB, but indirectly determines whether to change the voltage of the multi-port memory unit 720 according to the detection result of the detection circuit 610 (such as the CS signal). potential; in this case, the voltage adjustment circuit 710 may only include a transistor, the gate of which is coupled to the detection circuit 610, and it is determined whether to couple the multi-port memory unit 720 to a lower potential according to the detection result.

FIG. 9 is a partial circuit diagram of a multi-port SRAM module according to another embodiment of the present invention. The word line WLA and the word line WLB are coupled to each other through the switching element 810 and the switching element 820 , and both the switching elements 810 and 820 are coupled to the logic circuit 830 . When the word line WLA (word line WLB) is enabled, the switch element 820 (switch element 810) is turned on, and at this time the logic circuit 830 determines whether to implement word line drive inhibit. In this embodiment, the word line corresponding to the read operation will be given word line drive inhibition, and when two word lines are corresponding to the write operation at the same time, both will be given word line drive inhibition, which The corresponding relationship is shown in the table below:

WENA/WENB 0/0 0/1 1/0 1/1 WLA WLUD WLUD -- WLUD WLB WLUD -- WLUD WLUD

When the read/write control signals WENA and WENB are logic values 1/0, they correspond to write/read operations respectively, and WLUD represents word line driver inhibition. It can be seen that the design principle of the logic circuit 830 is that when the word line WLA and the word line WLB correspond to the read operation at the same time, both of them will be suppressed by the word line drive. When one corresponds to the read operation, the other When corresponding to the write operation, only the word line corresponding to the read operation will be inhibited by the word line drive, and when both are corresponding to the write operation at the same time, both will be inhibited by the word line drive; different Various changes can be derived from the disclosure of the implementation and the control of the word line drive suppression, and are not listed here to avoid redundant text. The logic circuit 830 includes a NAND gate (NANDGate) 831, four transistors 832, 834, 836, and 838. The operation principle and connection method thereof are understood and changed by those skilled in the art, and thus will not be described in detail.

Please refer to FIG. 10 , which is a flowchart of an embodiment of the control method of the multi-port SRAM module of the present invention, including the following steps:

Step S910: Change the potential of another word line according to the potential of one of the word lines of the same group. Taking dual-port as an example, as shown in FIG. 1 , in a dual-port SRAM module, the dual-port memory cells 110 in the same column are controlled by a group of word lines (including two word lines). In this step, when one of them is enabled, the potential of the other is changed; more specifically, when the word line WLA is disabled and the word line WLB is enabled, the word line WLB has a first consistent When the word line WLA and the word line WLB are simultaneously enabled, the word line WLB has a second enable potential different from the first enable potential. For example, lowering the enable potential of the word line WLB when the word line WLA is enabled can achieve the effect of word line drive suppression and reduce the read disturbance to the dual-port memory unit 110 . In addition, this step may further include the following details: determining whether to change the potential of the word line according to the read/write control signal. In one embodiment, the potential of the word line can be changed according to the above design principle of the logic circuit 830;

Step S920: Detect potential changes of a group of word lines, and generate a detection result. When at least two word lines in a group of word lines are simultaneously enabled, the detection result reflects the state; and

Step S930: Adjust the potential of the bit line or the memory cell according to the detection result. When at least 2 word lines of the same row of memory cells are enabled at the same time, the reliability of the write operation can be improved by reducing the voltage of the bit line (that is, implementing a negative bit line), or by reducing the memory The low potential of the unit makes it difficult for the data stored in the memory unit to be reversed, so as to improve the reliability of the read operation.

The above-mentioned embodiments can be implemented in combination, for example, Figure 5 can be combined with Figure 7 and/or Figure 8, Figure 9 can be combined with Figure 7 and/or Figure 8, or Figure 3 can be combined with Figure 7 and/or Figure 8, etc. etc. This is a combination change that can be easily deduced by those skilled in the art, so it will not be described in detail. In the process of FIG. 10 , step S910 can be implemented independently of step S920 and step S930 .

Although only any two word lines in the multi-port SRAM module are shown in the above-mentioned embodiments, the present invention can be extended to more than three word lines, for example, the word line WLB in FIG. 3 or FIG. A switching element that is in conduction/non-conduction state according to the potential of the word line WLC is coupled to the reference potential, or the detection circuit in FIG. 7 or FIG. On/off switching element. Because those skilled in the art can understand the implementation details and changes of the method invention in FIG. 10 through the disclosure of the device invention in FIGS. Under the premise of requirements and practicability, repeated descriptions are omitted here. Please note that in the aforementioned drawings, the shapes, sizes, proportions, and sequence of steps of components are only illustrative, for those skilled in the art to understand the present invention, and are not intended to limit the present invention.

Although the embodiments of the present invention are as described above, these embodiments are not used to limit the present invention, and those skilled in the art can make changes to the technical characteristics of the present invention according to the explicit or implicit content of the present invention, where Various changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention must be defined by the claims of this specification.

Claims (19)

1. a multi-port SRAM module, it is characterised in that comprise:

One memory cell array, comprises multiple row memory cell, and each memory cell comprises at least one first control port And one second control port；

One first word-line, couples multiple memory cells of a target column, is used for controlling whether this first control port is opened；

One second word-line, couples multiple memory cells of this target column, is used for controlling whether this second control port is opened； And

One switch element, couples this first word-line and this second word-line, decides whether according to the current potential of this first word-line This second word-line is coupled to a reference potential；

Wherein, when this first word-line not enable and this second word-line enable, this second word-line has one first enable Current potential, when the enable simultaneously of this first word-line and this second word-line, this second word-line has and is different from this first enable One second enable current potential of current potential.

2. multi-port SRAM module as claimed in claim 1, it is characterised in that also comprise:

One first phase inverter, is used for driving this first word-line, and its outfan couples this first control port；And

One second phase inverter, is used for driving this second word-line, and its outfan couples this second control port；

Wherein this switch element is a p-type metal-oxide half field effect transistor, and its source electrode couples the outfan of this second phase inverter and is somebody's turn to do The one of which of reference potential, drain electrode couples another one, and grid couples the input of this first phase inverter.

3. multi-port SRAM module as claimed in claim 1, it is characterised in that also comprise:

One first phase inverter, is used for driving this first word-line, and its outfan couples this first control port；And

One second phase inverter, is used for driving this second word-line, and its outfan couples this second control port；

Wherein this switch element is a N-type metal-oxide half field effect transistor, and its source electrode couples the outfan of this second phase inverter and is somebody's turn to do The one of which of reference potential, drain electrode couples another one, and grid couples the outfan of this first phase inverter.

4. multi-port SRAM module as claimed in claim 1, it is characterised in that also comprise:

One another switch element, couples this first word-line and this second word-line, determines according to the current potential of this second word-line Whether this first word-line is coupled to this reference potential.

5. multi-port SRAM module as claimed in claim 4, it is characterised in that also comprise:

One logic circuit, is coupled to this switch element, this another switch element and this reference potential, is used for according to should first Control one first read-write control signal of port and to should the second one second read-write control signal controlling port decide whether It is coupled to this reference potential by least within the one of this first word-line and this second word-line.

6. multi-port SRAM module as claimed in claim 1, it is characterised in that also comprise:

One testing circuit, couples this first word-line and this second word-line, is used for detecting this first word-line and this second word The current potential of unit's line, to produce a testing result；

Wherein, this testing result system changes the voltage of those memory cells of this target column according to this, or changes according to this and be somebody's turn to do The voltage of the bit line that the first control port or this second control port are connected.

7. multi-port SRAM module as claimed in claim 1, it is characterised in that this second enable current potential is less than this first enable Current potential.

8. multi-port SRAM module as claimed in claim 1, it is characterised in that this second enable current potential is more than this first enable Current potential.

9. a multi-port SRAM module, it is characterised in that comprise:

One memory cell array, comprises the memory cell of multiple row, and each memory cell comprises at least one first control end Mouth and one second controls port；

One first word-line, couples multiple memory cells of a target column, is used for controlling whether this first control port is opened；

One second word-line, couples multiple memory cells of this target column, is used for controlling whether this second control port is opened； And

One testing circuit, couples this first word-line and this second word-line, is used for detecting this first word-line and this second word The current potential of unit's line, to produce a testing result；

Wherein, this testing result system changes the voltage of those memory cells of this target column according to this, or changes according to this and be somebody's turn to do The voltage of the bit line that the first control port or this second control port are connected.

10. multi-port SRAM module as claimed in claim 9, it is characterised in that also comprise:

One write control circuit, couples this testing circuit, utilizes this bit line to perform write behaviour with the memory cell to part Make, and change the current potential of this bit line according to this testing result.

11. multi-port SRAM modules as claimed in claim 9, it is characterised in that also comprise:

One voltage-regulating circuit, couples this testing circuit, changes those memory cells of this target column according to this testing result Voltage.

12. multi-port SRAM modules as claimed in claim 9, it is characterised in that also comprise:

One voltage-regulating circuit, couples this first word-line and this second word-line, this first word-line of direct basis and this The current potential of two word-line, changes the voltage of those memory cells of this target column.

13. multi-port SRAM modules as claimed in claim 9, it is characterised in that this testing circuit comprises:

One the first transistor, has one first control end, one first end points and one second end points, and this first control end is coupled to this First word-line, this first end points is coupled to a reference potential；And

One transistor seconds, has one second control end, one the 3rd end points and one the 4th end points, and this second control end is coupled to this Second word-line, the 3rd end points is coupled to this second end points, and the 4th end points exports this testing result.

14. multi-port SRAM modules as claimed in claim 9, it is characterised in that also comprise:

One control line, couples this testing circuit, to transmit this testing result；And

One reset circuit, couples this control line, is used for enable in this first word-line and this second word-line are double while Period reset the current potential of this control line.

The control method of 15. 1 kinds of multi-port SRAM modules, this multi-port SRAM module comprises one first word-line and one second Word-line, this first word-line and this second word-line are respectively intended to control one first control of the multiple memory cells with string Port processed and one second controls whether port is opened, and this control method comprises:

The current potential of this second word-line is changed according to the current potential of this first word-line；

Wherein, when this first word-line not enable and this second word-line enable, this second word-line has one first enable Current potential, when the enable simultaneously of this first word-line and this second word-line, this second word-line has and is different from this first enable One second enable current potential of current potential.

16. control methods as claimed in claim 15, it is characterised in that also comprise:

According to should first control port one first read-write control signal and to should second control port one second reading Write control signal decides whether to change at least one of current potential of this first word-line and this second word-line.

17. control methods as claimed in claim 15, it is characterised in that each memory cell couples a bit line, this control Method processed also comprises:

Detect the change in voltage of this first word-line and this second word-line to produce a testing result；And

The current potential of this bit line or those memory cells is adjusted according to this testing result.

18. control methods as claimed in claim 15, it is characterised in that this second enable current potential is less than this first enable electricity Position.

19. control methods as claimed in claim 15, it is characterised in that this second enable current potential is more than this first enable electricity Position.