CN106249795A - A kind of LDO circuit of output of floating - Google Patents

Abstract

The embodiment of the present invention discloses a floating output LDO circuit, including: an operational amplifier circuit 10 and an output circuit 20 . The operational amplifier circuit 10 includes two inverting inputs and one non-inverting input. The output circuit 20 is connected to the operational amplifier circuit 10 for providing a feedback loop from input to output for the operational amplifier circuit 10 . In the example of the present invention, the two inverting input terminals of the operational amplifier circuit 10 are not input at the same time, and an appropriate input terminal is selected according to needs, and then a floating output voltage is generated through the output circuit 20 . The floating output LDO circuit can make the chip work more energy-saving, efficient and quick start, and has better practical application value than the traditional LDO circuit.

Description

A Floating Output LDO Circuit

technical field

The invention relates to the technical field of integrated circuit switching power supplies, in particular to a floating output LDO circuit.

Background technique

Today, mobile electronic devices have been widely used in the fields of life and industry, and power integrated circuits, as a prerequisite for the development of electronic device technology, have become a hot spot in the research of integrated circuits.

From the perspective of portability, mobile devices require a relatively small volume and mass of power supplies. However, mobile devices need good battery life, which requires a large power supply that can supply power to the device for a long time. These two points require the power supply to have the characteristics of small size and high energy at the same time, that is, the power supply must have high conversion efficiency. The linear low dropout regulator (Low Dropout Regulator, LDO) is a new generation of integrated circuit regulator with low power consumption, low noise and high power supply rejection ratio. It realizes the step-down function and obtains the output voltage VDD to supply power to other modules of the chip.

The general linear low-dropout voltage regulator circuit generates a stable voltage from the input to supply power to other modules of the system to meet user requirements. The power chip will encounter many situations during its operation, such as undervoltage, overvoltage, overtemperature and other harsh conditions. In this case, if the chip continues to work, the internal structure of the chip will be damaged and the working efficiency of the chip will be reduced. The traditional LDO circuit will stop working, and wait until the bad situation is lifted and then power on again. However, with the development of integrated circuits and different applications, the floating output LDO circuit can reduce power consumption and improve efficiency. Aiming at making the chip work more efficiently and saving energy in different modes, there is a need for an LDO circuit with a floating output.

Contents of the invention

The purpose of the present invention is to provide a floating output LDO circuit, which makes the chip work more efficient, saves energy, and saves power consumption while realizing fast startup.

The technical solutions disclosed in the present invention include:

An LDO circuit with a floating output is provided, which is characterized in that it includes: an operational amplifier circuit, the operational amplifier circuit includes a positive input terminal inp, an inverting input terminal inn1, an inverting input terminal inn2, and an output terminal op_out, and the operational amplifier The two inverting input terminals inn1 and inn2 of the circuit select an input as required, and the operational amplifier circuit makes the voltage of the positive input terminal inp equal to the voltage of one terminal inn1 and inn2 of the inverting input terminal; the output circuit , the input terminal of the output circuit is connected to the output terminal op_out of the operational amplifier circuit, and the output voltage VDD is obtained through resistor division. The output terminal VDD of the output circuit is connected with the positive input terminal inp of the operational amplifier circuit through a resistor R1, which is used to provide a feedback loop from input to output for the operational amplifier circuit, and realize the output and operation of the output circuit The input of the amplifier circuit forms a linear following relationship.

In an example of the present invention, the output circuit includes a first field effect transistor PM1, a second field effect transistor PM2, a first resistor R1, a second resistor R2, a third resistor R3, and a first load capacitor C1, wherein: The source of the first field effect transistor PM1 is connected to the power supply Vin, the grid and drain of the first field effect transistor PM1 are connected together to form a diode connection mode, and are connected to one end of the third resistor R3; The other end of the resistor R3 is connected to the output terminal op_out of the operational amplifier circuit and the gate of the second field effect transistor PM2 of the output circuit; the source end of the second field effect transistor PM2 is connected to the power supply Vin, the The gate terminal of the second field effect transistor PM2 is connected to the output terminal op_out of the operational amplifier circuit, and the drain terminal of the second field effect transistor PM2 is connected to the common terminal of the first resistor R1 and the first load capacitor C1 to become output terminal VDD; the first resistor R1 and the second resistor R2 are connected in series, and the common connection terminal of the first resistor R1 and the second resistor R2 is connected to the positive input terminal inp of the operational amplifier circuit; the second The other end of the resistor R2 is grounded; the other end of the first load capacitor C1 is grounded.

In an example of the present invention, the operational amplifier circuit includes a third field effect transistor PM3, a fourth field effect transistor PM4, a fifth field effect transistor PM5, a sixth field effect transistor PM6, a seventh field effect transistor NM1, an eighth field effect transistor field effect transistor NM2, the ninth field effect transistor NM3, and the tenth field effect transistor NM4, wherein: the gate of the third field effect transistor PM3 and the gate of the fourth field effect transistor PM4 are connected together, and the third field effect transistor PM4 The source of the field effect transistor PM3 is connected to the power supply Vin, the drain of the third field effect transistor PM3 is connected to the source of the fifth field effect transistor PM5, and connected to the output terminal op_out of the operational amplifier circuit; The source of the fourth field effect transistor PM4 is connected to the high potential terminal Vin, and the gate and drain of the fourth field effect transistor PM4 are connected together to the source of the sixth field effect transistor PM6; The gate of the fifth field effect transistor PM5 and the gate of the sixth field effect transistor PM6 are connected together, externally connected to a bias potential pbias, and the drain of the fifth field effect transistor PM5 is connected to the seventh field The drain of the effect transistor NM1 and the drain of the eighth field effect transistor NM2; the drain of the sixth field effect transistor PM6 is connected to the drain of the ninth field effect transistor NM3; the seventh field effect transistor NM1 The gate of the gate is connected to the inverting input terminal inn1 of the operational amplifier circuit, the source of the seventh field effect transistor NM1, the source of the eighth field effect transistor NM2, and the source of the ninth field effect transistor NM3 are connected to together, connected to the drain of the tenth field effect transistor NM4; the gate of the eighth field effect transistor NM2 connected to the inverting input terminal inn2 of the operational amplifier circuit; the gate of the ninth field effect transistor NM3 The gate is connected to the positive input terminal inp of the operational amplifier circuit; the gate of the tenth field effect transistor NM4 is externally connected to a bias potential nbias, and the source of the tenth field effect transistor NM4 is grounded.

In the example of the present invention, the two inverting input ends of the operational amplifier circuit are not input at the same time, and an appropriate input is selected according to the output requirement, and then a floating output voltage is generated through the output circuit. The operational amplifier circuit makes the voltage of the positive input terminal inp equal to the voltage of one terminal inn1 and inn2 of the negative input terminal through a feedback loop. The output voltage VDD is generated through resistor division, and the output voltage VDD forms a linear follow-up relationship with the input of the operational amplifier circuit. The floating output LDO circuit can make the chip work more energy-saving, efficient and quick start, and has better practical application value than the traditional LDO circuit.

Description of drawings

FIG. 1 is a schematic structural diagram of a floating output LDO circuit according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of an operational amplifier circuit according to an embodiment of the present invention.

detailed description

The specific structure of the floating output LDO circuit of the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a floating output LDO circuit according to an embodiment of the present invention.

As shown in FIG. 1 , in some embodiments of the present invention, a floating output LDO circuit includes an operational amplifier circuit 10 and an output circuit 20 .

The operational amplifier circuit 10 includes a positive input terminal inp, an inverting input terminal inn1, an inverting input terminal inn2 and an output terminal op_out, and the two inverting input terminals inn1 and inn2 of the operational amplifier circuit select an input as required, and the operation The amplifier circuit 10 makes the voltage of the positive input terminal inp and the voltages of one terminal inn1 and inn2 of the inverting input terminal equal (for example, approximately equal, in this paper, when talking about equal voltages, it is not strictly limited that the voltages must be completely equal , but the difference between the two voltages is still included in the "equal" range herein when within a certain error range); the output circuit 20, the input terminal of the output circuit 20 is connected to the operational amplifier circuit 10 The output terminal op_out obtains the output voltage VDD through resistor division. Wherein the output terminal VDD of the output circuit 20 is connected together with the forward input terminal inp of the operational amplifier circuit 10 through a resistor R1, so as to provide a feedback loop from input to output for the operational amplifier circuit 10, and realize the output circuit 20 The output of and the input of the operational amplifier circuit 10 form a linear following relationship.

As shown in FIG. 1, in some embodiments of the present invention, the output circuit 20 includes a first field effect transistor PM1, a second field effect transistor PM2, a first resistor R1, a second resistor R2, a third resistor R3, a first load Capacitor C1, wherein: the source of the first field effect transistor PM1 is connected to the power supply Vin, the gate and drain of the first field effect transistor PM1 are connected together to form a diode connection, and connected to the third resistor R3 One end; the other end of the third resistor R3 is connected to the output terminal op_out of the operational amplifier circuit 10 and the gate of the second field effect transistor PM2 of the output circuit 20; the source of the second field effect transistor PM2 terminal is connected to the power supply Vin, the gate terminal of the second field effect transistor PM2 is connected to the output terminal op_out of the operational amplifier circuit 10, and the drain terminal of the second field effect transistor PM2 is connected to the first resistor R1 and The common terminal of the first load capacitor C1 becomes the output terminal VDD; the first resistor R1 and the second resistor R2 are connected in series, and the common connection terminal of the first resistor R1 and the second resistor R2 is connected to the operational amplifier circuit 10 The positive input terminal inp; the other end of the second resistor R2 is grounded; the other end of the first load capacitor C1 is grounded.

In these embodiments, the resistance ratio of R1 and R2 can be adjusted arbitrarily to obtain the required VDD. The drain terminal of the second field effect transistor PM2 will flow a large current, so the width-to-length ratio of the second field effect transistor PM2 must be large. The voltage difference (Vin-op_out) across the first field effect transistor PM1 and the third resistor R3 is the source-gate difference Vgs1 of the second field effect transistor PM2, and the width-to-length ratio of the first field effect transistor PM1 and the second field effect transistor PM1 are set. The resistance value of the three resistors R3 can make the second field effect transistor PM2 work in the saturation region.

As shown in Figure 2, in some examples of the present invention, the operational amplifier circuit 10 includes a third field effect transistor PM3, a fourth field effect transistor PM4, a fifth field effect transistor PM5, a sixth field effect transistor PM6, a seventh field effect transistor tube NM1, the eighth field effect transistor NM2, the ninth field effect transistor NM3, and the tenth field effect transistor NM4, wherein: the gate of the third field effect transistor PM3 and the gate of the fourth field effect transistor PM4 are connected together , the source of the third field effect transistor PM3 is connected to the power supply Vin, the drain of the third field effect transistor PM3 is connected to the source of the fifth field effect transistor PM5, and connected to the operational amplifier circuit 10 output terminal op_out; the source of the fourth field effect transistor PM4 is connected to the power supply Vin, and the grid and drain of the fourth field effect transistor PM4 are connected together to the sixth field effect transistor PM6 source; the gate of the fifth field effect transistor PM5 is connected to the gate of the sixth field effect transistor PM6, and is externally connected to a bias potential pbias, and the drain of the fifth field effect transistor PM5 is connected to the The drain of the seventh field effect transistor NM1 and the drain of the eighth field effect transistor NM2; the drain of the sixth field effect transistor PM6 is connected to the drain of the ninth field effect transistor NM3; The gate of the field effect transistor NM1 is connected to the inverting input terminal inn1 of the operational amplifier circuit 10, the source of the seventh field effect transistor NM1 and the source of the eighth field effect transistor NM2, the ninth field effect transistor NM3 The sources of the eighth field effect transistor NM2 are connected to the drain of the tenth field effect transistor NM4; the gate of the eighth field effect transistor NM2 is connected to the inverting input terminal inn2 of the operational amplifier circuit 10; The gate of the nine field effect transistor NM3 is connected to the positive input terminal inp of the operational amplifier circuit 10; the gate of the tenth field effect transistor NM4 is externally connected to a bias potential nbias, and the tenth field effect transistor NM4 The source is grounded.

In the example of the present invention, the two bias potentials in the operational amplifier circuit 10 are generated by a common bias circuit and will not be described in detail. The seventh field effect transistor NM1 and the eighth field effect transistor NM2 will not work at the same time, which is determined according to the gate input. Because the output circuit 20 provides a feedback loop, the operational amplifier circuit 10 satisfies the virtual short condition, that is, the operational amplifier circuit 10 works in a negative feedback loop and the open-loop gain is large, thereby realizing the positive-phase input terminal and the positive-phase input terminal of the operational amplifier circuit 10. The voltages at the inverting inputs are equalized, which also keeps the system in a steady state.

In the example of the present invention, the two inverting input terminals of the operational amplifier circuit 10 are not input at the same time, and an appropriate input terminal is selected according to needs, and then a floating output voltage is generated through the output circuit 20 . The floating output LDO circuit can make the chip work more energy-saving, efficient and quick start, and has better practical application value than the traditional LDO circuit.

The working principle of the circuit of the embodiment of the present invention will be briefly described below.

For example, in the embodiment shown in FIG. 1, when the chip starts to be powered on, a lower inn1 input is generated, and the voltages of the non-inverting input terminal and the inverting input terminal of the operational amplifier circuit 10 are equal and the resistor voltage division relationship generates A regulated output VDD1, namely:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, at this time, the voltage of the non-inverting input terminal inp of the operational amplifier circuit 10 is equal to the voltage of the inverting input terminal inn1.

When VDD1 is stable, it can drive some other modules of the system to work, such as the bandgap reference module. At this time, a higher inn2 input will be generated, and a new regulated output VDD2 will be generated by the voltage equalization of the positive-phase input terminal and the reverse input terminal of the operational amplifier circuit 10 and the resistor voltage divider relationship, namely:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, at this time, the voltage of the non-inverting input terminal inp of the operational amplifier circuit 10 is equal to the voltage of the inverting input terminal inn2.

When the chip is working normally, the LDO circuit outputs VDD2 to supply power to the chip module; when some abnormal conditions suddenly occur on the chip, the LDO circuit switches to output VDD1 to maintain the work of some modules of the chip, but not completely shut down the entire chip; wait until it is abnormal After the situation is lifted, the chip can start quickly under the action of VDD1, and the LDO circuit switches to output VDD2. In this way, the floating output LDO circuit can make the chip work more efficiently and save energy, which will not affect the normal operation of the chip, but also allow the chip to start quickly after abnormal conditions are excluded.

It can be seen that the embodiment of the present invention has carried out a very good optimization on the working mode of the chip, which not only ensures the normal stable voltage output, but also realizes the function of quick start, so it has great practical application value.

The present invention has been described above through specific examples, but the present invention is not limited to these specific examples. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present invention. As long as these changes do not deviate from the spirit of the present invention, they should all be within the protection scope of the present invention. In addition, "one embodiment" described in many places above represents different embodiments, and of course all or part of them may be combined in one embodiment.

Claims (3)

1. A kind of LDO circuit of floating output, is characterized in that, comprises: Operational amplifier circuit (10): The operational amplifier circuit (10) includes a positive input terminal inp, an inverting input terminal inn1, an inverting input terminal inn2, and an output terminal op_out. The two inverting input terminals inn1 and inn2 of the operational amplifier circuit are based on One input needs to be selected, and the operational amplifier circuit (10) makes the voltage of the positive input terminal inp equal to the voltage of one terminal inn1 and inn2 of the negative input terminal; Output circuit (20): the input terminal of the output circuit (20) is connected to the output terminal op_out of the operational amplifier circuit (10), and the output voltage VDD is obtained through resistor division; Wherein the output terminal VDD of the output circuit (20) is connected together with the positive input terminal inp of the operational amplifier circuit (10) through a resistor R1 to provide a feedback loop from input to output for the operational amplifier circuit (10) . 2. A floating output LDO circuit according to claim 1, characterized in that the output circuit (20) comprises a first field effect transistor PM1, a second field effect transistor PM2, a first resistor R1, a second Resistor R2, third resistor R3, first load capacitor C1, wherein: The source of the first field effect transistor PM1 is connected to the power supply Vin, the gate and drain of the first field effect transistor PM1 are connected together to form a diode connection, and connected to one end of the third resistor R3; The other end of the third resistor R3 is connected to the output terminal op_out of the operational amplifier circuit (10) and the gate of the second field effect transistor PM2 of the output circuit (20); The source terminal of the second field effect transistor PM2 is connected to the power supply Vin, the gate terminal of the second field effect transistor PM2 is connected to the output terminal op_out of the operational amplifier circuit (10), and the second field effect transistor PM2 The drain terminal connected to the common terminal of the first resistor R1 and the first load capacitor C1 becomes the output terminal VDD; The first resistor R1 and the second resistor R2 are connected in series, and the common connection terminal of the first resistor R1 and the second resistor R2 is connected to the positive input terminal inp of the operational amplifier circuit (10); The other end of the second resistor R2 is grounded; The other end of the first load capacitor C1 is grounded. 3. A floating output LDO circuit as claimed in any one of claims 1 or 2, characterized in that the operational amplifier circuit (10) includes a third field effect transistor PM3, a fourth field effect transistor PM4, a fifth field effect transistor Field effect transistor PM5, sixth field effect transistor PM6, seventh field effect transistor NM1, eighth field effect transistor NM2, ninth field effect transistor NM3, tenth field effect transistor NM4, wherein: The gate of the third field effect transistor PM3 and the gate of the fourth field effect transistor PM4 are connected together, the source of the third field effect transistor PM3 is connected to the power supply Vin, and the gate of the third field effect transistor PM3 The drain is connected to the source of the fifth field effect transistor PM5, and connected to the output terminal op_out of the operational amplifier circuit (10); The source of the fourth field effect transistor PM4 is connected to the power supply Vin, and the gate and drain of the fourth field effect transistor PM4 are connected together to the source of the sixth field effect transistor PM6; The gate of the fifth field effect transistor PM5 and the gate of the sixth field effect transistor PM6 are connected together, externally connected to a bias potential pbias, and the drain of the fifth field effect transistor PM5 is connected to the seventh The drain of the field effect transistor NM1 and the drain of the eighth field effect transistor NM2; The drain of the sixth field effect transistor PM6 is connected to the drain of the ninth field effect transistor NM3; The gate of the seventh field effect transistor NM1 is connected to the inverting input terminal inn1 of the operational amplifier circuit (10), the source of the seventh field effect transistor NM1 and the source of the eighth field effect transistor NM2, The sources of the ninth field effect transistor NM3 are connected together and connected to the drain of the tenth field effect transistor NM4; The gate of the eighth field effect transistor NM2 is connected to the inverting input terminal inn2 of the operational amplifier circuit (10); The gate of the ninth field effect transistor NM3 is connected to the positive input terminal inp of the operational amplifier circuit (10); The gate of the tenth field effect transistor NM4 is externally connected to a bias potential nbias, and the source of the tenth field effect transistor NM4 is grounded.