CN106226963A - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- CN106226963A CN106226963A CN201610601460.9A CN201610601460A CN106226963A CN 106226963 A CN106226963 A CN 106226963A CN 201610601460 A CN201610601460 A CN 201610601460A CN 106226963 A CN106226963 A CN 106226963A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
nullThe invention discloses a kind of array base palte、Display floater and display device，Periphery cabling in the non-display area of array base palte include in sector arrangement at least two group the first cablings and with each first cabling one_to_one corresponding and the second cabling of the fold-line-shaped of electric connection，Compared with the structure arranged in sector overall with the periphery cabling in the non-display area of existing array base palte，The negligible amounts of each the first cabling comprised in one group of first cabling of arrangement in sector，Often organize the first cabling being positioned at zone line in the first cabling less with the resistance difference of the first cabling being positioned at two side areas，It is easy to the length by increasing the first cabling in zone line or increases the live width of the first cabling in two side areas to realize often organizing the resistance of each first cabling in the first cabling equal，And，The length of each second cabling is equal and live width is equal，The resistance of the most each second cabling is equal，Therefore，The resistance difference of periphery cabling can be compensated well for.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Among the existing display panels, an Organic Light Emitting display panel (OLED) has the advantages of simple preparation process, low cost, high Light Emitting efficiency, easy formation of a flexible structure, and the like; a Liquid Crystal Display (LCD) panel has the advantages of low power consumption, high Display quality, no electromagnetic radiation, and a wide application range.
Taking a liquid crystal display panel as an example, the liquid crystal display panel generally includes an array substrate, an opposite substrate and a liquid crystal layer located between the two substrates. The array substrate generally comprises a display area and a non-display area surrounding the display area; the display device generally includes pixels and signal lines, such as gate lines and data lines, disposed in the display region for transmitting signals, and the non-display region includes peripheral traces disposed therein for connecting the signal lines in the display region to the driving circuit, such as the gate lines connected to the gate driving circuit through the peripheral traces and the data lines connected to the source driving circuit through the peripheral traces.
In the non-display area of the array substrate, as shown in fig. 1, the peripheral traces 100 are arranged in a fan shape, the length of the peripheral trace 100 in the middle area a is less than the length of the peripheral trace 100 in the two side areas b, so that the resistance of the peripheral trace 100 in the middle area a is less than the resistance of the peripheral trace 100 in the two side areas b, which results in the delay time of the signal line electrically connected to the peripheral trace 100 in the middle area a receiving the signal being less than the delay time of the signal line electrically connected to the peripheral trace 100 in the two side areas b receiving the signal, which results in the charging time of the pixels in the display area corresponding to the middle area a being greater than the charging time of the pixels in the display area corresponding to the two side areas b, thereby resulting in the display brightness in the display area corresponding to the middle area a being greater than the display brightness in the display area corresponding to the two side areas b, various display defects are generated on the display panel.
The existing methods for compensating the difference of the peripheral wiring resistance have two types: one is to increase the resistance of the peripheral traces in the middle area by increasing the length of the peripheral traces in the middle area, and the other is to decrease the resistance of the peripheral traces in the two side areas by increasing the line width of the peripheral traces in the two side areas. However, as the resolution of the display panel is continuously improved, the number of pixels in the display panel is increased, and accordingly, the number of signal lines and peripheral traces is also increased, so that the resistance difference between the peripheral traces in the middle area and the peripheral traces in the two side areas is increased.
Disclosure of Invention
In view of this, embodiments of the present invention provide an array substrate, a display panel and a display device, so as to compensate for the resistance difference of the peripheral traces.
Therefore, an embodiment of the present invention provides an array substrate, including: a display area and a non-display area; the non-display area is internally provided with peripheral wires which electrically connect the signal wires in the display area to the driving chip;
the peripheral wires comprise at least two groups of first wires which are arranged in a fan shape and fold-line-shaped second wires which correspond to the first wires one by one and are electrically connected; wherein,
the resistances of the first wires are equal, and the first wires are electrically connected with the signal wires;
the second wires are equal in length and equal in line width and are electrically connected with the driving chip.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, the first traces are equal in length and equal in line width.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, each first trace includes a first sub-trace electrically connected to the corresponding second trace and a second sub-trace electrically connected to the signal line;
in each group of first wires, each first sub-wire is in a straight line shape, the extension lines of the first sub-wires are converged at least one point, the convergence point is located at one side of each first sub-wire close to the driving chip, and the length of each first sub-wire is gradually reduced and then gradually increased along the arrangement direction of the first wires;
in each group of first wires, the second sub-wires located in the middle area are curved, the second sub-wires located in the two side areas are straight, and the lengths of the second sub-wires are gradually increased and then gradually decreased along the arrangement direction of the first wires.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, in each group of the first traces, along the arrangement direction of the first traces, the line width of the first trace is gradually decreased and then gradually increased, and the length of the first trace is gradually decreased and then gradually increased.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, each first trace includes a first sub-trace electrically connected to the corresponding second trace and a second sub-trace electrically connected to the signal line;
in each group of first wires, each first sub-wire is in a straight line shape, the extension lines of the first sub-wires are converged at least one point, the convergence point is located at one side of each first sub-wire close to the driving chip, and the length of each first sub-wire is gradually reduced and then gradually increased along the arrangement direction of the first wires;
in each group of the first routing lines, each second sub-routing line is in a straight line shape, and the lengths of the second sub-routing lines are equal.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, the number of the first traces included in each group of the first traces is equal.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, the driving chip is a gate driving circuit;
the signal line is a gate line.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, the driving chip is a source driving circuit;
the signal line is a data line.
An embodiment of the present invention further provides a display panel, including: the array substrate provided by the embodiment of the invention.
An embodiment of the present invention further provides a display device, including: the display panel provided by the embodiment of the invention.
In the array substrate, the display panel and the display device provided in the embodiments of the present invention, the peripheral traces in the non-display area of the array substrate include at least two sets of first traces arranged in a fan shape and second traces in a zigzag shape that are in one-to-one correspondence with the first traces and are electrically connected to the first traces, compared with a structure in which the peripheral traces in the non-display area of the existing array substrate are arranged in a fan shape as a whole, the number of the first traces included in each set of first traces arranged in a fan shape is small, the length difference between the first traces in the middle area and the first traces in the two side areas in each set of first traces is small, the resistance difference between the first traces in the middle area and the first traces in the two side areas in each set of first traces is small, it is easy to achieve the equal resistance of the first traces in each set of first traces by increasing the length of the first traces in the middle area or increasing the line width of the first traces in the two side areas, moreover, the lengths of the second wires are equal, the line widths of the second wires are equal, namely, the resistances of the second wires are equal, so that the resistance difference of the peripheral wires can be well compensated, and poor display caused by the resistance difference of the peripheral wires is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a peripheral trace in a conventional array substrate;
fig. 2-4 are schematic structural diagrams of peripheral traces in an array substrate according to an embodiment of the invention.
Detailed Description
Embodiments of an array substrate, a display panel and a display device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
An array substrate provided in an embodiment of the present invention includes: a display area and a non-display area; as shown in fig. 2 and 3, the non-display region has a peripheral trace 2 for electrically connecting the signal line in the display region to the driving chip 1;
the peripheral traces 2 include at least two groups of first traces 21 (fig. 2 and 3 show two groups of first traces, respectively) arranged in a fan shape and a fold-line-shaped second trace 22 corresponding to and electrically connected to each first trace 21 one by one; wherein,
the first wires 21 have equal resistance and are electrically connected with the signal lines;
the second wires 22 have the same length and the same line width, and are electrically connected to the driving chip 1.
In the array substrate provided in the embodiment of the present invention, the peripheral traces in the non-display area of the array substrate include at least two sets of first traces arranged in a fan shape and second traces electrically connected to the first traces in a one-to-one correspondence, and compared with the structure in which the peripheral traces in the non-display area of the existing array substrate are arranged in a fan shape as a whole, the number of the first traces included in each set of first traces arranged in a fan shape is smaller, the length difference between the first trace in the middle area and the first traces in the two side areas in each set of first traces is smaller, the resistance difference between the first trace in the middle area and the first traces in the two side areas in each set of first traces is smaller, and the resistance of each first trace in each set of first traces is easily equal by increasing the length of the first trace in the middle area or increasing the line width of the first traces in the two side areas, moreover, the lengths of the second wires are equal, the line widths of the second wires are equal, namely, the resistances of the second wires are equal, so that the resistance difference of the peripheral wires can be well compensated, and poor display caused by the resistance difference of the peripheral wires is avoided.
It should be noted that the array substrate provided by the embodiment of the present invention is particularly suitable for a display panel with high resolution, because the higher the resolution of the display panel is, the more the number of pixels in the display panel is, and correspondingly, the more the number of signal lines and peripheral traces is, the greater the difference in length between the peripheral traces in the middle area and the peripheral traces in the two side areas is, and the greater the difference in resistance between the peripheral traces in the middle area and the peripheral traces in the two side areas is, the greater the difference in resistance between the peripheral traces can be improved by using the array substrate provided by the embodiment of the present invention.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, the number of groups of the first wires arranged in a fan shape can be determined according to the number of the peripheral wires, for example, the greater the number of the peripheral wires, the greater the number of groups of the first wires arranged in a fan shape.
In specific implementation, the array substrate provided by the embodiment of the invention can be applied to a Liquid Crystal Display (LCD); alternatively, the array substrate provided in the embodiment of the invention may be applied to an Organic Light Emitting Diode (OLED), which is not limited herein. The following embodiments of the present invention are described by taking an example in which the array substrate can be applied to an LCD.
In specific implementation, when the array substrate provided by the embodiment of the invention is applied to an LCD, the driving chip may be a gate driving circuit; alternatively, the driving chip may be a source driving circuit, which is not limited herein.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the driving chip is a gate driving circuit, the signal lines in the display area are gate lines, the gate lines are electrically connected to the gate driving circuit through the peripheral trace, and the gate driving circuit can load a gate scanning signal to each gate line. Specifically, the gate driving circuit may be bound in a non-display region of the array substrate.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the driving chip is a source driving circuit, the signal lines in the display area are data lines, the data lines are electrically connected to the source driving circuit through the peripheral traces, and the source driving circuit can load gray-scale signals to the data lines. Specifically, the source driving circuit may be directly disposed in the non-display region of the array substrate.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, in order to achieve that the resistances of the first traces are equal, the following two setting structures are specifically used to implement: the lengths of the first wires can be set to be equal and the line widths can be set to be equal; or, in each group of first wires, along the arrangement direction of the first wires, the line width of the first wires is set to be gradually reduced and then gradually increased, and the length of the first wires is set to be gradually reduced and then gradually increased; and are not limited herein.
The following describes in detail a specific implementation manner of the array substrate provided by the embodiment of the present invention when the two arrangement structures are applied to the array substrate respectively, by using two specific examples.
Example one: the first wires are equal in length and equal in line width.
As shown in fig. 2, each first trace 21 includes a first sub-trace 211 electrically connected to the corresponding second trace 22 and a second sub-trace 212 electrically connected to the signal line; in each group of first traces 21, each first sub-trace 211 is in a straight line shape, the extension lines of the first sub-traces 211 converge at least one point, the convergence point is located at one side of each first sub-trace 211 close to the driving chip 1, and the length of the first sub-trace 211 gradually decreases and then gradually increases along the arrangement direction of the first trace 21 (i.e., perpendicular to the extending direction of the second sub-trace 212, as shown by the arrow in fig. 2); in each group of the first traces 21, the second sub-traces 212 located in the middle area a 'are curved, the second sub-traces 212 located in the two side areas b' are straight, and the lengths of the second sub-traces 212 first gradually increase and then gradually decrease along the arrangement direction of the first traces 21 (i.e., perpendicular to the extending direction of the second sub-traces 212, as shown by the arrow in fig. 2); so that the lengths of the first tracks 21 in each group of first tracks 21 can be guaranteed to be equal.
Of course, in order to realize that the length of the second sub-trace gradually increases and then gradually decreases, the shape of the second sub-trace 212 located in the middle area a 'is not limited to be a curved line, and the shape of the second sub-trace 212 located in the two side areas b' is a straight line as shown in fig. 2, but the shape of the second sub-trace located in the middle area may also be a broken line, and the shape of the second sub-trace located in the two side areas may also be a straight line, which is not limited herein.
It should be noted that, in the array substrate provided in the embodiment of the present invention, in each group of the first traces, respective proportions of the middle area and the two side areas may be set according to actual needs, and are not specifically limited herein.
Preferably, in the array substrate provided in the embodiment of the present invention, the number of the first traces included in each group of the first traces may be set to be equal, so that the effect of compensating for the difference in resistance of each group of the first traces is ensured to be the same, thereby further optimizing the effect of compensating for the difference in resistance of the peripheral traces.
Example two: in each group of first wires, along the arrangement direction of the first wires, the line width of the first wires is gradually reduced and then gradually increased, and the length of the first wires is gradually reduced and then gradually increased.
As shown in fig. 3, each first trace 21 includes a first sub-trace 211 electrically connected to the corresponding second trace 22 and a second sub-trace 212 electrically connected to the signal line; in each group of first traces 21, each first sub-trace 211 is in a straight line shape, the extension lines of the first sub-traces 211 converge at least one point, the convergence point is located at one side of each first sub-trace 211 close to the driving chip 1, and the length of the first sub-trace 211 gradually decreases and then gradually increases along the arrangement direction of the first trace 21 (i.e., perpendicular to the extending direction of the second sub-trace 212, as shown by the arrow in fig. 3); in each group of the first wires 21, each second sub-wire 212 is straight, and the lengths of the second sub-wires 212 are equal; so that the lengths of the first traces 21 in each group of the first traces 21 can be ensured to be gradually reduced and then gradually increased.
Preferably, in the array substrate provided in the embodiment of the present invention, the number of the first traces included in each group of the first traces may be set to be equal, so that the effect of compensating for the difference in resistance of each group of the first traces is ensured to be the same, thereby further optimizing the effect of compensating for the difference in resistance of the peripheral traces.
In specific implementation, in the array substrate provided in the embodiment of the present invention, the second routing lines in a zigzag shape are not limited to the structures shown in fig. 2 and fig. 3, and may also be the structure shown in fig. 4, which is not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including: the array substrate provided by the embodiment of the invention. The implementation of the display panel can refer to the above embodiment of the array substrate, and repeated descriptions are omitted.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided in the embodiment of the present invention, where the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
In the array substrate, the display panel and the display device provided by the embodiment of the invention, the peripheral traces in the non-display area of the array substrate include at least two sets of first traces arranged in a fan shape and second traces which are in a zigzag shape and correspond to the first traces one by one and are electrically connected with each other, compared with the structure that the peripheral traces in the non-display area of the existing array substrate are arranged in a fan shape as a whole, the number of the first traces included in each set of first traces arranged in a fan shape is small, the difference between the resistance of the first traces in the middle area and the resistance of the first traces in the two side areas in each set of first traces is small, the equal resistance of the first traces in each set of first traces can be easily realized by increasing the length of the first traces in the middle area or increasing the line width of the first traces in the two side areas, and the lengths of the second traces are equal and the line widths are equal, namely, the resistance of each second wire is equal, so that the resistance difference of the peripheral wires can be well compensated.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An array substrate, comprising: a display area and a non-display area; the non-display area is internally provided with peripheral wires which electrically connect the signal wires in the display area to the driving chip; the method is characterized in that:
the peripheral wires comprise at least two groups of first wires which are arranged in a fan shape and fold-line-shaped second wires which correspond to the first wires one by one and are electrically connected; wherein,
the resistances of the first wires are equal, and the first wires are electrically connected with the signal wires;
the second wires are equal in length and equal in line width and are electrically connected with the driving chip.
2. The array substrate of claim 1, wherein the first traces are equal in length and equal in line width.
3. The array substrate according to claim 2, wherein each of the first traces includes a first sub-trace electrically connected to the corresponding second trace and a second sub-trace electrically connected to the signal line;
in each group of first wires, each first sub-wire is in a straight line shape, the extension lines of the first sub-wires are converged at least one point, the convergence point is located at one side of each first sub-wire close to the driving chip, and the length of each first sub-wire is gradually reduced and then gradually increased along the arrangement direction of the first wires;
in each group of first wires, the second sub-wires located in the middle area are curved, the second sub-wires located in the two side areas are straight, and the lengths of the second sub-wires are gradually increased and then gradually decreased along the arrangement direction of the first wires.
4. The array substrate according to claim 1, wherein in each group of the first traces, along the arrangement direction of the first traces, the line width of the first traces gradually decreases and then gradually increases, and the length of the first traces gradually decreases and then gradually increases.
5. The array substrate according to claim 4, wherein each of the first traces includes a first sub-trace electrically connected to the corresponding second trace and a second sub-trace electrically connected to the signal line;
in each group of first wires, each first sub-wire is in a straight line shape, the extension lines of the first sub-wires are converged at least one point, the convergence point is located at one side of each first sub-wire close to the driving chip, and the length of each first sub-wire is gradually reduced and then gradually increased along the arrangement direction of the first wires;
in each group of the first routing lines, each second sub-routing line is in a straight line shape, and the lengths of the second sub-routing lines are equal.
6. The array substrate according to any one of claims 1 to 5, wherein the number of the first traces included in each group of the first traces is equal.
7. The array substrate of any one of claims 1-5, wherein the driving chip is a gate driving circuit;
the signal line is a gate line.
8. The array substrate of any one of claims 1-5, wherein the driving chip is a source driving circuit;
the signal line is a data line.
9. A display panel, comprising: the array substrate according to any one of claims 1 to 8.
10. A display device, comprising: the display panel of claim 9.
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