CN106222619A - A kind of substrate, substrate and preparation method thereof, electronic device - Google Patents
A kind of substrate, substrate and preparation method thereof, electronic device Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 149
- 238000002360 preparation method Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000001816 cooling Methods 0.000 claims abstract description 10
- 238000010884 ion-beam technique Methods 0.000 claims description 23
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- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
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- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
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- 239000010410 layer Substances 0.000 description 187
- 239000010408 film Substances 0.000 description 48
- 230000015572 biosynthetic process Effects 0.000 description 17
- 238000000151 deposition Methods 0.000 description 17
- 238000005755 formation reaction Methods 0.000 description 17
- 230000008021 deposition Effects 0.000 description 14
- 229920006254 polymer film Polymers 0.000 description 7
- 229920005570 flexible polymer Polymers 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- -1 HIZO Substances 0.000 description 1
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- 230000002411 adverse Effects 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 239000005457 ice water Substances 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/10—Glass or silica
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- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
- H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10F10/00—Individual photovoltaic cells, e.g. solar cells
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Abstract
本发明涉及电子器件技术领域,公开了一种基底、基板及其制作方法、电子器件。本发明的基底包括一衬底的表面形成缓冲层的步骤,并通过多次成膜工艺形成所需厚度的缓冲层,每次成膜工艺形成的子缓冲层的厚度较薄,而且在形成每一子缓冲层后均进行降温处理,使得基底的整体温度始终较低,减少了内应力的产生。同时,由于缓冲层的热膨胀系数小于衬底的热膨胀系数,使得缓冲层具有较好的耐热性,从而能够在高温环境下在缓冲层上制作电子器件的各功能薄膜,保证成膜质量,并减少薄膜内应力的产生,提高电子器件的品质。
The invention relates to the technical field of electronic devices, and discloses a base, a substrate, a manufacturing method thereof, and an electronic device. The substrate of the present invention includes a step of forming a buffer layer on the surface of a substrate, and forms a buffer layer with a required thickness through multiple film forming processes. After each sub-buffer layer, cooling treatment is carried out, so that the overall temperature of the substrate is always low, and the generation of internal stress is reduced. At the same time, since the thermal expansion coefficient of the buffer layer is smaller than that of the substrate, the buffer layer has better heat resistance, so that various functional films of electronic devices can be fabricated on the buffer layer in a high temperature environment, ensuring the film quality and Reduce the generation of internal stress in the film and improve the quality of electronic devices.
Description
技术领域technical field
本发明涉及电子器件技术领域,特别是涉及一种基底、基板及其制作方法、电子器件。The invention relates to the technical field of electronic devices, in particular to a substrate, a substrate and a manufacturing method thereof, and an electronic device.
背景技术Background technique
近年来,伴随着电子器件不断向轻量化、薄型化和柔性化方向发展,柔性器件,如:LCD显示器和OLED显示器、柔性薄膜太阳能电池,引起了人们高度关注。在柔性的聚合物薄膜基底上沉积透明导电层制作柔性的透明导电基板,从而取代传统的硬质玻璃导电基板是实现电子器件柔性化的核心技术。In recent years, with the continuous development of electronic devices in the direction of light weight, thinning and flexibility, flexible devices, such as LCD displays and OLED displays, and flexible thin-film solar cells, have attracted great attention. Depositing a transparent conductive layer on a flexible polymer film substrate to make a flexible transparent conductive substrate, thereby replacing the traditional hard glass conductive substrate is the core technology for realizing the flexibility of electronic devices.
然而,聚合物薄膜基底材料耐热性较差,透明导电层只能在较低的温度下进行沉积,不易获得具有良好沉积质量的透明导电层。同时,在较高温度下沉积透明导电层时,由于透明导电层与聚合物薄膜的热膨胀系数相差较大,容易产生较大的内应力,上述因素均会对柔性器件的相关性能产生不利影响。However, the polymer film base material has poor heat resistance, and the transparent conductive layer can only be deposited at a relatively low temperature, so it is difficult to obtain a transparent conductive layer with good deposition quality. At the same time, when the transparent conductive layer is deposited at a higher temperature, due to the large difference in thermal expansion coefficient between the transparent conductive layer and the polymer film, it is easy to generate a large internal stress, and the above factors will adversely affect the performance of the flexible device.
发明内容Contents of the invention
本发明提供一种基底、基板及其制作方法、电子器件,用以解决如何耐热性较好的基底的问题。The invention provides a substrate, a substrate, a manufacturing method thereof, and an electronic device to solve the problem of how to obtain a substrate with better heat resistance.
为解决上述技术问题,本发明实施例中提供一种基底的制作方法,包括在一衬底的表面形成缓冲层的步骤,形成缓冲层的步骤包括:In order to solve the above technical problems, an embodiment of the present invention provides a substrate manufacturing method, including the step of forming a buffer layer on the surface of a substrate, and the step of forming the buffer layer includes:
在所述衬底的表面形成子缓冲层,并对所述子缓冲层进行降温处理;forming a sub-buffer layer on the surface of the substrate, and performing a cooling treatment on the sub-buffer layer;
重复上述步骤,形成多个子缓冲层,由所述多个子缓冲层层叠形成所述缓冲层,所述缓冲层的热膨胀系数小于所述衬底的热膨胀系数。Repeating the above steps to form a plurality of sub-buffer layers, the buffer layer is formed by laminating the plurality of sub-buffer layers, and the coefficient of thermal expansion of the buffer layer is smaller than the coefficient of thermal expansion of the substrate.
本发明实施例中还提供一种透明导电基板的制作方法,采用如上所述的制作方法形成基底,在所述基底的缓冲层上形成透明导电层。An embodiment of the present invention also provides a method for manufacturing a transparent conductive substrate, using the above-mentioned manufacturing method to form a base, and forming a transparent conductive layer on the buffer layer of the base.
本发明实施例中还提供一种显示基板的制作方法,包括:An embodiment of the present invention also provides a method for manufacturing a display substrate, including:
采用如上所述的制作方法形成基底;Forming the substrate by the manufacturing method as described above;
在所述基底的缓冲层上形成显示用的各膜层结构。Various film layer structures for display are formed on the buffer layer of the base.
本发明实施例中还提供一种基底,采用如上所述的制作方法制得,所述基底包括衬底和接触设置在所述衬底上的缓冲层,所述缓冲层包括多个层叠设置的子缓冲层,所述缓冲层的热膨胀系数小于所述衬底的热膨胀系数。An embodiment of the present invention also provides a substrate, which is manufactured by the above-mentioned manufacturing method, the substrate includes a substrate and a buffer layer contacted on the substrate, and the buffer layer includes a plurality of stacked A sub-buffer layer, the thermal expansion coefficient of the buffer layer is smaller than the thermal expansion coefficient of the substrate.
本发明实施例中还提供一种透明导电基板,包括:An embodiment of the present invention also provides a transparent conductive substrate, including:
如上所述的基底;substrate as described above;
形成在所述基底的缓冲层上的透明导电层。A transparent conductive layer is formed on the buffer layer of the substrate.
本发明实施例中还提供一种显示基板,其特征在于,包括:An embodiment of the present invention also provides a display substrate, which is characterized in that it includes:
如上所述的基底;substrate as described above;
设置在所述基底的缓冲层上的显示用的各膜层结构。Each film layer structure for display is arranged on the buffer layer of the base.
本发明实施例中还提供一种电子器件,采用如上所述的基底。An electronic device is also provided in an embodiment of the present invention, using the above-mentioned substrate.
本发明的上述技术方案的有益效果如下:The beneficial effects of above-mentioned technical scheme of the present invention are as follows:
上述技术方案中,通过多次成膜工艺形成所需厚度的缓冲层,每次成膜工艺形成的子缓冲层的厚度较薄,而且在形成每一子缓冲层后均进行降温处理,使得基底的整体温度始终较低,减少了内应力的产生。同时,由于缓冲层的热膨胀系数小于衬底的热膨胀系数,使得缓冲层具有较好的耐热性,从而能够在高温环境下在缓冲层上制作电子器件的各功能薄膜,保证成膜质量,并减少薄膜内应力的产生,提高电子器件的品质。In the above technical scheme, the buffer layer with the required thickness is formed through multiple film-forming processes, the thickness of the sub-buffer layer formed by each film-forming process is relatively thin, and after the formation of each sub-buffer layer, a cooling treatment is performed, so that the substrate The overall temperature is always low, reducing the generation of internal stress. At the same time, since the thermal expansion coefficient of the buffer layer is smaller than that of the substrate, the buffer layer has better heat resistance, so that various functional films of electronic devices can be fabricated on the buffer layer in a high temperature environment, ensuring the film quality and Reduce the generation of internal stress in the film and improve the quality of electronic devices.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1表示本发明实施例中基底的立体图;Fig. 1 represents the perspective view of substrate in the embodiment of the present invention;
图2表示图1的主视图;Fig. 2 represents the front view of Fig. 1;
图3-图5表示本发明实施例中基底的制作过程示意图;Fig. 3-Fig. 5 represent the schematic diagram of the manufacturing process of the substrate in the embodiment of the present invention;
图6表示本发明实施例中透明导电基板的立体图;6 shows a perspective view of a transparent conductive substrate in an embodiment of the present invention;
图7表示图6的主视图;Fig. 7 represents the front view of Fig. 6;
图8表示本发明实施例中透明导电基板的制作方法流程图。FIG. 8 shows a flowchart of a method for manufacturing a transparent conductive substrate in an embodiment of the present invention.
具体实施方式detailed description
下面将结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。The specific implementation manner of the present invention will be further described in detail below with reference to the drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
实施例一Embodiment one
对于电子器件,例如:显示器件、太阳能电池等,需要提供承载各功能膜层结构的基底,基底的质量对电子器件的品质具有直接的影响。For electronic devices, such as display devices, solar cells, etc., it is necessary to provide a substrate for carrying various functional film structures, and the quality of the substrate has a direct impact on the quality of the electronic device.
本发明中基底的质量具体是指基底的耐热性,较高的耐热性能够保证在高温环境下在所述基底上成膜,提高成膜质量,并减少内应力的产生。The quality of the substrate in the present invention specifically refers to the heat resistance of the substrate. Higher heat resistance can ensure the formation of a film on the substrate in a high temperature environment, improve the quality of the film formation, and reduce the generation of internal stress.
本实施例中提供一种基底及其制作方法,即用以提高基底的耐热性。In this embodiment, a substrate and a manufacturing method thereof are provided, which are used to improve the heat resistance of the substrate.
结合图1-图5所示,所述制作方法包括在一衬底10的表面形成缓冲层1的步骤,形成缓冲层1的步骤包括:As shown in FIGS. 1-5 , the manufacturing method includes the step of forming a buffer layer 1 on the surface of a substrate 10, and the step of forming the buffer layer 1 includes:
在衬底10的表面形成子缓冲层11,并对子缓冲层11进行降温处理;Forming a sub-buffer layer 11 on the surface of the substrate 10, and performing a cooling treatment on the sub-buffer layer 11;
重复上述步骤,形成多个子缓冲层11,由多个子缓冲层11形成缓冲层1,缓冲层1的热膨胀系数小于衬底10的热膨胀系数。The above steps are repeated to form a plurality of sub-buffer layers 11 . The buffer layer 1 is formed from the plurality of sub-buffer layers 11 . The coefficient of thermal expansion of the buffer layer 1 is smaller than that of the substrate 10 .
上述制作方法,通过多次成膜工艺在衬底上形成缓冲层,直至缓冲层的厚度达到要求。其中,缓冲层的厚度已知,则每次成膜的厚度小于缓冲层的最终厚度,多次成膜层叠累积形成最终厚度。即,子缓冲层的厚度小于缓冲层1的厚度,多个子缓冲层11层叠后的厚度为缓冲层1的厚度。In the above manufacturing method, a buffer layer is formed on the substrate through multiple film forming processes until the thickness of the buffer layer reaches the requirement. Wherein, the thickness of the buffer layer is known, the thickness of each film formation is smaller than the final thickness of the buffer layer, and the final thickness is formed by stacking multiple film formations. That is, the thickness of the sub-buffer layer is smaller than the thickness of the buffer layer 1 , and the thickness of the stacked sub-buffer layers 11 is equal to the thickness of the buffer layer 1 .
需要说明的是,材料的热膨胀系数越小,其受热的形变量越小,耐热性越好。It should be noted that the smaller the coefficient of thermal expansion of the material, the smaller its deformation when heated, and the better the heat resistance.
结合图1和图2所示,通过上述制作方法制得的基底包括衬底10和接触设置在衬底10上的缓冲层1,缓冲层1包括多个层叠设置的子缓冲层11,缓冲层1的热膨胀系数小于衬底10的热膨胀系数。As shown in FIG. 1 and FIG. 2, the substrate prepared by the above manufacturing method includes a substrate 10 and a buffer layer 1 arranged in contact with the substrate 10. The buffer layer 1 includes a plurality of stacked sub-buffer layers 11, and the buffer layer The coefficient of thermal expansion of 1 is smaller than the coefficient of thermal expansion of the substrate 10 .
本发明的技术方案通过多次成膜工艺形成所需厚度的缓冲层,每次成膜工艺形成的子缓冲层的厚度较薄,而且在形成每一子缓冲层后均进行降温处理,使得基底的整体温度始终较低,减少了内应力的产生。同时,由于缓冲层的热膨胀系数小于衬底的热膨胀系数,使得缓冲层具有较好的耐热性,从而能够在高温环境下在缓冲层上制作电子器件的各功能薄膜,保证成膜质量,并减少薄膜内应力的产生,提高电子器件的品质。The technical proposal of the present invention forms the buffer layer of required thickness through multiple film-forming processes, and the thickness of the sub-buffer layer formed by each film-forming process is relatively thin, and after each sub-buffer layer is formed, the temperature is lowered, so that the substrate The overall temperature is always low, reducing the generation of internal stress. At the same time, since the thermal expansion coefficient of the buffer layer is smaller than that of the substrate, the buffer layer has better heat resistance, so that various functional films of electronic devices can be fabricated on the buffer layer in a high temperature environment, ensuring the film quality and Reduce the generation of internal stress in the film and improve the quality of electronic devices.
其中,多个子缓冲层11的厚度可以一致或不一致。本实施例中设置多个子缓冲层11的厚度一致,成膜参数相同,如:成膜时间,简化缓冲层的制作工艺。在实际应用过程中,可以根据温度需求以及缓冲层1的厚度来设置子缓冲层11的厚度,防止形成每一子缓冲层11后基底的整体温度较高,产生较大的内应力。例如:设置缓冲层1包括至少4个子缓冲层11。Wherein, the thicknesses of the multiple sub-buffer layers 11 may be uniform or inconsistent. In this embodiment, the thicknesses of the plurality of sub-buffer layers 11 are set to be the same, and the film-forming parameters are the same, such as the film-forming time, so as to simplify the manufacturing process of the buffer layers. In actual application, the thickness of the sub-buffer layer 11 can be set according to the temperature requirement and the thickness of the buffer layer 1, so as to prevent the overall temperature of the substrate after each sub-buffer layer 11 is formed from being high, resulting in greater internal stress. For example: the setting buffer layer 1 includes at least 4 sub-buffer layers 11 .
具体可以通过磁控溅射成膜工艺形成子缓冲层11,因为磁控溅射成膜工艺具有高速、低温、镀膜面积大和附着力强等优点,能够在较低温度环境下实现快速成膜,进一步减少内应力的产生。而且成膜的附着力强,能够增加衬底10和缓冲层1的结合力,使缓冲层1不易从衬底10上剥离。Specifically, the sub-buffer layer 11 can be formed by a magnetron sputtering film formation process, because the magnetron sputtering film formation process has the advantages of high speed, low temperature, large coating area and strong adhesion, and can realize rapid film formation in a relatively low temperature environment. Further reduce the generation of internal stress. Moreover, the adhesion of the film formation is strong, which can increase the bonding force between the substrate 10 and the buffer layer 1 , making it difficult for the buffer layer 1 to peel off from the substrate 10 .
本发明的技术方案尤其适用于柔性基底及其制作,因为柔性基底的衬底为聚合物薄膜,其耐热性较差,限制了电子器件的各功能薄膜的成膜温度,降低成膜质量,而且会产生较大的内应力,影响电子器件的品质,通过本发明的技术方案可以很好地解决该技术问题。当然,本发明的技术方案也适用于玻璃基底、石英基底等非柔性基底及其制作。The technical solution of the present invention is especially suitable for flexible substrates and their production, because the substrate of the flexible substrate is a polymer film, which has poor heat resistance, limits the film-forming temperature of various functional films of electronic devices, and reduces the film-forming quality. Moreover, relatively large internal stress will be generated, which will affect the quality of electronic devices. This technical problem can be well solved by the technical solution of the present invention. Of course, the technical solution of the present invention is also applicable to non-flexible substrates such as glass substrates and quartz substrates and their fabrication.
对于柔性基底,衬底10为柔性衬底,其材料可以选择PET、PC、PEN、PI中的一种。For a flexible substrate, the substrate 10 is a flexible substrate, and its material can be selected from one of PET, PC, PEN, and PI.
为了改善基底的耐热性,缓冲层1选择热膨胀系数较小的材料,例如:SiO2、TiO2、CeO2中的一种。可选的,每一子缓冲层11的材料相同,以降低成本,简化缓冲层1的制作工艺。In order to improve the heat resistance of the substrate, the buffer layer 1 selects a material with a small thermal expansion coefficient, such as one of SiO 2 , TiO 2 , and CeO 2 . Optionally, the material of each sub-buffer layer 11 is the same, so as to reduce the cost and simplify the manufacturing process of the buffer layer 1 .
在形成多个每一子缓冲层11后,均需对子缓冲层11进行降温处理,减少内应力的产生。其中,实现降温的方式有很多种,例如:冰水浴、通风。After forming multiple sub-buffer layers 11 , it is necessary to lower the temperature of the sub-buffer layers 11 to reduce the generation of internal stress. Among them, there are many ways to achieve cooling, for example: ice water bath, ventilation.
结合图3-图5所示,本实施例中对子缓冲层11进行降温处理的步骤具体为:As shown in FIGS. 3-5 , the steps for cooling the sub-buffer layer 11 in this embodiment are as follows:
采用离子束(对应附图中带箭头的线)对子缓冲层11的表面进行处理。The surface of the sub-buffer layer 11 is treated with an ion beam (corresponding to the line with the arrow in the drawing).
具体可以采用Ar+离子束对子缓冲层11的表面进行处理。Specifically, Ar + ion beams may be used to treat the surface of the sub-buffer layer 11 .
上述步骤通过离子束对子缓冲层11的表面进行处理,来实现降温,可以在完成成膜后,立即进行降温,具有高效、快捷、方便等优点。而且多次沉积,每一子缓冲层11均经过离子束的处理,能够获得致密均匀的缓冲层1。同时,经离子束表面处理后,缓冲层1表面的有效表面积增大,设置在缓冲层1上的薄膜与缓冲层1界面间的咬合作用增强,增加层间结合力,使得电子器件的各功能薄膜不易从基底上剥离。对于柔性器件,较大的层间结合力还能够提高抗弯折性。当在缓冲层1上接触设置导电层时,由于经离子束处理后,缓冲层1与导电层的界面存在电偶极子之间的相互作用,能够促进导电层形成多晶态,提高导电层的导电性。In the above steps, the surface of the sub-buffer layer 11 is treated with ion beams to achieve cooling, and the cooling can be performed immediately after the film formation is completed, which has the advantages of high efficiency, quickness, and convenience. Moreover, after multiple depositions, each sub-buffer layer 11 is treated with an ion beam, so that a dense and uniform buffer layer 1 can be obtained. At the same time, after ion beam surface treatment, the effective surface area of the surface of the buffer layer 1 increases, the interlocking action between the thin film arranged on the buffer layer 1 and the interface of the buffer layer 1 is enhanced, and the interlayer bonding force is increased, so that the functions of the electronic device The film does not peel easily from the substrate. For flexible devices, greater interlayer bonding can also improve bending resistance. When the conductive layer is placed in contact with the buffer layer 1, due to the interaction between the electric dipoles at the interface between the buffer layer 1 and the conductive layer after ion beam treatment, it can promote the formation of polycrystalline state of the conductive layer and improve the performance of the conductive layer. conductivity.
在一个具体的实施方式中,结合图1、图3-图5所示,柔性基底的制作方法具体包括:In a specific embodiment, as shown in Fig. 1, Fig. 3-Fig. 5, the manufacturing method of the flexible substrate specifically includes:
步骤S11、清洗柔性聚合物薄膜衬底10;Step S11, cleaning the flexible polymer film substrate 10;
步骤S12、如图3所示,利用磁控溅射成膜工艺在聚合物薄膜衬底10上沉积一子缓冲层11,沉积温度为100℃,气压为1Pa,沉积功率为200W。当该子缓冲层11的厚度约为20nm时,利用Ar+离子束对子缓冲层11的的表面进行处理,离子束的能量为150eV,入射角为80°,时间为10s;Step S12 , as shown in FIG. 3 , deposit a sub-buffer layer 11 on the polymer film substrate 10 by magnetron sputtering film formation process, the deposition temperature is 100° C., the gas pressure is 1 Pa, and the deposition power is 200 W. When the thickness of the sub-buffer layer 11 is about 20nm, the surface of the sub-buffer layer 11 is treated with Ar + ion beam, the energy of the ion beam is 150eV, the incident angle is 80°, and the time is 10s;
步骤S13、重复步骤S12,参见图4和图5所示,直至缓冲层1的厚度达到100nm,如图1所示。Step S13 , repeating step S12 , as shown in FIG. 4 and FIG. 5 , until the thickness of the buffer layer 1 reaches 100 nm, as shown in FIG. 1 .
在另一个具体的实施方式中,结合图1、图3-图5所示,柔性基底的制作方法具体包括:In another specific embodiment, as shown in Fig. 1, Fig. 3-Fig. 5, the manufacturing method of the flexible substrate specifically includes:
步骤S21、清洗柔性聚合物薄膜衬底10;Step S21, cleaning the flexible polymer film substrate 10;
步骤S22、如图3所示,利用磁控溅射成膜工艺在聚合物薄膜衬底10上沉积一子缓冲层11,沉积温度为100℃,气压为1Pa,沉积功率为200W。当该子缓冲层11厚度约为20nm时,利用Ar+离子束对子缓冲层11的表面进行处理,离子束能量为100eV,入射角为80°,时间为13s;Step S22 , as shown in FIG. 3 , deposit a sub-buffer layer 11 on the polymer film substrate 10 by magnetron sputtering film formation process, the deposition temperature is 100° C., the gas pressure is 1 Pa, and the deposition power is 200 W. When the thickness of the sub-buffer layer 11 is about 20nm, the surface of the sub-buffer layer 11 is treated with Ar + ion beam, the ion beam energy is 100eV, the incident angle is 80°, and the time is 13s;
步骤S23、重复步骤S22,参见图4和图5所示,上直至缓冲层1的厚度达到100nm,如图1所示。Step S23 , repeat step S22 , as shown in FIG. 4 and FIG. 5 , until the thickness of the buffer layer 1 reaches 100 nm, as shown in FIG. 1 .
上述两个实施方式中仅提供两种具体的工艺参数组合,在实际应用过程中,本领域技术人员很容易想到还可以对各工艺参数进行合理调整,其都属于本发明的保护范围,只要能够实现本发明的目的即可。In the above two embodiments, only two specific combinations of process parameters are provided. In the actual application process, those skilled in the art can easily think that each process parameter can be reasonably adjusted, which all belong to the protection scope of the present invention. The object of the present invention can be realized.
本领域技术人员很容易推出,所述缓冲层的材料也可以选择金属材料或透明导电材料,利用上述制作方法制得导电的缓冲层。具体利用磁控溅射成膜工艺形成所述导电的缓冲层。当所述基底为透明基底时,所述导电层选择透明导电材料,例如:HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO。Those skilled in the art can easily deduce that the material of the buffer layer can also be a metal material or a transparent conductive material, and the conductive buffer layer can be prepared by the above-mentioned manufacturing method. Specifically, the conductive buffer layer is formed by using a magnetron sputtering film forming process. When the substrate is a transparent substrate, the conductive layer is made of a transparent conductive material, such as HIZO, ZnO, TiO 2 , CdSnO, MgZnO, IGO, IZO, ITO or IGZO.
实施例二Embodiment two
结合图6-图8所示,本实施例中一种透明导电基板的制作方法,包括:As shown in FIGS. 6-8 , a method for manufacturing a transparent conductive substrate in this embodiment includes:
采用实施例一中的制作方法形成基底;The base is formed by the manufacturing method in Example 1;
在所述基底的缓冲层1上形成透明导电层2。A transparent conductive layer 2 is formed on the buffer layer 1 of the substrate.
通过上述制作方法制得的透明导电基板包括实施例一中的基底,以及设置在所述基底的缓冲层1上的透明导电层2。The transparent conductive substrate prepared by the above manufacturing method includes the substrate in the first embodiment, and the transparent conductive layer 2 disposed on the buffer layer 1 of the substrate.
本实施例中由于透明导电层2接触设置在基底的缓冲层1上,而缓冲层1的热膨胀系数较大,具有较好的耐热性,从而能够在高温环境下形成透明导电层2,保证透明导电层2具有优异的性能。而且缓冲层1与透明导电层2的热膨胀系数差值较小,减少了内应力的产生,提高了透明导电基板的品质。In this embodiment, since the transparent conductive layer 2 is arranged in contact with the buffer layer 1 of the base, and the thermal expansion coefficient of the buffer layer 1 is large, it has better heat resistance, so that the transparent conductive layer 2 can be formed in a high temperature environment, ensuring The transparent conductive layer 2 has excellent properties. Moreover, the thermal expansion coefficient difference between the buffer layer 1 and the transparent conductive layer 2 is small, which reduces the generation of internal stress and improves the quality of the transparent conductive substrate.
本发明的技术方案尤其适用于柔性的透明导电基板及其制作,因为缓冲层的制作能够大大提高基底的耐热性,保证透明导电层的成膜温度,提高透明导电层的性能。当然,本发明的技术方案也适用于非柔性的透明导电基板及其制作,非柔性的透明导电基板可以选择玻璃衬底、石英衬底等。The technical solution of the present invention is especially suitable for flexible transparent conductive substrates and their production, because the production of the buffer layer can greatly improve the heat resistance of the substrate, ensure the film-forming temperature of the transparent conductive layer, and improve the performance of the transparent conductive layer. Of course, the technical solution of the present invention is also applicable to non-flexible transparent conductive substrates and their manufacture, and non-flexible transparent conductive substrates can be selected from glass substrates, quartz substrates, and the like.
至于基底及其制作过程,可以参见实施例一中的描述,在此不再详述。As for the substrate and its manufacturing process, reference may be made to the description in Embodiment 1, which will not be described in detail here.
可选的,在形成缓冲层1的每一子缓冲层11后,采用离子束对子缓冲层11的表面进行处理,能够增大缓冲层1表面的有效表面积,增强缓冲层1与透明导电层2界面间的咬合作用,增加缓冲层1与透明导电层2的结合力,使得透明导电层2不易从基底上剥离。对于柔性器件,较大的层间结合力还能够提高抗弯折性。当在缓冲层1上接触设置透明导电层2时,由于经离子束处理后,缓冲层1与透明导电层2的界面存在电偶极子之间的相互作用,能够促进透明导电层2形成多晶态,提高透明导电层2的导电性。Optionally, after forming each sub-buffer layer 11 of the buffer layer 1, the surface of the sub-buffer layer 11 is treated with an ion beam, which can increase the effective surface area of the buffer layer 1 surface, and strengthen the connection between the buffer layer 1 and the transparent conductive layer. The occlusion between the two interfaces increases the binding force between the buffer layer 1 and the transparent conductive layer 2, so that the transparent conductive layer 2 is not easily peeled off from the substrate. For flexible devices, greater interlayer bonding can also improve bending resistance. When the transparent conductive layer 2 is arranged in contact with the buffer layer 1, due to the interaction between the electric dipoles at the interface between the buffer layer 1 and the transparent conductive layer 2 after the ion beam treatment, the formation of the transparent conductive layer 2 can be promoted. crystalline state, improving the conductivity of the transparent conductive layer 2.
在一个具体的实施方式中,结合图1、图3-图5所示,透明导电基板的制作方法具体包括:In a specific embodiment, as shown in Fig. 1, Fig. 3-Fig. 5, the manufacturing method of the transparent conductive substrate specifically includes:
步骤S11、清洗柔性聚合物薄膜衬底10;Step S11, cleaning the flexible polymer film substrate 10;
步骤S12、如图3所示,利用磁控溅射成膜工艺在聚合物薄膜衬底10上沉积一子缓冲层11,沉积温度为100℃,气压为1Pa,沉积功率为200W。当该子缓冲层11的厚度约为20nm时,利用Ar+离子束对子缓冲层11的的表面进行处理,离子束的能量为150eV,入射角为80°,时间为10s;Step S12 , as shown in FIG. 3 , deposit a sub-buffer layer 11 on the polymer film substrate 10 by magnetron sputtering film formation process, the deposition temperature is 100° C., the gas pressure is 1 Pa, and the deposition power is 200 W. When the thickness of the sub-buffer layer 11 is about 20nm, the surface of the sub-buffer layer 11 is treated with Ar + ion beam, the energy of the ion beam is 150eV, the incident angle is 80°, and the time is 10s;
步骤S13、重复步骤S12,参见图4和图5所示,直至缓冲层1的厚度达到100nm,如图1所示。Step S13 , repeating step S12 , as shown in FIG. 4 and FIG. 5 , until the thickness of the buffer layer 1 reaches 100 nm, as shown in FIG. 1 .
步骤S14、利用磁控溅射成膜工艺在缓冲层1上沉积透明导电层2。沉积温度为100℃,气压为0.5Pa,沉积功率为100W,透明导电层2的厚度为70nm。Step S14 , depositing a transparent conductive layer 2 on the buffer layer 1 by using a magnetron sputtering film forming process. The deposition temperature is 100° C., the gas pressure is 0.5 Pa, the deposition power is 100 W, and the thickness of the transparent conductive layer 2 is 70 nm.
通过上述步骤S11-S14制得的柔性透明导电基板的表面电阻为19Ω/sq,光线透过率为88%。The surface resistance of the flexible transparent conductive substrate prepared through the above steps S11-S14 is 19Ω/sq, and the light transmittance is 88%.
在另一个具体的实施方式中,结合图1、图3-图5所示,透明导电基板的制作方法具体包括:In another specific embodiment, as shown in Fig. 1, Fig. 3-Fig. 5, the manufacturing method of the transparent conductive substrate specifically includes:
步骤S21、清洗柔性聚合物薄膜衬底10;Step S21, cleaning the flexible polymer film substrate 10;
步骤S22、如图3所示,利用磁控溅射成膜工艺在聚合物薄膜衬底10上沉积一子缓冲层11,沉积温度为100℃,气压为1Pa,沉积功率为200W。当该子缓冲层11厚度约为20nm时,利用Ar+离子束对子缓冲层11的表面进行处理,离子束能量为100eV,入射角为80°,时间为13s;Step S22 , as shown in FIG. 3 , deposit a sub-buffer layer 11 on the polymer film substrate 10 by magnetron sputtering film formation process, the deposition temperature is 100° C., the gas pressure is 1 Pa, and the deposition power is 200 W. When the thickness of the sub-buffer layer 11 is about 20nm, the surface of the sub-buffer layer 11 is treated with Ar + ion beam, the ion beam energy is 100eV, the incident angle is 80°, and the time is 13s;
步骤S23、重复步骤S22,参见图4和图5所示,上直至缓冲层1的厚度达到100nm,如图1所示;Step S23, repeat step S22, see Figure 4 and Figure 5, until the thickness of the buffer layer 1 reaches 100nm, as shown in Figure 1;
步骤S24、利用磁控溅射成膜工艺在缓冲层1上沉积透明导电层2。沉积温度为100℃,气压为0.5Pa,沉积功率为100W,透明导电层2的厚度为70nm。Step S24 , depositing a transparent conductive layer 2 on the buffer layer 1 by using a magnetron sputtering film forming process. The deposition temperature is 100° C., the gas pressure is 0.5 Pa, the deposition power is 100 W, and the thickness of the transparent conductive layer 2 is 70 nm.
通过上述步骤S21-S24制得的柔性透明导电基板的表面电阻为27Ω/sq,光线透过率为86%。The surface resistance of the flexible transparent conductive substrate prepared through the above steps S21-S24 is 27Ω/sq, and the light transmittance is 86%.
比较上述两个实施方式可以发现:离子束处理的功率(能量/处理时间)会影响透明导电基板的表面电阻和光线透过率。因为离子束处理的功率越大,缓冲层1与透明导电层2界面的电偶极子之间的相互作用越强,有利于促进透明导电层2形成多晶态,提高透明导电层2的导电性。而且离子束处理的功率越大,越有利于形成致密均匀的缓冲层1,会减小光线的透过率。Comparing the above two embodiments, it can be found that the power (energy/treatment time) of the ion beam treatment will affect the surface resistance and light transmittance of the transparent conductive substrate. Because the greater the power of ion beam treatment, the stronger the interaction between the electric dipoles of the buffer layer 1 and the transparent conductive layer 2 interface, which is conducive to promoting the formation of polycrystalline state of the transparent conductive layer 2 and improving the conductivity of the transparent conductive layer 2. sex. Moreover, the greater the power of the ion beam treatment, the more favorable it is to form a dense and uniform buffer layer 1, which will reduce the transmittance of light.
上述两个实施方式中仅提供两种具体的工艺参数组合,在实际应用过程中,本领域技术人员很容易想到还可以对各工艺参数进行合理调整,其都属于本发明的保护范围,只要能够实现本发明的目的即可。In the above two embodiments, only two specific combinations of process parameters are provided. In the actual application process, those skilled in the art can easily think that each process parameter can be reasonably adjusted, which all belong to the protection scope of the present invention. The object of the present invention can be realized.
实施例三Embodiment Three
本实施例中提供一种显示基板的制作方法,包括:In this embodiment, a method for manufacturing a display substrate is provided, including:
采用实施例一中的制作方法形成基底;The base is formed by the manufacturing method in Example 1;
在所述基底的缓冲层上形成显示用的各膜层结构。Various film layer structures for display are formed on the buffer layer of the base.
通过上述制作方法制得的显示基板包括实施例一中的基底,以及设置在所述基底的缓冲层上的显示用的各膜层结构。The display substrate manufactured by the above manufacturing method includes the substrate in Example 1, and various film layer structures for display disposed on the buffer layer of the substrate.
本实施例中由于显示用的各膜层结构接触设置在基底的缓冲层上,而缓冲层的热膨胀系数较大,具有较好的耐热性,当显示用的导电层接触设置在缓冲层上时,能够在高温环境下形成显示用的导电层,保证显示用的导电层具有优异的性能。而且缓冲层与显示用的导电层的热膨胀系数差值较小,减少了内应力的产生,提高了显示基板的品质。In this embodiment, since each film layer structure used for display is arranged on the buffer layer of the base, and the coefficient of thermal expansion of the buffer layer is relatively large, it has better heat resistance. When the conductive layer used for display is arranged on the buffer layer , the conductive layer for display can be formed in a high-temperature environment, ensuring that the conductive layer for display has excellent performance. Moreover, the thermal expansion coefficient difference between the buffer layer and the conductive layer for display is small, which reduces the generation of internal stress and improves the quality of the display substrate.
本发明的技术方案尤其适用于柔性显示基板及其制作,因为缓冲层的制作能够大大提高基底的耐热性,保证显示用的各膜层结构的成膜温度,提高显示用的各膜层结构的性能。当然,本发明的技术方案也适用于非柔性的显示基板及其制作,非柔性的显示基板可以选择玻璃衬底、石英衬底等。The technical solution of the present invention is especially suitable for flexible display substrates and their manufacture, because the manufacture of the buffer layer can greatly improve the heat resistance of the substrate, ensure the film-forming temperature of each film layer structure used for display, and improve the temperature of each film layer structure used for display. performance. Of course, the technical solution of the present invention is also applicable to non-flexible display substrates and their manufacture, and non-flexible display substrates can be selected from glass substrates, quartz substrates, and the like.
以柔性的有机发光二极管显示基板为例,显示用的各膜层结构包括有机发光二极管,则在所述基底的缓冲层上形成显示用的各膜层结构的步骤具体包括:Taking a flexible organic light emitting diode display substrate as an example, the film layer structure for display includes an organic light emitting diode, and the step of forming the film layer structure for display on the buffer layer of the substrate specifically includes:
在所述基底的缓冲层上形成有机发光二极管,所述有机发光二极管的底电极与所述缓冲层接触设置。An organic light emitting diode is formed on the buffer layer of the base, and the bottom electrode of the organic light emitting diode is arranged in contact with the buffer layer.
通过上述步骤形成的有机发光二极管显示基板,有机发光二极管的底电极接触设置在基底的缓冲层上,能够在高温环境下形成所述底电极,保证底电极具有优异的性能。In the organic light emitting diode display substrate formed through the above steps, the bottom electrode of the organic light emitting diode is arranged in contact with the buffer layer of the substrate, and the bottom electrode can be formed in a high temperature environment to ensure that the bottom electrode has excellent performance.
进一步地,在形成所述缓冲层的每一子缓冲层后,采用离子束对子缓冲层的表面进行处理,能够增大缓冲层表面的有效表面积,增强缓冲层与底电极界面间的咬合作用,增加缓冲层与底电极的结合力,使得底电极不易从基底上剥离,提高显示基板的抗弯折性。同时,由于经离子束处理后,缓冲层与底电极的界面存在电偶极子之间的相互作用,能够促进底电极形成多晶态,提高底电极的导电性。Further, after each sub-buffer layer of the buffer layer is formed, the surface of the sub-buffer layer is treated with an ion beam, which can increase the effective surface area of the buffer layer surface and enhance the interlocking effect between the buffer layer and the bottom electrode interface. , increasing the binding force between the buffer layer and the bottom electrode, making it difficult for the bottom electrode to peel off from the substrate, and improving the bending resistance of the display substrate. At the same time, due to the interaction between the electric dipoles at the interface between the buffer layer and the bottom electrode after the ion beam treatment, the bottom electrode can be promoted to form a polycrystalline state and the conductivity of the bottom electrode can be improved.
至于基底及其制作过程,可以参见实施例一中的描述,在此不再详述。As for the substrate and its manufacturing process, reference may be made to the description in Embodiment 1, which will not be described in detail here.
实施例四Embodiment four
本实施例中提供一种电子器件,所述电子器件可以为触摸屏、显示器件、太阳能电池等,所述电子器件采用实施例一中的基底,提高了电子器件的各功能膜层的成膜质量,保证了电子器件的性能,并减少薄膜内应力的产生。An electronic device is provided in this embodiment, and the electronic device can be a touch screen, a display device, a solar cell, etc., and the electronic device adopts the substrate in Embodiment 1, which improves the film-forming quality of each functional film layer of the electronic device , to ensure the performance of electronic devices and reduce the generation of internal stress in the film.
具体的,对于显示器件,其还包括设置在所述基底的缓冲层上的显示用的各膜层结构。由于缓冲层的设置提高了基底的耐热性,从而能够在高温环境下制作显示用的各膜层结构,保证各膜层结构具有优异的性能,尤其保证与基底的缓冲层接触设置的膜层结构具有优异的性能。同时,还减少了薄膜内应力的产生,提高了显示产品的品质。Specifically, for a display device, it also includes various display film layer structures disposed on the buffer layer of the base. Since the setting of the buffer layer improves the heat resistance of the substrate, it is possible to make the film structure for display in a high temperature environment, ensuring that each film structure has excellent performance, especially the film layer that is in contact with the buffer layer of the substrate. The structure has excellent performance. At the same time, it also reduces the generation of internal stress in the film and improves the quality of display products.
所述显示器件为:液晶显示器件、OLED显示器件、电子纸、手机、平板电脑、电视机笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。The display device is any product or component with a display function such as a liquid crystal display device, an OLED display device, electronic paper, a mobile phone, a tablet computer, a television notebook computer, a digital photo frame, a navigator, and the like.
对于太阳能电池,其还包括透明的前电极,所述前电极接触设置在所述基底的缓冲层上,从而能够在高温环境下形成所述前电极,保证前电极具有优异的性能,并减少薄膜内应力的产生,提高了太阳能电池的品质。然后在所述前电极上依次制备电子传输层、光敏层、空穴传输层与背电极等。For solar cells, it also includes a transparent front electrode, the front electrode contact is arranged on the buffer layer of the substrate, so that the front electrode can be formed in a high temperature environment, ensure that the front electrode has excellent performance, and reduce the film The generation of internal stress improves the quality of solar cells. Then an electron transport layer, a photosensitive layer, a hole transport layer, a back electrode and the like are sequentially prepared on the front electrode.
当然,本发明的技术方案还适用于其他电子器件,在此不再一一列举。Of course, the technical solution of the present invention is also applicable to other electronic devices, which will not be listed here.
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换也应视为本发明的保护范围。The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present invention, some improvements and replacements can also be made, these improvements and replacements It should also be regarded as the protection scope of the present invention.
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