CN106209342B - System for realizing low-frequency clock transmission in xDSL transmission system - Google Patents
System for realizing low-frequency clock transmission in xDSL transmission system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
- H04M3/302—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs
- H04M3/304—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs and using xDSL modems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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Abstract
The invention discloses a system for realizing low-frequency clock transmission in an xDSL transmission system, which comprises: the system comprises a main end and a slave end which are used for carrying out data transmission in an xDSL transmission system, wherein both the main end and the slave end are provided with a Field Programmable Gate Array (FPGA) chip; one end of the FPGA chip is connected with a clock signal phase locking module; the FPGA of the master end and the FPGA of the slave end realize the transmission of low-frequency clock signals in the xDSL transmission system through a high-level data control link HDLC constructed between the FPGA of the master end and the FPGA of the slave end. The invention provides a system for realizing low-frequency clock transmission in an xDSL transmission system, which can lead a high-frequency signal output by a clock signal phase-locking module to be effectively transmitted to an opposite terminal by introducing an FPGA into the xDSL transmission system, effectively solves the phase-locking problem and leads the stability and the universality of the transmission system to be stronger.
Description
Technical Field
The invention relates to a system for low frequency clock transfer for use in communication situations. More particularly, the invention relates to a system for implementing low frequency clock delivery in an xDSL transmission system for use in respective communication protocols or data transmission modes.
Background
xDSL is a generic term for various types of DSL (Digital Subscriber Line) Digital Subscriber lines, including SDSL, HDSL, SHDSL, and the like. Any character or character string of an 'x' table in xDSL is obtained with different signal transmission rates and distances according to different modulation modes. xDSL is an existing transmission technology that uses higher frequencies and corresponding modulation techniques on existing copper telephone lines, i.e., signal processing techniques that add or extract more digital data in the analog line, to achieve high transmission rates. With the advent of xDSL technology, copper lines have evolved from low speed data access, which is only capable of transmitting voice and 56 kbit/s, to high speed data signals. The xDSL access technologies based on copper line transmission, such as SDSL, HDSL, SHDSL, etc., have made copper lines an important means for broadband user access, and become the mainstream technology of broadband access, and are adopted by the majority of users.
Low frequency clock signals (e.g., 1Hz clocks, which are actually "second" signals) are important clock signals in electronic timepieces and many electronic instruments and automatic measurement control devices.
In the xDSL transmission system with the ethernet interface, in some application occasions, it is necessary to transmit the low-frequency clock to the opposite end while normally transmitting the ethernet service data, and maintain the synchronization between the sending end clock and the receiving end clock of the low-frequency clock, and satisfy the small phase jitter.
However, for a low frequency clock, it is necessary to be phase locked to a high frequency clock before transmission to the opposite end via the transmission channel. The need to phase lock the low frequency clock to the high frequency clock is often achieved by a direct digital frequency synthesizer (DDS) digital PLL, and in most applications, frequency stability is not a big problem, as the PLL control loop will typically compensate for any inherent frequency drift. However, in applications where the loop bandwidth is very low, the input clock to the low frequency clock requires a very small loop bandwidth, e.g., the loop bandwidth of a 1Hz clock is only 0.02Hz, and therefore, the frequency drift rate needs to be of particular concern, because when the frequency drift rate is very high, the loop may not respond and compensate at a fast enough rate, which may cause the PLL output to become phase-locked.
Disclosure of Invention
An object of the present invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
The present invention also provides a system for implementing low frequency clock transmission in an xDSL transmission system, which can implement mutual conversion between MII data and HDLC data during data transmission by introducing an FPGA into the xDSL transmission system, so that a high frequency signal output by a clock signal phase-locking module can be effectively transmitted to an opposite terminal, and implement low frequency clock signal transmission in the xDSL transmission system based on the characteristic of mutual synchronization between a master clock and a slave clock of the xDSL transmission system, thereby effectively solving the problem of phase locking and enhancing stability and universality in the transmission system.
The invention also aims to provide a method for realizing the low-frequency clock by using the characteristic that the master clock and the slave clock of an xDSL transmission system are mutually synchronous, selecting to phase-lock the low-frequency clock to the high-frequency clock, transmitting the high-frequency clock to an opposite terminal through a channel of an HDLC (high-level data link control) sending clock, and then carrying out frequency re-division on the opposite terminal to obtain the low-frequency clock, thereby effectively locking the phase of the output of a PLL (phase locked loop) in the application with very low loop bandwidth in the loop bandwidth with very low requirement on the input clock of the low-frequency clock, so that the PLL can adapt to various application environments and has wide adaptability.
To achieve these objects and other advantages in accordance with the present invention, there is provided a system for implementing low frequency clock delivery in an xDSL transmission system, comprising:
the system comprises a main end and a slave end which are used for carrying out data transmission in an xDSL transmission system, wherein both the main end and the slave end are provided with a Field Programmable Gate Array (FPGA) chip;
the FPGA chip at the main end is connected with a clock signal phase-locking module which is used for phase-locking a received external low-frequency clock signal to a high-frequency clock signal;
the FPGA of the master end and the FPGA of the slave end realize the transmission of low-frequency clock signals in the xDSL transmission system through a clock transmission channel on the HDLC through a high-level data control link HDLC constructed between the FPGA of the master end and the FPGA of the slave end.
Preferably, wherein the HDLC construction comprises:
the data transmission chips are respectively arranged on the master end and the slave end in a matched manner, so that the data transmission chips which are suitable for each data transmission mode in an xDSL transmission system are realized through the connection of cables, and each data transmission chip is in communication connection with the FPGA through an HDLC bus.
Preferably, the data transmission chip is configured to accommodate any one of SDSL, HDSL and SHDSL having HDLC interface function.
Preferably, the clock signal phase locking module comprises:
a direct digital frequency synthesizer DDS chip for phase-locking a received external low frequency clock signal to a high frequency clock signal;
a constant temperature crystal oscillator connected with the DDS chip to provide a system clock for the DDS chip, wherein the temperature stability is PPb order of magnitude;
and the filter circuit is connected with the FPGA chip to output the filtered high-frequency clock signal.
Preferably, the FPGA chip and the data transmission chip are connected to a CPU through a parallel bus respectively.
Preferably, the CPU configures the master-slave, rate, and clock mode operating parameters of the data transmission chip to a synchronous mode through a parallel bus.
Preferably, the FPGA is further connected to a PHY interface of the ethernet through an MII data interface, so as to implement data communication in the xDSL transmission system.
Preferably, the system further comprises a power module for respectively providing working power for the CPU, the FPGA and the data transmission chip.
The object of the invention is further achieved by a method of applying said system, comprising:
the clock signal phase-locking module on the master end is used for locking the received external low-frequency clock signal to a high-frequency clock signal in a phase manner;
the FPGA chip on the master end divides the frequency of a high-frequency clock signal output by the slave clock signal phase locking module to generate a corresponding HDLC sending clock based on the principle that the clock signals of the master end and the slave end are synchronous when data transmission is carried out in an xDSL transmission system so as to trigger the HDLC to send corresponding clock signal data to the slave end;
the FPGA chip of the slave end divides the frequency into corresponding low-frequency clock signals based on the received clock signal data, and further realizes the low-frequency clock transmission from the master end to the slave end.
Preferably, the clock signal phase-locking module receives a corresponding parameter configuration from the microprocessor through a configuration interface, and the parameter configuration range includes: the system frequency is configured to be 500 MHz-1 GHz, the loop bandwidth is configured to be 0.001 Hz-0.05 Hz, the feedback frequency division coefficient (S) is 62500000-400000000, and the reference frequency is 1 Hz-800 MHz.
The invention at least comprises the following beneficial effects: firstly, the invention realizes the mutual conversion between MII data and HDLC data in the data transmission process by introducing the FPGA into the xDSL transmission system, so that a high-frequency signal output by a clock signal phase-locking module can be effectively transmitted to an opposite end, and the transmission of a low-frequency clock signal in the xDSL transmission system is realized based on the characteristic that a master clock and a slave clock of the xDSL transmission system are mutually synchronous, the problem of phase locking is effectively solved, and the stability and the universality of the transmission system are stronger.
Secondly, the invention also uses an application system method to utilize the mutual synchronization characteristic of the master clock and the slave clock of the xDSL transmission system, and selects the realization method that the low-frequency clock is phase-locked to the high-frequency clock, and then transmitted to the opposite terminal through the channel of the HDLC sending clock, and the opposite terminal re-frequency-divides the low-frequency clock, thereby realizing effectively locking the phase of the output of the PLL in the application with very low loop bandwidth, and in the loop bandwidth with very small requirement of the input clock of the low-frequency clock, so that the PLL can adapt to various application environments, and has wide adaptability.
Thirdly, in order to realize reliable phase locking under the condition of smaller loop bandwidth, the invention combines the parameter configuration of the DDS and adopts a constant temperature crystal oscillator with the temperature stability of PPb order of magnitude, thereby well solving the problem of phase locking.
Fourthly, the invention adopts the method, transmits the low-frequency clock signal from the master end to the slave end without influencing the transmission of the Ethernet service data, keeps the synchronism of the low-frequency clock signal, and adopts a clock signal phase-locking module, namely a DDS circuit to ensure that the jitter between the master end and the slave end does not exceed +/-20 ns.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
Fig. 1 is a clock transfer flow diagram of a system for implementing low frequency clock transfer in an xDSL transmission system according to an embodiment of the present invention;
fig. 2 is a block diagram of a schematic structure of a system for implementing low-frequency clock transmission in an xDSL transmission system according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a clock signal phase-locking module of a system for implementing low-frequency clock transmission in an xDSL transmission system according to an embodiment of the present invention;
fig. 4 is a flow chart of a system software configuration for implementing low frequency clock delivery in an xDSL transmission system according to another embodiment of the present invention.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
Fig. 2 shows an implementation form of a system for implementing low frequency clock delivery in an xDSL transmission system according to the present invention, which includes:
a master end 1 and a slave end 2 for data transmission in the xDSL transmission system, both of which are provided with a field programmable gate array FPGA chip 110, specifically, the FPGA is connected to an ethernet interface 160, a clock signal phase-locking module, i.e., a clock chip, and a data transmission chip, i.e., an xDSL chip, and the FPGA is connected to a PHY of the ethernet interface through an MII interface; the FPGA is connected with the Ethernet interface, the clock chip and the xDSL chip through the I/O interface, and the FPGA is connected with the PHY of the Ethernet interface through the MII interface; the FPGA is connected with the clock chip through the I/O port and receives an xMHz signal generated by the clock chip (the MHz is one of the fluctuation frequency units, and the 'x' in the xMHz indicates any one megahertz value); the FPGA is connected with the xDSL chip through an HDLC bus, so that the conversion between MII data and an HDLC data format is realized, and an HDLC sending clock is generated after the frequency division of xMHz signals, so as to trigger the HDLC to send data. The xDSL chip is connected with an opposite terminal through a line interface, and the port is connected with the clock chip and receives an xMHz signal generated by the clock chip;
the FPGA chip at the master end is connected with a clock signal phase-locking module 120 for phase-locking the received external low-frequency clock signal to a high-frequency clock signal; namely, the DDS circuit shown in fig. 2, which is configured to generate a corresponding xMHz signal, so as to realize phase locking of the received external low-frequency clock signal to a high-frequency clock signal;
the FPGA of the master end and the FPGA of the slave end are connected with an xDSL chip through an HDLC bus to realize the conversion of MII data and an HDLC data format through a clock transmission channel on the HDLC by constructing a high-level data control link HDLC between the master end and the slave end, and the conversion of the MII data and the HDLC data format is realized by dividing frequency through an xMHz signal to generate an HDLC sending clock to trigger the HDLC to send data, and the xDSL chip is connected with an opposite end through a line interface to further realize the transmission of low-frequency clock signals. By adopting the scheme, the FPGA is introduced into the xDSL transmission system, the mutual conversion between MII data and HDLC data in the data transmission process is realized, so that a high-frequency signal output by the clock signal phase-locked module can be effectively transmitted to an opposite end, and the transmission of a low-frequency clock signal in the xDSL transmission system is realized based on the characteristic of mutual synchronization of a master clock and a slave clock of the xDSL transmission system, the phase-locked problem is effectively solved, and the stability and the universality of the transmission system are higher. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
As shown in fig. 2, in another example, the HDLC construction includes:
the data transmission chips 130 are respectively arranged on the master end and the slave end in a matched manner, so that the data transmission chips 130 adapting to each data transmission mode in the xDSL transmission system are realized through the connection of cables, and each data transmission chip is in communication connection with the FPGA through an HDLC bus. The scheme is adopted, and the data transmission chip is introduced to adapt to the data transmission requirements of different data transmission protocols, so that the data transmission chip has the advantages of stronger universality and adaptability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
In another example, the data transmission chip is configured to adapt to any one of SDSL, HDSL, SHDSL with HDLC interface function. This solution is adopted to make it more versatile and adaptable. Also, this manner is merely an illustration of a preferred example, but not limited thereto. In the implementation of the invention, appropriate replacement and/or modification can be carried out according to the requirements of users.
As shown in fig. 3, in another example, the clock signal phase locking module includes:
a direct digital frequency synthesizer DDS chip 121 for phase-locking a received external low frequency clock signal to a high frequency clock signal;
a constant temperature crystal oscillator 122 connected with the DDS chip to provide a system clock for the DDS chip, wherein the temperature stability is PPb order of magnitude;
and the filter circuit 123 is connected with the DDS chip to filter the high-frequency clock signal output by the DDS chip, and the filter circuit is connected with the FPGA chip to output the filtered high-frequency clock signal. The DDS circuit mainly comprises a DDS chip, a filter circuit, a constant temperature crystal oscillator and the like. The DDS chip is connected with a low-frequency clock input, a constant-temperature crystal oscillator, a filter circuit and a configuration interface 124. The DDS chip phase-locks the low frequency clock input from outside to the high frequency clock, and the high frequency clock is output to the filter circuit for filtering processing. The constant temperature crystal oscillator provides a system clock for the DDS chip, and the temperature stability is PPb order of magnitude. The filter circuit performs filtering processing on the high-frequency clock. The configuration interface receives configuration information of the DDS chip. The invention adopts the constant temperature crystal oscillator with the temperature stability of the order of PPb to well solve the phase locking problem and has the advantages of good implementable effect and good stability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
In another example, as shown in fig. 2, the FPGA chip and the data transmission chip are respectively connected to a processor CPU 140 through a parallel bus. The CPU in the scheme is connected with a clock chip, an FPGA, an xDSL chip and a management interface 150, the CPU configures the function and the clock frequency of the clock chip through an SPI interface, the CPU interacts information such as the speed, the master and the slave and the like with the FPGA through a parallel bus, and the CPU configures the working parameters of a data transmission chip such as the xDSL chip through the parallel bus, wherein the specific configuration mode is that the master-slave, the speed and the clock mode of the xDSL are in a synchronous mode, and the method has the advantages of wide adaptability and operability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
In another example, the CPU configures the master-slave, rate, and clock mode operating parameters of the data transmission chip into a synchronous mode through a parallel bus. The scheme is adopted to configure the relevant parameters of the data transmission chip so as to achieve the effect stated herein, and the method has the advantages of good implementable effect and strong operability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
In another example, the FPGA is further connected to a PHY interface of an ethernet through an MII data interface, so as to implement data communication in the xDSL transmission system. The adoption of the scheme realizes the data communication in the xDSL transmission system, so that the xDSL transmission system has the possibility of practical use and has the advantage of good implementable effect. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
As shown in fig. 2, in another embodiment, a power module 170 is further included for providing operating power to the CPU, the FPGA and the data transmission chip. The power supply part adopting the scheme provides power supplies of 3.3V, 1.5V, 1.8V, 2.5V and the like for a CPU, an FPGA, an xDSL chip and the like so as to meet the working requirement and the requirements of energy conservation and environmental protection, and has the advantages of good implementable effect and strong operability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
The object of the invention is further achieved by a method of applying said system, comprising:
the clock signal phase locking module on the master end locks the received external low-frequency clock signal to a high-frequency clock signal;
the FPGA chip on the master end is based on the principle that the clock signals of the master end and the slave end are synchronous when data transmission is carried out in an xDSL transmission system, namely, a slave end HDLC receiving clock is synchronous with a master end HDLC sending clock;
the FPGA chip of the slave end divides the frequency into corresponding low-frequency clock signals based on the received clock signal data, and further realizes the low-frequency clock transmission from the master end to the slave end. In the xDSL transmission system with the ethernet interface, because the transmitted data is asynchronous ethernet data, how to transfer the synchronization characteristic of the clock to the opposite end without affecting the normal transmission of the ethernet data is a problem to be solved by the present invention. The invention uses the characteristic that the master clock and the slave clock of the xDSL transmission system are mutually synchronous, selects to phase-lock the low-frequency clock to the high-frequency clock, then transmits the low-frequency clock to the opposite end through the channel of the HDLC sending clock, and the opposite end frequency-divides the low-frequency clock, thereby realizing that the phase of the output of the PLL is effectively locked in the application with very low loop bandwidth in the loop bandwidth with very low requirement of the input clock of the low-frequency clock, and the invention has the advantages of good implementable effect, strong operability and good stability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
In another example, the clock signal phase locking module receives a corresponding parameter configuration from a microprocessor through a configuration interface, and the parameter configuration range includes: the system frequency is configured to be 500 MHz-1 GHz, the loop bandwidth is configured to be 0.001 Hz-0.05 Hz, the feedback frequency division coefficient (S) is 62500000-400000000, and the reference frequency is 1 Hz-800 MHz. The scheme is adopted to specifically configure the Ethernet service data transmission method so as to achieve the aim that the method is adopted, the low-frequency clock signal is transmitted from the master end to the slave end while the Ethernet service data transmission is not influenced, the synchronism of the low-frequency clock signal is kept, and the clock signal phase-locking module, namely the DDS circuit, is adopted to ensure that the jitter between the master end and the slave end does not exceed +/-20 ns, so that the Ethernet service data transmission method has the advantages of good implementation effect and strong operability. Also, this manner is merely an illustration of a preferred example, but not limited thereto. When the invention is implemented, appropriate replacement and/or modification can be carried out according to the requirements of users.
Specifically, the clock transmission flow of the method is shown in fig. 1: the special clock chip of the master end locks the low-frequency clock signal to an xMHz clock, the FPGA transmits the clock to the slave end HDLC receiving clock through the HDLC after frequency division is carried out on the xMHz clock, and the FPGA of the slave end divides the frequency from the HDLC receiving clock to obtain the low-frequency clock signal. According to the characteristic that a master end HDLC sending clock and a slave end HDLC receiving clock of the xDSL transmission system are mutually synchronous, a low-frequency clock of the slave end and a low-frequency clock signal of the master end are mutually synchronous, and therefore the transmission of the low-frequency clock signal is achieved.
As shown in fig. 4, the software configuration method is easily implemented by those skilled in the art according to actual needs, so that detailed description of the specific software configuration method is omitted herein, and the essence of the configuration can be described only with the flowchart.
The number of apparatuses and the scale of the process described herein are intended to simplify the description of the present invention. Applications, modifications and variations of the system for low frequency clock delivery in xDSL transmission systems and the method thereof of the present invention will be apparent to those skilled in the art.
While embodiments of the invention have been disclosed above, it is not intended to be limited to the uses set forth in the specification and examples. It can be applied to all kinds of fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. It is therefore intended that the invention not be limited to the exact details and illustrations described and illustrated herein, but fall within the scope of the appended claims and equivalents thereof.
Claims (9)
1. A system for implementing low frequency clock delivery in an xDSL transmission system, characterized by: the method comprises the following steps:
the system comprises a main end and a slave end which are used for carrying out data transmission in an xDSL transmission system, wherein both the main end and the slave end are provided with a Field Programmable Gate Array (FPGA) chip;
the FPGA chip at the main end is connected with a clock signal phase-locking module which is used for phase-locking a received external low-frequency clock signal to a high-frequency clock signal;
the FPGA of the master end and the FPGA of the slave end realize the transmission of low-frequency clock signals in the xDSL transmission system through a clock transmission channel on the HDLC through a high-level data control link HDLC constructed between the master end and the slave end;
the clock signal phase locking module on the master end locks the received external low-frequency clock signal to a high-frequency clock signal;
the FPGA chip on the master end divides the frequency of a high-frequency clock signal output by the slave clock signal phase-locking module based on the principle that the clock signals of the master end and the slave end are synchronous when data transmission is carried out in an xDSL transmission system so as to generate a corresponding HDLC (high-level data link control) sending clock, so that the HDLC is triggered to send corresponding clock signal data to the slave end;
the FPGA chip of the slave end divides the frequency into corresponding low-frequency clock signals based on the received clock signal data, and further realizes the low-frequency clock transmission from the master end to the slave end.
2. The system for implementing low frequency clock delivery in an xDSL transmission system as recited in claim 1, wherein said HDLC constructing comprises:
the data transmission chips are respectively arranged on the master end and the slave end in a matched mode, so that the data transmission chips which are suitable for each data transmission mode in the xDSL transmission system are realized through the connection of cables, and each data transmission chip is in communication connection with the FPGA through an HDLC bus.
3. The system for implementing low frequency clock delivery in an xDSL transmission system as recited in claim 2, wherein the data transmission chip is configured to accommodate any one of SDSL, HDSL, SHDSL with HDLC interface functionality.
4. The system for implementing low frequency clock delivery in an xDSL transmission system as recited in claim 1, wherein the clock signal phase locking module comprises:
a direct digital frequency synthesizer DDS chip for phase-locking a received external low frequency clock signal to a high frequency clock signal;
a constant temperature crystal oscillator connected with the DDS chip to provide a system clock for the DDS chip, wherein the temperature stability is PPb order of magnitude;
and the filter circuit is connected with the FPGA chip to output the filtered high-frequency clock signal.
5. The system of claim 2, wherein the FPGA chip and the data transmission chip are respectively connected to a CPU through a parallel bus.
6. The system for implementing low frequency clock delivery in an xDSL transmission system as recited in claim 5, wherein said CPU configures the master-slave, rate, clock mode operational parameters of the data transmission chip into a synchronous mode via a parallel bus.
7. The system according to claim 1, wherein the FPGA is further connected to the PHY interface of the ethernet via an MII data interface, so as to implement data communication in the xDSL transmission system.
8. The system of claim 1, further comprising a power module for providing operating power to the CPU, the FPGA and the data transmission chip.
9. The system of claim 1, wherein the clock phase lock module receives the corresponding parameter configuration from the microprocessor through a configuration interface, and the parameter configuration range includes: the system frequency is configured to be 500 MHz-1 GHz, the loop bandwidth is configured to be 0.001 Hz-0.05 Hz, the feedback frequency division coefficient is 62500000-400000000, and the reference frequency is 1 Hz-800 MHz.
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| CN201610727717.5A CN106209342B (en) | 2016-08-25 | 2016-08-25 | System for realizing low-frequency clock transmission in xDSL transmission system |
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| CN201610727717.5A CN106209342B (en) | 2016-08-25 | 2016-08-25 | System for realizing low-frequency clock transmission in xDSL transmission system |
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| CN106209342B true CN106209342B (en) | 2022-10-18 |
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| CN112054866A (en) * | 2020-08-18 | 2020-12-08 | 南方电网科学研究院有限责任公司 | Clock synchronization device with clock retention capability |
| CN116015353A (en) * | 2022-11-29 | 2023-04-25 | 四川灵通电讯有限公司 | Enhanced double-stranded copper wire transmission system and implementation method |
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