CN106209090A - A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA - Google Patents
A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA of the present invention, simple and convenient, resolve simple.Described method includes, step 1, and the inside pulse per second (PPS) using external pulse per second (PPS) to be combined unit counts；According to combining unit data output frequencies, its output data sequence number is circulated counting；Two countings all reset at pulse per second (PPS) rising edge time；Step 2, labelling receives second count value and the data sequence number count value of external pulse per second (PPS) rising edge time, calculates interior external clock time difference outside cycle output data, is time difference to be adjusted during synchronism output, and obtains time difference；Step 3, adjusts time difference to be adjusted during synchronism output before combining unit synchronizes and exports pulse into combining unit data, and the error of output pulse is less than ± 10 microseconds, completes combining unit synchronism output.Described system includes that the counting module realized by FPGA, difference calculating module and data output enable module.
Description
Technical field
The present invention relates to power communication industry field, a kind of combining unit pulse per second (PPS) synchronism output based on FPGA
System and method.
Background technology
In order to the physical location carrying out time correlation combination from the electric current of two times transfer device and/or voltage data is called
Combining unit.Combining unit can be an assembly of transformer, it is also possible to be a separate unit.For merging list in industry
Requirement in the technical specification of unit, combining unit sample frequency is 4kHz, and the sample variance time is less than 10 microseconds, adds adopting
The synchronization requirement of sample data so that synchronize the punctual key technology becoming combining unit.In prior art, combining unit exists
The problem that can produce transmission frequency shake in synchronizing process；I.e. sampled value discrete time is more than 10 microseconds, causes the accurate of sampling
Property reduce.
Summary of the invention
For problems of the prior art, it is defeated that the present invention provides a kind of combining unit pulse per second (PPS) based on FPGA to synchronize
Go out system and method, simple and convenient, resolve simple, realize based on FPGA, there is good autgmentability and real-time.
The present invention is to be achieved through the following technical solutions:
A kind of combining unit pulse per second (PPS) synchronism output method, comprises the steps,
Step 1, the inside pulse per second (PPS) using external pulse per second (PPS) to be combined unit counts；Defeated according to combining unit data
Go out frequency, its output data sequence number is circulated counting；Two countings all reset at pulse per second (PPS) rising edge time；
Step 2, labelling receives second count value and the data sequence number count value of external pulse per second (PPS) rising edge time, calculates
Interior external clock time difference outside cycle output data, is time difference to be adjusted during synchronism output, and obtains time difference
Value；
Step 3, after receiving external pulse, the next cycle of internal pulse signal initially enters the presynchronization stage；?
In the presynchronization stage, internal first cycle of pulse per second (PPS) is the metamorphosis stage；Time difference is compensated in time metamorphosis stage
In several pulses front, the time that each impulse compensation arrives is in ± 10 milliseconds；After the metamorphosis stage terminates, combining unit is just
Often output pulse signal, when the outside pulse per second (PPS) rising edge of the next one arrives, internal pulse per second (PPS) exports simultaneously, and data counts value is clear
Zero, enter synchronous phase, it is achieved time difference to be adjusted during synchronism output adjusted into combining unit before combining unit synchronizes
Data output pulse, and the error of output pulse is less than ± 10 microseconds, completes combining unit synchronism output.
Preferably, in step 1, external pulse per second (PPS) can use program master clock or the B code being converted into pulse per second (PPS) or
1588 clocks are as external clock pulse per second (PPS).
Preferably, in step 1, the program master clock outside employing is as the signal source of external pulse per second (PPS), and master clock is
50MHz, the cycle was 20 nanoseconds, and its count value scope is 0～500000000, and the frequency of data output is 4kHz, its count value model
It is trapped among 0～3999.
Further, in step 2, when external pps pulse per second signal rising edge being detected, labelling second count value is C1, data sequence
Number count value is C2, and time difference count value is (C1-12500*C2).
Further, in step 3, combining unit data output frequency be 4kHz, then the cycle is 250 microseconds, corresponding main time
Clock is counted as 12500, before combining unit synchronism output, need to adjust output pulse data sequence number count value by time difference (C1-
12500*C2) compensate.
Further, in step 3, output pulse data sequence number count value need to be adjusted in the range of 12000～13000.
A kind of combining unit pulse per second (PPS) synchronism output system based on FPGA, including the counting module realized by FPGA,
Difference calculating module and data output enable module；
Counting module is for the internal pulse per second (PPS) of the external pulse per second (PPS) of labelling and combining unit；
Difference calculating module is used for when calculating the internal pulse per second (PPS) of combining unit with external pulse per second (PPS) synchronism output needing to adjust
Time difference；
Data output enables module and is used for generating data output enable signal.
Preferably, output enable signal includes that three kinds enable signals generation states, the most asynchronous state, presynchronization shape
State and synchronous regime.
Compared with prior art, the present invention has a following useful technique effect:
The synchronism output that method of the present invention is combined unit by using external pulse per second (PPS) synchronizes, and will exceed
The time difference of range of error is shared in the middle of multiple pulse in range of error, meets its sample variance time less than 10 microseconds
Requirement, simple and convenient；Avoid employing markers method synchronism output, the problem that target algorithm is excessively complicated when resolving.
Method of the present invention realizes based on FPGA, has good autgmentability and real-time, simple in construction, merit
Consume low and the construction cycle is short, low cost；It is prone to debugging by modular setting search problem, there is stronger portability.
Accompanying drawing explanation
Fig. 1 is the principle modules schematic diagram of system described in present example.
Fig. 2 is that in present example, internal pulse per second (PPS) counts schematic diagram with external pulse per second (PPS) difference.
Fig. 3 is output impulsive synchronization schematic diagram in present example.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention is described in further detail, described in be explanation of the invention and
It not to limit.
A kind of combining unit pulse per second (PPS) synchronism output system based on FPGA of the present invention, as it is shown in figure 1, it includes count module
Block, difference calculating module and data output enable module；Counting module is for the external pulse per second (PPS) of labelling and the combining unit internal second
Pulse；Difference calculating module for calculate the internal pulse per second (PPS) of combining unit with need during external pulse per second (PPS) synchronism output to adjust time
Between poor；Data output enables module and is used for generating data output enable signal, comprises three kinds of enable signals and generates state: be asynchronous
State (not having external synchronizing signal), presynchronization state (adjusting before synchronizing) and synchronous regime.The method is different from prior art
The markers method synchronism output of middle employing, algorithm is simple；It realizes based on FPGA, has good autgmentability and real-time, structure
Simply, low in energy consumption and the construction cycle is short, the advantage of low cost.Its detailed step is as follows:
(1) the inside pulse per second (PPS) using external pulse per second (PPS) to be combined unit counts；According to combining unit output frequency,
Its output data sequence number is circulated counting；Two countings all reset at pulse per second (PPS) rising edge time.External pulse per second (PPS) can be adopted
With multiple signal source, such as B code and 1588 clocks, by being converted to the step of pulse per second (PPS) as external clock pulse per second (PPS)；This is excellent
Selecting examples to connect the program master clock outside signal source employing of pulse per second (PPS), master clock is 50MHz, and the cycle was 20 nanoseconds, its
Count value scope is 0～500000000, and the frequency of data output is 4kHz, and its count value scope is 0～3999；
(2) as in figure 2 it is shown, labelling receives external clock pulse per second (PPS) rising edge time second count value and data sequence number counting
Value, calculates interior external clock time difference outside cycle output data, is time difference to be adjusted during synchronism output.Work as inspection
When measuring external pps pulse per second signal rising edge, labelling second count value is C1, and data sequence number count value is C2, and time difference count value is
(C1-12500*C2)；
(3) time difference to be adjusted during synchronism output is adjusted before combining unit synchronizes into combining unit data output arteries and veins
Punching, it is ensured that the error of output pulse, less than ± 10 microseconds, reaches the purpose of combining unit synchronism output with this.Data output
Frequency is 4kHz, then the cycle is 250 microseconds, and corresponding master clock is counted as 12500, before combining unit synchronism output, needs suitably
Adjust output data sequence number count value (adjusting range 12000～13000) to compensate by time difference (C1-12500*C2).
Concrete, as it is shown on figure 3, when receiving external pulse, initially enter presynchronization from the next cycle of internal pulse signal
Stage；In the presynchronization stage, it is the metamorphosis stage in internal first cycle of pulse per second (PPS), in the time of metamorphosis stage, has
4000 data output pulses, several pulses before selecting, compensate by time difference (C1-12500*C2), each compensation
Time all in ± 10 milliseconds, after the metamorphosis stage terminates, the normal output pulse signal of combining unit, outside the next one
When pulse per second (PPS) rising edge arrives, inside exports simultaneously, and data counts resets, and enters synchronous phase, it is achieved combining unit synchronizes defeated
Go out.
Inventive algorithm is simple, and it realizes based on FPGA, has good autgmentability and real-time, simple in construction, power consumption
Low, the advantage of low cost short with the construction cycle.Modularity of the present invention, it is easy to debugging searches problem, and has stronger portability.
The ultimate principle of the present invention and principal character and advantages of the present invention have more than been shown and described.The technology of the industry
Personnel, it should be appreciated that the present invention is not restricted to the described embodiments, simply illustrating this described in above-described embodiment and description
The principle of invention, without departing from the spirit and scope of the present invention, the present invention also has various changes and modifications, and these become
Change and improvement both falls within scope of the claimed invention.Claimed scope by appending claims and
Equivalent defines.
Claims (8)
1. a combining unit pulse per second (PPS) synchronism output method, it is characterised in that comprise the steps,
Step 1, the inside pulse per second (PPS) using external pulse per second (PPS) to be combined unit counts；According to combining unit data output frequency
Rate, is circulated counting to its output data sequence number；Two countings all reset at pulse per second (PPS) rising edge time；
Step 2, labelling receives second count value and the data sequence number count value of external pulse per second (PPS) rising edge time, calculates inside and outside
Clock time difference outside cycle output data, is time difference to be adjusted during synchronism output, and obtains time difference；
Step 3, after receiving external pulse, the next cycle of internal pulse signal initially enters the presynchronization stage；Pre-same
In step section, internal first cycle of pulse per second (PPS) is the metamorphosis stage；If before time difference being compensated in time metamorphosis stage
In dry pulse, the time that each impulse compensation arrives is in ± 10 milliseconds；After the metamorphosis stage terminates, combining unit is the most defeated
Going out pulse signal, when the outside pulse per second (PPS) rising edge of the next one arrives, internal pulse per second (PPS) exports simultaneously, and data counts value resets,
Enter synchronous phase, it is achieved time difference to be adjusted during synchronism output adjusted into combining unit data before combining unit synchronizes
Output pulse, and the error of output pulse is less than ± 10 microseconds, completes combining unit synchronism output.
A kind of combining unit pulse per second (PPS) synchronism output method the most according to claim 1, it is characterised in that in step 1, outward
Connecing pulse per second (PPS) can use program master clock or the B code being converted into pulse per second (PPS) or 1588 clocks as external clock pulse per second (PPS).
A kind of combining unit pulse per second (PPS) synchronism output method the most according to claim 1, it is characterised in that in step 1, adopt
With outside program master clock as the signal source of external pulse per second (PPS), master clock is 50MHz, and the cycle was 20 nanoseconds, its count value
Scope is 0～500000000, and the frequency of data output is 4kHz, and its count value scope is 0～3999.
A kind of combining unit pulse per second (PPS) synchronism output method the most according to claim 3, it is characterised in that in step 2, when
When external pps pulse per second signal rising edge being detected, labelling second count value is C1, and data sequence number count value is C2, time difference count value
For (C1-12500*C2).
A kind of combining unit pulse per second (PPS) synchronism output method the most according to claim 4, it is characterised in that in step 3, close
And the frequency of cell data output is 4kHz, then the cycle is 250 microseconds, and corresponding master clock is counted as 12500, same in combining unit
Before step output, output pulse data sequence number count value need to be adjusted and compensate by time difference (C1-12500*C2).
A kind of combining unit pulse per second (PPS) synchronism output method the most according to claim 5, it is characterised in that in step 3, need
Adjust output pulse data sequence number count value in the range of 12000～13000.
7. a combining unit pulse per second (PPS) synchronism output system based on FPGA, it is characterised in that include by FPGA realization
Counting module, difference calculating module and data output enable module；
Counting module is for the internal pulse per second (PPS) of the external pulse per second (PPS) of labelling and combining unit；
Difference calculating module for calculate the internal pulse per second (PPS) of combining unit with need during external pulse per second (PPS) synchronism output to adjust time
Between poor；
Data output enables module and is used for generating data output enable signal.
A kind of combining unit pulse per second (PPS) synchronism output system based on FPGA the most according to claim 7, it is characterised in that
Output enables signal and includes that three kinds enable signal generation state, the most asynchronous state, presynchronization state and synchronous regime.
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| CN113900480A (en) * | 2021-12-10 | 2022-01-07 | 成都金诺信高科技有限公司 | Time synchronization method of periodic second pulse output aligned with specified time |
| CN115857620A (en) * | 2023-02-28 | 2023-03-28 | 交通运输部北海航海保障中心天津航标处 | AIS time slot calculation method and equipment based on FPGA |
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| CN105634640A (en) * | 2015-12-31 | 2016-06-01 | 武汉凡谷电子技术股份有限公司 | Realization method and device of TDD synchronization switch |
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| JP2010008833A (en) * | 2008-06-30 | 2010-01-14 | Fujitsu Ltd | Beam exposure apparatus and drawing control circuit of beam exposure apparatus |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111506000A (en) * | 2020-05-25 | 2020-08-07 | 南京国电南自电网自动化有限公司 | Synchronous sampling device based on non-real-time bus |
| CN113900480A (en) * | 2021-12-10 | 2022-01-07 | 成都金诺信高科技有限公司 | Time synchronization method of periodic second pulse output aligned with specified time |
| CN113900480B (en) * | 2021-12-10 | 2022-03-04 | 成都金诺信高科技有限公司 | Time synchronization method of periodic second pulse output aligned with specified time |
| CN115857620A (en) * | 2023-02-28 | 2023-03-28 | 交通运输部北海航海保障中心天津航标处 | AIS time slot calculation method and equipment based on FPGA |
| CN115857620B (en) * | 2023-02-28 | 2023-05-05 | 交通运输部北海航海保障中心天津航标处 | AIS time slot calculation method and equipment based on FPGA |
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