CN106206782A - Semiconductor substrate - Google Patents

Abstract

The invention discloses a semiconductor substrate, which includes a semiconductor body, a first buffer layer, a first amorphous silicon layer, a second buffer layer, a second amorphous silicon layer and a first protective layer. The semiconductor body has a first surface and a second surface opposite to the first surface. The first buffer layer is disposed on the first surface of the semiconductor body. The first amorphous silicon layer is doped with a first type dopant and is disposed on the first buffer layer. The second buffer layer is disposed on the second surface of the semiconductor body. The second amorphous silicon layer is doped with a second type dopant and is disposed on the second buffer layer. The first protective layer is disposed on the first amorphous silicon layer.

Description

semiconductor substrate

technical field

The invention relates to a semiconductor substrate, in particular to a semiconductor substrate applied to solar cells.

Background technique

With the development of technology, the demand for energy is increasing day by day. However, the energy contained in the earth is limited, so all countries are competing to devote themselves to the development of alternative energy sources. Among them, solar power generation that meets environmental demands is the most active.

A solar cell is a photovoltaic element that converts sunlight energy into electricity. At present, the simplest solar cell structure can only be composed of a P-type semiconductor layer and an N-type semiconductor layer forming a PN junction with each other. When the solar cell is irradiated with sunlight, the valence band electrons in the semiconductor layer can be excited by the energy of sunlight to form excited electron-hole pairs, and the excited electrons will be affected by the built-in electric field and move towards the N-type semiconductor layer. Move, while the excited holes move towards the P-type semiconductor layer. Therefore, when the light-receiving P-type semiconductor layer and N-type semiconductor layer are respectively connected to external circuits to form a loop, current and voltage will be generated. And this reaction of converting light energy into electrical energy can be called the photovoltaic effect (PhotovoltaicEffect).

In solar cells, silicon is the most important raw material. Among them, silicon can generally be divided into three types: single crystal silicon (Single Crystalline Silicon), polycrystalline silicon (Polycrystalline Silicon) and amorphous silicon (Amorphous Silicon). In terms of conversion efficiency, monocrystalline silicon is the highest, followed by polycrystalline silicon, and amorphous silicon is the lowest. However, in terms of production cost, amorphous silicon has the lowest production cost. Therefore, at present, solar cells are mainly made of monocrystalline silicon and amorphous silicon.

In recent years, a Heterojunction With Intrinsic Thin-Layer (HIT for short) solar cell prepared by a low-temperature process has been developed. HIT solar cells reduce the defects on the heterojunction interface and improve its characteristics by interposing an essentially amorphous silicon layer between the single crystal silicon substrate and the amorphous silicon layer.

Generally speaking, there are two different doped layers in a HIT solar cell to form the emitter and the back electric field respectively. For example, when the crystalline silicon wafer is N-type, a P-type doped layer is usually formed on one side to form an emitter, and an N-type doped layer is formed on the other side to form a back electric field, and then these doped layers are formed. The impurity layer is covered with a transparent conductive oxide (Transparent Conductive Oxide, TCO for short) layer. However, most of the existing doped layers are amorphous silicon or microcrystalline silicon grown by chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), while the TCO layer is mostly grown by physical vapor deposition (Physical Vapor Deposition, referred to as PVD). Grown Indium Tin Oxide (ITO for short). Therefore, in the process of connecting the processes, the surface of the doped layer will inevitably be oxidized or affected by moisture due to exposure to the atmosphere, thereby affecting the subsequent conversion efficiency.

Contents of the invention

In view of this, the object of the present invention is to provide a semiconductor substrate, comprising a semiconductor body, a first buffer layer, a first amorphous silicon layer, a second buffer layer, a second amorphous silicon layer and a first protection layer. Wherein, the semiconductor body has a first surface and a second surface opposite to the first surface. The first buffer layer is disposed on the first surface of the semiconductor body. The first amorphous silicon layer is doped with first type dopant and is arranged on the first buffer layer. The second buffer layer is disposed on the second surface of the semiconductor body. The second amorphous silicon layer is doped with second-type dopant and disposed on the second buffer layer. The first protective layer is disposed on the first amorphous silicon layer.

In one embodiment of the semiconductor substrate of the present invention, the thickness of the first protective layer is not greater than 10 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the thickness of the first protection layer is not greater than 5 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the thickness of the first protection layer is between 2 to 3 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the first protective layer is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer.

In one embodiment of the semiconductor substrate of the present invention, the first protection layer is a hydrophobic protection layer.

In one embodiment of the semiconductor substrate of the present invention, it further includes a second protection layer disposed on the second amorphous silicon layer.

In one embodiment of the semiconductor substrate of the present invention, the thickness of the second protection layer is not greater than 10 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the thickness of the second protective layer is not greater than 5 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the thickness of the second protective layer is between 2 to 3 nanometers (nm).

In one embodiment of the semiconductor substrate of the present invention, the above-mentioned second protective layer is an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer.

In one embodiment of the semiconductor substrate of the present invention, when the first-type dopant is P-type, the second-type dopant is N-type, and when the first-type dopant is N-type, the second-type dopant The quality is P type.

In one concept of the semiconductor substrate of the present invention, the aforementioned second protection layer is a hydrophobic protection layer.

In summary, according to the semiconductor substrate implemented in the present invention, by forming a protective layer with an appropriate thickness on the amorphous silicon layer doped with dopants, the surface of the amorphous silicon layer is protected from being oxidized or damaged during the process connection process. Affected by water vapor, the conversion efficiency of the solar cell can be improved when the solar cell is subsequently fabricated.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

1 is a side sectional view of a first embodiment of a semiconductor substrate of the present invention;

2 is a process flow diagram of the first embodiment of the semiconductor substrate of the present invention;

3 is a side sectional view of a second embodiment of the semiconductor substrate of the present invention;

FIG. 4 is a process flow diagram of the second embodiment of the semiconductor substrate of the present invention.

detailed description

In the drawings of the present invention, for the convenience of display and description, the proportions and textures of the various structures may not match the proportions and textures of the actual structures, which are only used for reference and not intended to limit the present invention.

Fig. 1 is a side sectional view of a first embodiment of the present invention. Referring to FIG. 1 , a semiconductor substrate 100 is disclosed. In the first embodiment, the semiconductor substrate 100 includes a semiconductor body 110 , a first buffer layer 120 , a first amorphous silicon layer 140 , a second buffer layer 130 , a second amorphous silicon layer 150 and a first protection layer 160 .

The semiconductor body 110 has a first surface 111 and a second surface 112 opposite to the first surface 111 . Here, the first surface 111 and the second surface 112 of the semiconductor body 110 can be roughened to increase the amount of light incident on the semiconductor body 110 . The semiconductor body 110 in this embodiment is a single-crystal silicon wafer doped with N-type dopants, but the present invention is not limited thereto, and the semiconductor body 110 can also be a single-crystal silicon wafer doped with P-type dopants round.

The first buffer layer 120 and the first amorphous silicon layer 140 are sequentially stacked on the first surface 111 of the semiconductor body 110, and the second buffer layer 130 and the second amorphous silicon layer 150 are also sequentially stacked on the semiconductor body. 110 on the second surface 112 . In other words, after the first buffer layer 120 is formed on the first surface 111 of the semiconductor body 110, the first amorphous silicon layer 140 is formed on the first buffer layer 120, and the second buffer layer 130 is formed on the semiconductor body 110. The second amorphous silicon layer 150 is formed on the second buffer layer 130 after being on the second surface 112 . Wherein, the first amorphous silicon layer 140 is doped with a first type dopant, and the second amorphous silicon layer 150 is doped with a second type dopant.

In this embodiment, the first-type dopant can be a P-type dopant, and the second-type dopant can be an N-type dopant, but the present invention is not limited thereto, that is, the first-type dopant can be N-type dopant, and the second-type dopant is P-type dopant.

In addition, in this embodiment, the first buffer layer 120 is an intrinsic semiconductor layer, and the technical means of disposing the first buffer layer 120 between the semiconductor body 110 and the first amorphous silicon layer 140 can improve the performance of the heterojunction interface. characteristics, thereby obtaining better conversion efficiency. Similarly, the second buffer layer 130 can also be an intrinsic semiconductor layer, and the second buffer layer 130 is disposed between the semiconductor body 110 and the second amorphous silicon layer 150 to improve the characteristics of the heterojunction interface, thereby obtaining better conversion efficiency.

The first protective layer 160 may be an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer. Here, the first protective layer 160 can be disposed on the first amorphous silicon layer 140, but the present invention is not limited thereto, that is, the first protective layer 160 can also be disposed on the second amorphous silicon layer 150, here It all depends on the needs of the design.

FIG. 2 is a process flow chart of the first embodiment of the semiconductor substrate of the present invention. Please refer to FIG. 2 , the process of the first embodiment of the semiconductor substrate of the present invention may include the following steps.

Step S01 : forming a first buffer layer 120 on the first surface 111 of the semiconductor body 110 .

Generally speaking, before forming the first buffer layer 120 on the semiconductor body 110, some pre-processes can be performed first to increase the subsequent conversion efficiency. In this embodiment, the pre-program may include the following steps.

Firstly, in order to prevent the semiconductor body 110 from being polluted during wafer processing, such as handling and storage, which would affect device characteristics, the semiconductor body 110 can be cleaned first. Here, the RCA cleaning method widely used in the industry can be used for cleaning.

After cleaning, some processing procedures can be performed on the semiconductor body 110 . For example, the surface is roughened, and the semiconductor body 110 is directional etched, so that a pyramid-shaped anti-reflection structure appears on the surface of the semiconductor body 110 , so as to reduce the reflectance of incident light. Next, the semiconductor body 110 having the pyramid-shaped anti-reflection structure can be cleaned again by using the RCA cleaning method.

In addition, because in the process, the surface of the semiconductor body 110 is easily oxidized to form an oxide layer, therefore, the semiconductor body 110 with a pyramid-shaped anti-reflection structure can be immersed in a dilute hydrofluoric acid solution to remove the surface of the semiconductor body 110. surface oxide layer.

Therefore, in step S01 , the first buffer layer 120 may be formed on the first surface 111 of the semiconductor body 110 from which the surface oxide layer has been removed. In this embodiment, the first buffer layer 120 is an intrinsic amorphous silicon (Intrinsic amorphous silicon) layer, and the first buffer layer 120 may be deposited on the first layer of the semiconductor body 110 by chemical vapor deposition (Chemical Vapor Deposition, CVD for short). on the surface 111. In another embodiment, the first buffer layer 120 may be a lightly doped amorphous silicon layer with 1×10 ¹⁴ to 1×10 ¹⁶ atoms/cm ³ (atom/cm ³ ) microdoping.

Step S02 : forming a first amorphous silicon layer 140 on the first buffer layer 120 .

In step S02 , the first amorphous silicon layer 140 may be deposited on the first buffer layer 120 by chemical vapor deposition. In addition, the first amorphous silicon layer 140 may be doped with first type dopants. Here, the first-type dopant can be an N-type dopant, such as phosphorus, arsenic, etc., but the present invention is not limited thereto, that is, the first-type dopant can also be a P-type dopant, such as: boron, arsenic, etc. gallium etc.

Step S03 : forming a first protective layer 160 on the first amorphous silicon layer 140 .

In step S03 , the first protective layer 160 may be deposited on the first amorphous silicon layer 140 by chemical vapor deposition to protect the first amorphous silicon layer 140 . Here, the first passivation layer 160 may be an essentially amorphous silicon layer or an essentially microcrystalline silicon layer. In addition, the first protection layer 160 has hydrophobicity. Here, the first protective layer 160 has a higher hydrophobicity than the first amorphous silicon layer 140, so it can protect the first amorphous silicon layer 140 from being affected by water vapor due to exposure to the atmosphere. Or be oxidized to change the characteristics.

In this embodiment, the thickness D1 of the first protective layer 160 is less than or equal to 10 nanometers (nm). In other words, the thickness D1 of the first protection layer 160 is not greater than 10 nanometers (nm).

In another embodiment, the thickness D1 of the first protective layer 160 is less than or equal to 5 nanometers (nm). In other words, the thickness D1 of the first protection layer 160 is not greater than 5 nanometers (nm).

In yet another embodiment, the thickness D1 of the first protective layer 160 is between 2 and 3 nanometers (nm).

Step S04 : forming a second buffer layer 130 on the second surface 112 of the semiconductor body 110 .

In step S04 , the second buffer layer 130 may be deposited on the second surface 112 of the semiconductor body 110 by chemical vapor deposition. Here, the second buffer layer 130 may be an essentially amorphous silicon layer. In another embodiment, the second buffer layer 130 may be a lightly doped amorphous silicon layer with 1×10 ¹⁴ to 1×10 ¹⁶ atoms/cm ³ (atom/cm ³ ) microdoping.

Step S05 : forming a second amorphous silicon layer 150 on the second buffer layer 130 .

In step S05, the second amorphous silicon layer 150 may be deposited on the second buffer layer 130 by chemical vapor deposition. In addition, the second amorphous silicon layer 150 may be doped with a second type of dopant, which is opposite to the type of the first amorphous silicon layer 140 . Here, the second-type dopant can be a P-type dopant, such as: boron, gallium, etc., but the present invention is not limited thereto, that is, the second-type dopant can also be an N-type dopant, such as: phosphorus, gallium, etc. Arsenic etc. In other words, when the first type dopant doped in the first amorphous silicon layer 140 is N type, the second type dopant doped in the second amorphous silicon layer 150 is P type; When the first-type dopant doped in the crystalline silicon layer 140 is P-type, the second-type dopant doped in the second amorphous silicon layer 150 is N-type.

Therefore, according to the process steps of the first embodiment, a protective layer with an appropriate thickness is deposited on one of the amorphous silicon layers doped with dopants on the semiconductor substrate 100, so that the semiconductor substrate 100 is subsequently sputtered with a transparent conductive oxide ( Transparent Conductive Oxides (TCO for short) layer and screen-printed metal electrodes are used to prepare solar cells during the manufacturing process. The amorphous silicon layer of the semiconductor substrate 100 can be protected by the protective layer from being oxidized due to exposure to the atmosphere.

Fig. 3 is a side sectional view of a second embodiment of the present invention. Referring to FIG. 3 , a semiconductor substrate 100 is disclosed. In the second embodiment, the semiconductor substrate 100 includes a semiconductor body 110, a first buffer layer 120, a first amorphous silicon layer 140, a second buffer layer 130, a second amorphous silicon layer 150, a first protection layer 160 and a second Second protective layer 170 .

In this embodiment, the first buffer layer 120 is disposed on the first surface 111 of the semiconductor body 110 , and the first amorphous silicon layer 140 is disposed on the first buffer layer 120 . The second buffer layer 130 is disposed on the second surface 112 of the semiconductor body 110 , and the second amorphous silicon layer 150 is disposed on the second buffer layer 130 . In addition, the first protection layer 160 and the second protection layer 170 are disposed on the first amorphous silicon layer 140 and the second amorphous silicon layer 150 respectively. Therefore, in this embodiment, both sides of the semiconductor substrate 100 (ie, the first surface 111 and the second surface 112) are provided with protective layers (ie, the first protective layer 160 and the second protective layer 170) to protect it. A doped amorphous silicon layer (ie, the first amorphous silicon layer 140 and the second amorphous silicon layer 150 ).

Here, the second protection layer 170 may be an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer. Therefore, the properties of the second protection layer 170 may be substantially the same as those of the first protection layer 160 . In addition, in this embodiment, since the semiconductor body 110, the first buffer layer 120, the first amorphous silicon layer 140, the second buffer layer 130, the second amorphous silicon layer 150, and the first protective layer 160 are all substantially compatible with The first embodiment is the same, so it will not be described again.

FIG. 4 is a process flow diagram of the second embodiment of the semiconductor substrate of the present invention. Please refer to FIG. 4 , the process of the second embodiment of the semiconductor substrate of the present invention may include the following steps.

Step S11 : forming a first buffer layer 120 on the first surface 111 of the semiconductor body 110 .

Generally speaking, before performing step S11, some pre-procedures may also be performed first, so as to improve the subsequent conversion efficiency. These pre-procedures have been outlined in the first embodiment, so they will not be repeated here.

In step S11 , the first buffer layer 120 may be deposited on the first surface 111 of the semiconductor body 110 from which the surface oxide layer has been removed through a pre-process by chemical vapor deposition (Chemical Vapor Deposition, CVD for short). Here, the first buffer layer 120 may be an intrinsic amorphous silicon (AmorphousSilicon) layer. In another embodiment, the first buffer layer 120 may be a lightly doped amorphous silicon layer with 1×10 ¹⁴ to 1×10 ¹⁶ atoms/cm ³ (atom/cm ³ ) microdoping.

Step S12 : forming a first amorphous silicon layer 140 on the first buffer layer 120 .

In step S12, the first amorphous silicon layer 140 may be deposited on the first buffer layer 120 by chemical vapor deposition. In addition, the first amorphous silicon layer 140 may be doped with first type dopants. Here, the first-type dopant can be an N-type dopant, such as phosphorus, arsenic, etc., but the present invention is not limited thereto, that is, the first-type dopant can also be a P-type dopant, such as: boron, arsenic, etc. gallium etc.

Step S13 : forming a first protective layer 160 on the first amorphous silicon layer 140 .

In step S13 , the first protection layer 160 may be deposited on the first amorphous silicon layer 140 by chemical vapor deposition to protect the first amorphous silicon layer 140 . Here, the first passivation layer 160 may be an essentially amorphous silicon layer or an essentially microcrystalline silicon layer. In addition, the first protection layer 160 may have hydrophobicity. Here, the first protective layer 160 has a higher hydrophobicity than the first amorphous silicon layer 140, so it can protect the first amorphous silicon layer 140 from being affected by water vapor due to exposure to the atmosphere. or be oxidized.

In an embodiment, the thickness D1 of the first protective layer 160 is less than or equal to 10 nanometers (nm). In other words, the thickness D1 of the first protection layer 160 is not greater than 10 nanometers (nm).

In another embodiment, the thickness D1 of the first protection layer 160 is less than or equal to 5 nanometers (nm). In other words, the thickness D1 of the first protection layer 160 is not greater than 5 nanometers (nm).

In yet another embodiment, the thickness D1 of the first protection layer 160 is between 2 to 3 nanometers (nm).

Step S14 : forming a second buffer layer 130 on the second surface 112 of the semiconductor body 110 .

In step S14 , the second buffer layer 130 may be deposited on the second surface 112 of the semiconductor body 110 by chemical vapor deposition. Here, the second buffer layer 130 may be an essentially amorphous silicon layer. In another embodiment, the second buffer layer 130 may be a lightly doped amorphous silicon layer with 1×10 ¹⁴ to 1×10 ¹⁶ atoms/cm ³ (atom/cm ³ ) microdoping.

Step S15 : forming a second amorphous silicon layer 150 on the second buffer layer 130 .

In step S15, the second amorphous silicon layer 150 may be deposited on the second buffer layer 130 by chemical vapor deposition. In addition, the second amorphous silicon layer 150 may be doped with a second type of dopant, which is opposite to the type of the first amorphous silicon layer 140 . Here, the second-type dopant can be a P-type dopant, such as: boron, gallium, etc., but the present invention is not limited thereto, that is, the second-type dopant can also be an N-type dopant, such as: phosphorus, gallium, etc. Arsenic etc. In other words, when the first type dopant doped in the first amorphous silicon layer 140 is N type, the second type dopant doped in the second amorphous silicon layer 150 is P type; When the first-type dopant doped in the crystalline silicon layer 140 is P-type, the second-type dopant doped in the second amorphous silicon layer 150 is N-type.

Step S16 : forming a second protective layer 170 on the second amorphous silicon layer 150 .

In step S16 , the second protective layer 170 may be deposited on the second amorphous silicon layer 150 by chemical vapor deposition to protect the second amorphous silicon layer 150 . Here, the second protection layer 170 may be an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer. In addition, the second protective layer 170 has hydrophobicity. Here, the second protective layer 170 has a higher hydrophobicity than the second amorphous silicon layer 150, so it can protect the second amorphous silicon layer 150 from being affected by water vapor due to exposure to the atmosphere. or be oxidized.

In an embodiment, the thickness D2 of the second protective layer 170 is less than or equal to 10 nanometers (nm). In other words, the thickness D2 of the second protective layer 170 is not greater than 10 nanometers (nm).

In another embodiment, the thickness D2 of the second protective layer 170 is less than or equal to 5 nanometers (nm). In other words, the thickness D2 of the second protection layer 170 is not greater than 5 nanometers (nm).

In yet another embodiment, the thickness D2 of the second protective layer 170 is between 2 and 3 nanometers (nm).

Therefore, by performing step S11 to step S16 in sequence, protective layers with appropriate thicknesses are respectively formed on the amorphous silicon layer on both sides of the semiconductor substrate 100, compared with only one side of the semiconductor substrate 100 in the first embodiment. In terms of forming a protective layer with an appropriate thickness, the second embodiment can obtain a more perfect protective effect.

However, in this embodiment, the order of steps S11 to S16 is not absolute, that is, after step S12 is performed (that is, the first amorphous silicon layer 140 is formed on the first buffer layer 120), the After steps S14 and S15 are executed in sequence, step S13 and step S16 are executed synchronously. In other words, the first protection layer 160 and the second protection layer 170 can be sequentially formed on the first surface 111 of the semiconductor body 110 on the first buffer layer 120 and the first amorphous silicon layer 140, and the second buffer layer 130, the second After the two amorphous silicon layers 150 are sequentially formed on the second surface 112 of the semiconductor body 110 , they are respectively formed on the first amorphous silicon layer 140 and the second amorphous silicon layer 150 simultaneously.

In summary, according to the semiconductor substrate implemented in the present invention, by forming a protective layer with an appropriate thickness on the amorphous silicon layer doped with dopants, the surface of the amorphous silicon layer is protected in the subsequent process of preparing a solar cell. The process is not oxidized or affected by moisture due to exposure to the atmosphere, so the retention time (Q-Time) can be extended, and the conversion efficiency of the solar cell caused by the excessive retention time of the existing solar cell is solved. The problem of falling, which in turn allows solar cells to have greater flexibility in the production process and time.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (13)

1. A semiconductor substrate, characterized in that, comprising: a semiconductor body having a first surface and a second surface opposite to the first surface; a first buffer layer disposed on the first surface; a first amorphous silicon layer, disposed on the first buffer layer, doped with a first type dopant; a second buffer layer disposed on the second surface; a second amorphous silicon layer, disposed on the second buffer layer, doped with a second type dopant; and A first protection layer is arranged on the first amorphous silicon layer. 2. The semiconductor substrate according to claim 1, wherein the thickness of the first protection layer is not greater than 10 nanometers. 3. The semiconductor substrate according to claim 1, wherein the thickness of the first protection layer is not greater than 5 nanometers. 4. The semiconductor substrate according to claim 1, wherein the thickness of the first protection layer is between 2 and 3 nanometers. 5. The semiconductor substrate according to claim 1, wherein the first protection layer is an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer. 6. The semiconductor substrate according to claim 1 or 5, wherein the first protection layer is a hydrophobic protection layer. 7. The semiconductor substrate according to claim 1, further comprising: A second protective layer is disposed on the second amorphous silicon layer. 8. The semiconductor substrate according to claim 7, wherein the thickness of the second protection layer is not greater than 10 nanometers. 9. The semiconductor substrate according to claim 7, wherein the thickness of the second protection layer is not greater than 5 nanometers. 10 . The semiconductor substrate according to claim 7 , wherein the thickness of the second protective layer is between 2 and 3 nanometers. 11 . 11. The semiconductor substrate according to claim 7, wherein the second protection layer is an intrinsically amorphous silicon layer or an intrinsically microcrystalline silicon layer. 12. The semiconductor substrate according to any one of claims 1 to 11, wherein when the first-type dopant is P-type, the second-type dopant is N-type, and when the first-type dopant is When the dopant is N type, the second type dopant is P type. 13. The semiconductor substrate according to claim 7 or 11, wherein the second protection layer is a hydrophobic protection layer.