CN106206527B - Semiconductor subassembly and its manufacturing method - Google Patents
Semiconductor subassembly and its manufacturing method Download PDFInfo
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- CN106206527B CN106206527B CN201610041083.8A CN201610041083A CN106206527B CN 106206527 B CN106206527 B CN 106206527B CN 201610041083 A CN201610041083 A CN 201610041083A CN 106206527 B CN106206527 B CN 106206527B
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- warpage
- cover
- wafer
- interposer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The invention discloses semiconductor components, include an interposer substrate, have a front and a back side；One redistribution layer is located at the front, and the redistribution layer includes multiple engagement pads；Multiple convex blocks are located in the engagement pad；At least semiconductor chip is installed on the front, and is electrically connected by the convex block and the redistribution layer；One warpage inhibits cover to be installed on the front, covers and seals the semiconductor chip；And multiple straight-through silicon perforations, it is electrically connected through the interposer substrate and with the redistribution layer.
Description
Technical field
The present invention relates to field of semiconductor package, are fanned out to (fan-out) wafer-level packaging (wafer more particularly to one kind
Level packaging) and manufacture interposer substrate (interposer substrate) method.
Background technique
Wafer-level packaging technique is technology known to the field technical staff.In wafer-level packaging technique, include
Integrated circuit formed wherein or the wafer that is installed on it of chip can by process sequence, such as polishing, crystal grain alignment engagement, with
And envelope mold forming and etc., finally final products are obtained using cutting.Industry generally believes that wafer-level packaging technique is now
It is most suitable for applying the technology in small size and high-speed chip encapsulation.
In general, will use a relatively thick moulding compound (molding compound) when carrying out wafer-level packaging and cover
Wafer and the crystal grain being mounted on wafer.Due to the difference of thermal expansion coefficient (CTE) and wafer of moulding compound, by certain thickness
Warpage is easy when the packaging body that moulding compound is constituted is by thermal change.Moreover, the presence of moulding compound also makes the whole of packaging body
Body thickness increases.The problem of silicon wafer warpage, the always described field technical staff attempted to solve the problems, such as.
Silicon wafer warpage causes to be not easy to maintain the connection between crystal grain and wafer, causes crystal grain and wafer lamination to assemble and fails.It sticks up
Qu Wenti is even more obviously, to keep the wafer-level packaging of big ruler inch wafer more difficult on large scale wafer.Therefore, industry there is still a need for
The wafer-level packaging method of one improvement, the problem of can solve above-mentioned prior art.
Summary of the invention
The main purpose of the present invention is to provide the semiconductor subassemblies of an improvement, and wafer or packaging body can be mitigated or eliminated
The problem of warpage, makes semiconductor package body obtained have better reliability.
The semiconductor subassembly provided according to the present invention includes an interposer substrate, has a front and a back side；One heavy cloth
Layer is located at the front, and the redistribution layer includes multiple engagement pads；Multiple convex blocks are located in the engagement pad；At least
Semiconductor chip is installed on the front, and is electrically connected by the convex block and the redistribution layer；One warpage inhibits cover peace
Loaded on the front, the semiconductor chip is covered and sealed；And multiple straight-through silicon perforations, through the interposer substrate and
It is electrically connected with the redistribution layer.
An embodiment according to the present invention, the warpage inhibit cover to be not directly contacted with the semiconductor chip.According to this hair
A bright embodiment, the warpage inhibit to cover the front for being fixed on interposer substrate securely.It is described according to one embodiment of the invention
Warpage inhibits cover that can be made of glass, siliceous, metal, ceramics or any combination thereof.
It is unquestionable, the skilled worker in the field run through the detailed description of the following preferred embodiment of the present invention with it is attached
After figure, the purpose of the present invention can be appreciated that.
Detailed description of the invention
Attached drawing provide for this embodiment deeper into understanding, and be included in this specification as a portion.These are attached
Figure and description, for illustrating the principle of some embodiments.
Fig. 1 to Figure 12 is schematic cross sectional view, illustrates an embodiment according to the present invention, manufactures the side of a wafer-level packaging body
Method.
Figure 13 is that the warpage that one embodiment of the invention provides inhibits cover schematic cross sectional view, is bonded mutually by two wafers
It constitutes.
Figure 14 is that the warpage that one embodiment of the invention provides inhibits cover perspective view, is painted the bottom surface that wafer scale warpage inhibits cover
Part and its compartment.
Wherein, the reference numerals are as follows:
10 semiconductor subassemblies
100 wafers
The front 100a
The back side 100b
101 interposer substrates
102 straight-through silicon perforations
110 redistribution layers
112 dielectric layers
114 metal layers
116 dimpling blocks
120 chips or crystal grain
130 gaps
140 brilliant back weight wire winding layers
141 dielectric layers
142 bump pads
150 controllable avalanche Chip Connection bumps
200 warpages inhibit cover
202 first wafers
204 second wafers
220 compartments
300 package substrates
Specific embodiment
Next detailed narration must be referring to content shown in relevant drawings, for illustrate specifically to carry out according to the present invention
Embodiment.
These embodiments provide enough details, and those skilled in the art can be made to fully understand and specifically carry out this hair
It is bright.It is not departing from the scope of the present invention, the modification that can be made in structure, logic and electrical property is applied in other embodiments.
Therefore, next detailed description is not intended to limit the present invention.The range that the present invention covers is by its power
Benefit requires to define.Have equivalence with the claims in the present invention, should also belong to the range that the present invention covers.
The attached drawing of institute of embodiment of the present invention reference is schematic diagram, is not necessarily to scale, and same or similar feature is logical
Often with the description of identical appended drawing reference.
In the present specification, " crystal grain ", " semiconductor chip " and " semiconductor grain " has synonymous, is used interchangeably.
In the present specification, " wafer " and " substrate " mean that any includes an exposure, deposition materials and can make on it
Make any works of redistribution layer (RDL) circuit structure of such as embodiment of the present invention.
It will be appreciated that " substrate " includes semiconductor crystal wafer, but not limited to this.In technique, " substrate " is also used to indicate to wrap
The semiconductor structure object of material layer containing manufacture on it.
Please refer to Fig. 1 to Figure 12.Fig. 1 to Figure 12 is schematic cross sectional view, illustrates an embodiment according to the present invention, manufacture one
The method of wafer-level packaging body.
As shown in Figure 1, providing a wafer 100 first.Wafer 100 includes Silicon Wafer, semiconductor crystal wafer or intermediary layer wafer,
But not limited to this.For example, wafer 100 can be a silicon intermediary layer wafer.
Wafer 100 has an original thickness t, can be between 600 to 800 microns, such as 770 microns.Wafer 100 has
An one front 100a and back side 100b.
As shown in Fig. 2, multiple straight-through silicon perforations (TSV) 102 can be formed in the positive 100a of wafer 100.Manufacture is straight-through
The method of silicon perforation 102 is that the technical personnel in the technical field are familiar with.
For example, the method for manufacturing straight-through silicon perforation 102 includes brilliant in the positive 100a manufacture distance of wafer 100 first
The TSV hole of circle 100 main surface, one predetermined depth, then the deposited metal layer in TSV hole, such as diffusion barrier metals layer with
Layers of copper, but not limited to this.Then a polishing process is carried out to the positive 100a of wafer 100, removes metal extra outside TSV hole
Layer.
Then as shown in figure 3, forming a redistribution layer (RDL) 110 on the positive 100a of wafer 100.Redistribution layer 110 can be with
Include at least a dielectric layer 112 and an at least metal layer 114.Straight-through silicon perforation 102 can be electrically connected with metal layer 114.
As shown in figure 4, then forming multiple dimpling blocks 116 in redistribution layer 110, used for subsequent connection.Dimpling block 116 can
It is formed directly into the engagement pad of metal layer 114 respectively.
As shown in figure 5, after forming dimpling block 116, it is then that individual crystal covered chips or crystal grain are actively face-down, by dimpling
Block 116 is installed in redistribution layer 110, obtains the construction that a chip overlaps wafer.
Next, optionally filling a primer between the positive 100a of each chip or crystal grain 120 and wafer 100
118.Then, a heat treatment is carried out, 116 reflow of dimpling block is made.
As shown in fig. 6, generally then there is identical size and shape with wafer 100 by one after completing crystal grain engagement
Warpage inhibits cover 200, is covered on wafer 100 in a manner of wafer.
According to embodiments of the present invention, warpage inhibits cover 200 can be by glass, siliceous, metal, ceramics or any combination thereof structure
At.When it is to consist of metal that warpage, which inhibits cover 200, while having the function of shielding electromagnetic interference (EMI).
According to embodiments of the present invention, warpage inhibits cover 200 that can firmly fix by adhesive agent or the mode of melting engagement
On the positive 100a of wafer 100, but not limited to this.
According to embodiments of the present invention, warpage inhibits cover 200 identical as thermal expansion coefficient (CTE) of wafer 100, therefore can be with
Avoiding wafer 100, there is a situation where warpages.
Warpage inhibits the construction of cover 200 as shown in figure 13, is bonded mutually by two wafers, and single-wafer cover is formed.
First wafer 202 has thickness t1, such as 300 microns.Second wafer 204 has thickness t2, such as 400 microns.Therefore,
Warpage inhibition cover 200 is summed up with a thickness of the two, and about 700 microns.
Second wafer 204 has multiple pass through openings, therefore the first wafer 202 is bonded with the second wafer 204
Afterwards, the wafer cover with multiple compartments 220 can be obtained.As shown in figure 14, warpage inhibit cover 200 compartment 220 position with
The alignment of chip or crystal grain 120 or alignment being mounted on wafer 100.Each compartment 220 can at least accommodate one or two installation
Chip or crystal grain 120.
According to embodiments of the present invention, warpage inhibits have a gap 130 between cover 200 and the chip or crystal grain 120 of installation.Root
According to the embodiment of the present invention, gap 130 can be a gap vacuumized.
However it will be appreciated that in other embodiments, warpage inhibits cover 200 straight with the chip or crystal grain 120 of installation
Contact.According to embodiments of the present invention, in the treatment process of wafer 100, and moulding compound is not used.
The advantage of the invention is that provided wafer-level packaging method eliminate the step of forming moulding compound with it is subsequent
Curing schedule has relatively simplified technique.Moreover, not only restraining silicon wafer warpage, outgassing caused by moulding compound also can avoid
(outgassing) problem.
As shown in fig. 7, then carrying out a brilliant back after warpage inhibits cover 200 to be installed to the back side 100b of wafer 100 and throwing
Light technology keeps the thickness of wafer 100 thinning.The part wafer 100 of back side 100b is removed in this step.
As shown in figure 8, making straight-through 102 one end of silicon perforation from wafer followed by chemically mechanical polishing (CMP) technique
100 back side 100b is revealed.According to embodiments of the present invention, the back side 100b of wafer 100 includes a dielectric layer 141.Technique
To the current stage, the remaining thickness of wafer 100 is between 90~110 microns, such as 100 microns.
As shown in figure 9, then forming one in the back side 100b of wafer 100 after the bottom of straight-through silicon perforation 102 reveals
Crystalline substance back weight wire winding layer 140.Crystalline substance back weight wire winding layer 140 and straight-through silicon perforation 102 are electrically connected.According to embodiments of the present invention, brilliant back
Weight wire winding layer 140 may include bump pads 142.
As shown in Figure 10, according to embodiments of the present invention, multiple controllable avalanche chip connection (C4) convex blocks 150 are respectively in convex block
It is formed on pad 142.According to embodiments of the present invention, for preferably, about 10~100 microns of the diameter of C4 convex block 150, spacing
(pitch) about 200 microns.For best, spacing is 50~150 microns.
As shown in figure 11, it is then cut along the Cutting Road region of wafer 100, obtains an other semiconductor subassembly 10.Wafer
100 after dicing, becomes an other interposer substrate 101.According to embodiments of the present invention, each semiconductor subassembly 10 may include
At least semiconductor chip or the crystal grain upper surface that is mounted on interposer substrate 101.
As shown in figure 12, according to embodiments of the present invention, then semiconductor subassembly 10 is installed on a package substrate 300,
Then subsequent to be sealed up semiconductor subassembly 10 with moulding compound (not shown).Since chip or crystal grain 120 are inhibited by warpage
Cover 200 covers, therefore can't directly contact with moulding compound.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of semiconductor subassembly, characterized by comprising:
One interposer substrate has a front and a back side；
One redistribution layer, positioned at the front of the interposer substrate, wherein the redistribution layer includes multiple engagement pads；
Multiple convex blocks are located in multiple engagement pads of the redistribution layer；
At least semiconductor chip is installed on the front of the interposer substrate, and by the convex block and redistribution layer electricity
Property connection；
One warpage inhibits cover, is installed on the front of the interposer substrate, covers and surround the semiconductor chip；And
Multiple straight-through silicon perforations are electrically connected through the interposer substrate and with the redistribution layer,
Wherein the warpage inhibits cover identical as the thermal expansion coefficient of the interposer substrate,
Wherein the warpage inhibits cover includes two silicon wafer circular portions mutually to fit, and the first silicon wafer circular portion has wherein
At least one opening, the second silicon wafer circular portion extend over said opening, the first silicon wafer circular portion and second silicon wafer
Circular portion, which combines, forms at least one compartment, and at least semiconductor chip is located at least one described compartment.
2. semiconductor subassembly according to claim 1, which is characterized in that additionally comprise multiple bump pads, be located at the intermediary
The back side of laminar substrate.
3. semiconductor subassembly according to claim 2, which is characterized in that it is convex to additionally comprise multiple controllable avalanche chip connections
Block is located in the multiple bump pads.
4. semiconductor subassembly according to claim 1, which is characterized in that the warpage inhibits cover and the semiconductor chip
It is not directly contacted with.
5. semiconductor subassembly according to claim 4, which is characterized in that it is described that the warpage inhibits cover to be firmly fixed at
The front of interposer substrate.
6. semiconductor subassembly according to claim 4, which is characterized in that additionally comprise a gap, be located at the warpage and inhibit
Between cover and the semiconductor chip.
7. semiconductor subassembly according to claim 6, which is characterized in that the gap is a gap vacuumized.
8. semiconductor subassembly according to claim 1, which is characterized in that the warpage inhibit cover with a thickness of 700 microns.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201514720841A | 2015-05-25 | 2015-05-25 | |
| US14/720,841 | 2015-05-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206527A CN106206527A (en) | 2016-12-07 |
| CN106206527B true CN106206527B (en) | 2019-08-13 |
Family
ID=57453168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610041083.8A Active CN106206527B (en) | 2015-05-25 | 2016-01-21 | Semiconductor subassembly and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106206527B (en) |
| TW (1) | TWI600133B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9570369B1 (en) * | 2016-03-14 | 2017-02-14 | Inotera Memories, Inc. | Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof |
| US10535597B2 (en) * | 2017-01-13 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
| US10396003B2 (en) * | 2017-10-18 | 2019-08-27 | Micron Technology, Inc. | Stress tuned stiffeners for micro electronics package warpage control |
| US11139341B2 (en) * | 2018-06-18 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection of MRAM from external magnetic field using magnetic-field-shielding structure |
| CN111698824B (en) * | 2020-05-22 | 2022-03-08 | 中国电子科技集团公司第二十九研究所 | Integrated interconnection structure of self-airtight packaging functional module and implementation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1572718A (en) * | 2003-06-06 | 2005-02-02 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN101322245A (en) * | 2006-09-15 | 2008-12-10 | 香港应用科技研究院有限公司 | Electronic component packaging with EMI shielding |
| CN103617991A (en) * | 2013-11-20 | 2014-03-05 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor encapsulation electromagnetic shielding structure and manufacturing method |
| CN103730448A (en) * | 2012-10-11 | 2014-04-16 | 财团法人工业技术研究院 | Package substrate and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10345377B4 (en) * | 2003-09-30 | 2009-07-30 | Qimonda Ag | Semiconductor module and method for producing a semiconductor module |
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2016
- 2016-01-04 TW TW105100026A patent/TWI600133B/en active
- 2016-01-21 CN CN201610041083.8A patent/CN106206527B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1572718A (en) * | 2003-06-06 | 2005-02-02 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN101322245A (en) * | 2006-09-15 | 2008-12-10 | 香港应用科技研究院有限公司 | Electronic component packaging with EMI shielding |
| CN103730448A (en) * | 2012-10-11 | 2014-04-16 | 财团法人工业技术研究院 | Package substrate and manufacturing method thereof |
| CN103617991A (en) * | 2013-11-20 | 2014-03-05 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor encapsulation electromagnetic shielding structure and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206527A (en) | 2016-12-07 |
| TWI600133B (en) | 2017-09-21 |
| TW201642429A (en) | 2016-12-01 |
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Effective date of registration: 20170303 Address after: Idaho Applicant after: Micron Technology, Inc. Address before: Chinese Taiwan Taoyuan City Applicant before: Inotera Memories, Inc. |
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