CN106206484A - Chip packaging method and encapsulating structure - Google Patents
Chip packaging method and encapsulating structure Download PDFInfo
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- CN106206484A CN106206484A CN201610707387.3A CN201610707387A CN106206484A CN 106206484 A CN106206484 A CN 106206484A CN 201610707387 A CN201610707387 A CN 201610707387A CN 106206484 A CN106206484 A CN 106206484A
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- groove
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- line layer
- insulating barrier
- pad liner
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 65
- 239000003292 glue Substances 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 14
- 238000007711 solidification Methods 0.000 claims description 6
- 230000008023 solidification Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- 238000003032 molecular docking Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000011946 reduction process Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides chip packaging method and encapsulating structure.The method includes: providing wafer, this wafer has first surface and second surface, and wafer first surface is integrated with multiple chip unit；The first groove is formed between the pad liner of adjacent chips unit；Forming the first insulating barrier, the first insulating barrier has multiple hatch frame exposed pad liner；Making first line layer, first line layer electrically connects with pad liner；In the first groove, fill the first glue and solidify；The second groove is formed at wafer second surface；In the second groove and described wafer second surface makes the second insulating barrier；The 3rd groove, exposed portion first line layer is formed in the second groove；Sequentially forming the second line layer and solder mask, the second line layer electrically connects with first line layer.The chip packaging method of present invention offer and encapsulating structure, solve easy fracture at wafer pad liner, the problem that package strength reliability is the highest.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to chip packaging method and encapsulating structure.
Background technology
At present, crystal wafer chip dimension encapsulation is the one in integrated antenna package mode, and it is that one is first brilliant by full wafer
Sheet is packaged, then cutting obtains the method for packing of simple grain chip.
Currently mainly packaged type is that the deep reactive ion etching of wafer rear forms groove and pore structure, then by laser drill and weight
Wiring technique, causes wafer pad signal chip back and completes encapsulation.Such packaged type there is the problem that wafer welds
At dish, silicon ratio is relatively thin, easy fracture, and package strength reliability is the highest.
Summary of the invention
In order to solve above-mentioned technical problem, the present invention proposes chip packaging method and encapsulating structure, to realize improving chip
The purpose of package strength.
First aspect, the embodiment of the present invention provides chip packaging method, including:
Step 110, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
Stating wafer first surface and be integrated with multiple chip unit, each described chip unit is provided with some pads at described first surface
Liner；
Step 120, between the pad liner of adjacent described chip unit, form the first groove；
Step 130, in described first groove and described wafer first surface forms the first insulating barrier, described first exhausted
Edge layer has multiple hatch frame, and described hatch frame exposes described pad liner；
Step 140, make first line layer, described first line layer and described pad on the surface of described first insulating barrier
Liner electrically connects；
Step 150, in described first groove, fill the first glue and solidify；
Step 160, forming the second groove at described wafer second surface, described second groove is positioned at described first groove
Lower section, and described second bottom portion of groove exposes described first insulating barrier；
Step 170, in described second groove and described wafer second surface makes the second insulating barrier；
Step 180, in described second groove, form the 3rd groove, first line layer described in exposed portion；
Step 190, in described second surface of insulating layer and described 3rd groove, sequentially form the second line layer and resistance
Layer, described second line layer electrically connects with described first line layer；
Step 200, along described second groove cut the plurality of chip unit form multiple individual chips.
Alternatively, after described step 150, and before described step 160, also include step 151:
Described first surface at described wafer is bonded and supports substrate, and subtracts the described second surface of described wafer
Thin process；
After described step 190, and also included before described step 200: remove described support substrate.
Alternatively, after described step 190, and before described step 200, also include step 201:
In described second groove and described 3rd groove, fill the second glue and solidify.
Alternatively, described step 180 includes:
Forming the 3rd groove in described second groove by mechanical cutting processes, described 3rd bottom portion of groove is positioned at described
In first groove, first line layer described in the sidewall exposed portion of described 3rd groove.
Alternatively, described step 180 includes:
Etch described first insulating barrier of described second bottom portion of groove and described second insulating barrier, form the 3rd groove；
First line layer described in described 3rd bottom portion of groove exposed portion.
Alternatively, setting is docked with the bottom of described first groove in the bottom of described second groove；Or, described first groove
Bottom be positioned at described second groove.
Second aspect, the embodiment of the present invention provides chip-packaging structure, including:
Wafer, described wafer has first surface and the second surface relative with described first surface, described wafer
One surface is integrated with multiple chip unit；It is formed with the first groove between the pad liner of adjacent described chip unit；Described
In one groove and described wafer first surface is formed with the first insulating barrier, described first insulating barrier has multiple hatch frame,
Described hatch frame exposes described pad liner；The surface of described first insulating barrier is formed with first line layer, described First Line
Road floor electrically connects with described pad liner；The first glue of solidification it is filled with in described first groove；Described wafer second surface
Being formed with the second groove, described second groove is positioned at the lower section of described first groove, and described second bottom portion of groove exposes described
First insulating barrier；In described second groove and described wafer second surface is formed with the second insulating barrier；In described second groove
It is formed with the 3rd groove, first line layer described in described 3rd groove exposed portion；Described second surface of insulating layer and described
Being sequentially formed with the second line layer and solder mask in 3rd groove, described second line layer electrically connects with described first line layer.
Alternatively, setting is docked with the bottom of described first groove in the bottom of described second groove；Or, described first groove
Bottom be positioned at described second groove.
Alternatively, described 3rd bottom portion of groove is positioned at described first groove, the sidewall exposed portion of described 3rd groove
Described first line layer；Or, first line layer described in described 3rd bottom portion of groove exposed portion.
Alternatively, the second glue of solidification it is filled with in described second groove and described 3rd groove.
The chip packaging method of embodiment of the present invention offer and encapsulating structure, by described in described wafer first surface
Fill described filling the first glue in first groove, so open described second groove and described 3rd groove at described second surface
And when making described second line layer, described wafer is provided strength support, solve described at wafer pad liner brilliant
Circle ratio is relatively thin, easy fracture, the problem that package strength reliability is the highest.
Accompanying drawing explanation
The schematic flow sheet of the chip packaging method that Fig. 1 provides for the embodiment of the present invention one；
Fig. 2 a-2o is profile corresponding to each step of chip packaging method that the embodiment of the present invention one provides；
The chip-packaging structure generalized section that Fig. 2 p-2r provides for the embodiment of the present invention two.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention is illustrate only rather than entire infrastructure in description, accompanying drawing.
Embodiment one
The schematic flow sheet of the chip packaging method that Fig. 1 provides for the embodiment of the present invention one, Fig. 2 a-2o is that the present invention implements
Profile corresponding to each step of chip packaging method that example one provides.See Fig. 1, said method comprising the steps of:
Step 110, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
Stating wafer first surface and be integrated with multiple chip unit, each described chip unit is provided with some pads at described first surface
Liner.
Referring to Fig. 2 a, wafer 10 has first surface 100 and the second surface 200 relative with first surface 100, brilliant
Circle 10 first surfaces 100 are integrated with multiple chip unit (not shown).Chip unit is e.g. noted by repeatedly photoetching, ion
Enter, etch and the technique such as evaporation forms the circuit knot of the multilayer electronic component composition with specific function at wafer first surface
Structure.Each chip unit is provided with some pad liners 101 at first surface 100.Pad liner 101 is equivalent to each chip list
The extraction electrode of unit, pad liner 101 is connected with the circuit structure in chip unit.Wafer 10 can be silicon, germanium or other half
Conductor backing material.
Step 120, between the pad liner of adjacent described chip unit, form the first groove.
See Fig. 2 b, between the pad liner 101 of adjacent chips unit, form the first groove 102.First groove 102 example
As formed by photoetching and deep reaction ion etching technique.
Step 130, in described first groove and described wafer first surface forms the first insulating barrier, described first exhausted
Edge layer has multiple hatch frame, and described hatch frame exposes described pad liner.
Seeing Fig. 2 c, in the first groove 102 and wafer 10 first surface 100 forms the first insulating barrier 103, first is exhausted
Edge layer 103 has multiple hatch frame 104, and hatch frame 104 exposed pad liner 101.First insulating barrier 103 can be logical
Cross thermally grown or depositing technics to be formed at wafer 10 first surface 100.
Alternatively, the first insulating barrier 103 can be SiO2.When the first insulating barrier 103 is SiO2Time, SiO2Can be raw by heat
Long or deposit mode generates.Thermally grown technique i.e. is allowed to react with wafer (such as silicon chip) by being externally supplied high purity oxygen gas,
Forming layer of oxide layer at silicon chip surface, this oxide layer is the first insulating barrier 103.Deposit is i.e. by being externally supplied oxygen and silicon
Source, makes them react in cavity, thus forms layer of oxide layer thin film, the i.e. first insulating barrier 103 at silicon chip surface.First opens
Mouth structure 104 such as can reserve opening knot by patterned mask plate when crystal column surface forms the first insulating barrier 103
Structure 104；The making of hatch frame 104 such as can also be completed by etching technics after forming the first insulating barrier 103.
Step 140, make first line layer, described first line layer and described pad on the surface of described first insulating barrier
Liner electrically connects.
Seeing Fig. 2 d, make first line layer 105 on the surface of the first insulating barrier 103, first line layer 105 passes through opening
Structure 104 electrically connects with pad liner 101.
Alternatively, the first line layer 105 on the surface of the first insulating barrier 103 can include one or more layers metal.The
The preparation technology of one line layer 105 can be such as magnetron sputtering technique.First line layer 105 is by the telecommunications of pad liner 101
Number lead to the first surface 100 of wafer 10.It should be noted that multiple layer metal forms first line layer 105 relatively layer of metal
Form first line layer 105 can preferably electrically connect with being formed between pad liner 101.Exemplarily, at the first insulating barrier
103 surface splash-proofing sputtering metal titaniums, then sputter layer of metal copper by magnetron sputtering at metallic titanium surface, thus complete metal wiring layer
Making.
Step 150, in described first groove, fill the first glue and solidify.
See Fig. 2 e, in the first groove 102, fill the first glue 106 and solidify.
First glue can be such as the macromolecular materials such as epoxy resin, after overcuring, can increase wafer 10
Mechanical strength.
Alternatively, after described step 150, and before described step 160, also include step 151: at described crystalline substance
The described first surface bonding of circle supports substrate, and the described second surface of described wafer is carried out reduction processing.
Seeing Fig. 2 f, the first surface 100 at wafer 10 is bonded and supports substrate 20, and the second surface 200 to wafer 10
Carry out reduction processing (dotted portion is the thinning wafer material removed).Bonding substrate 20 is to increase during reduction process
Add mechanical strength.Before wafer is thinned to suitable thickness, it is necessary to support substrate at wafer frontside ephemeral key unification block, in order to
Enough mechanical strengths are provided during the most thinning.Reduction process can be such as chemical mechanical milling tech.Relatively thin
Wafer substrate material can reduce dry etching, the difficulty of the technique such as machine cuts and rewiring, meanwhile, thinner wafer
Thickness can improve chip cooling, and makes product become thinner.
Step 160, forming the second groove at described wafer second surface, described second groove is positioned at described first groove
Lower section, and described second bottom portion of groove exposes described first insulating barrier.
Seeing Fig. 2 g, form the second groove 107 at wafer 10 second surface 200, the second groove 107 is positioned at the first groove
The first insulating barrier 103 is exposed bottom the lower section of 102, and the second groove 107.Second groove 107 such as can be by photoetching with deep
Reactive ion etching process is formed.
Alternatively, setting is docked with the bottom of the first groove 102 in the bottom of the second groove 107；Or, the first groove 102
Bottom is positioned at the second groove 107.
It should be noted that the bottom of the exemplary bottom that the second groove 107 is set of the present embodiment and the first groove 102
Docking is arranged, and not restriction to the embodiment of the present invention, in other embodiments, can distinguish according to actual application scenarios
First groove 102 and shape, size and the position of the second groove 107 is set, as long as it is recessed to ensure that the second groove 107 is positioned at first
Described first insulating barrier is exposed bottom the lower section of groove 102, and the second groove 107.See Fig. 2 h, the end of the first groove 102
Portion may be located in the second groove 107.
Step 170, in described second groove and described wafer second surface makes the second insulating barrier.
See Fig. 2 i, in the second groove 107 and wafer 10 second surface 200 surface makes the second insulating barrier 108.The
Two insulating barriers 108 can be to be formed on wafer 10 second surface 200 surface by thermally grown or depositing technics.
Step 180, in described second groove, form the 3rd groove, first line layer described in exposed portion.
See Fig. 2 j, in the second groove 107, form the 3rd groove 109, expose first line layer 105.
It should be noted that the 3rd groove 109 can be formed by kinds of processes, as long as the 3rd groove 109 exposed portion
First line layer 105.
Alternatively, see Fig. 2 j, the 3rd groove 109 can be formed in the second groove 107 by mechanical cutting processes, the
The first groove 102 it is positioned at, the sidewall exposed portion first line layer 105 of the 3rd groove 109 bottom three grooves 109.
Alternatively, Fig. 2 k is seen, it is also possible to etch the first insulating barrier 103 and the second insulation bottom the second groove 107
Layer 108, forms the 3rd groove 109；Exposed portion first line layer 105 bottom 3rd groove 109.Etching technics can be such as
Dry etching or wet etching.
It should be noted that the making of the second groove 107 and the 3rd groove 109 is so that first line layer 105 He
Second line layer 110 of follow-up preparation realizes electrical connection, completes the signal of telecommunication by wafer 10 first surface 100 to second surface 200
The signal of telecommunication draw.And in the process, do not remove the wafer material under pad liner 101 so that wafer pad liner
Wafer material is there is not thin at 101, easy fracture, the problem that package strength reliability is the highest.
Step 190, in described second surface of insulating layer and described 3rd groove, sequentially form the second line layer and resistance
Layer, described second line layer electrically connects with described first line layer.
See Fig. 2 l, in the second insulating barrier 108 and the 3rd groove 109, be sequentially formed with the second line layer 110 and welding resistance
Layer 111, the second line layer 110 and first line layer 105 electrically connect.So complete the signal of telecommunication in wafer 10 from chip unit
Cause the transmittance process of wafer 10 second surface 200 by way of first line layer 105 and the second line layer 110 to pad liner 101.
Compared to the structure by the signal of telecommunication being caused at 101 times formation through holes of pad liner wafer second surface, the embodiment of the present invention
Wafer material under middle pad liner is the most thinning (seeing at the dotted line frame in Fig. 2 l), therefore can avoid in encapsulation process
In, at pad liner, wafer material is relatively thin, is susceptible to fracture, the problem causing the interruption of the signal of telecommunication.
If the first surface 100 at wafer is bonded supports substrate, and the second surface 200 of wafer 10 is carried out thinning place
Reason.The most after step 190 and also included before step 200: remove and support substrate 20.With reference to Fig. 2 m, remove substrate
20.Remove substrate 20 in this step, in previous process step, both enhanced wafer mechanical strength, be again follow-up cutting technique
Reduce cutting difficulty.
Step 200, along described second groove cut the plurality of chip unit form multiple individual chips.
Seeing Fig. 2 n, the cutting of multiple chip units is formed multiple individual chips by the center along the second groove 107.Cut
Cut technique such as to be cut by line.
Alternatively, Fig. 2 o is seen, after step 190, and before step 200, it is also possible to include step 201:
Fill the second glue in described second groove and described 3rd groove and solidify.
Before cutting crystal wafer, in the second groove 107 and the 3rd groove 109, fill the second glue 112, and solidify, permissible
Increase the mechanical strength of wafer further.
The chip packaging method that the embodiment of the present invention provides, by filling first in the first groove of wafer first surface
Glue, and solidifying, and make substrate at wafer first surface, so carries out reduction processing at second surface, to form second recessed
When groove and the 3rd groove and formation the second line layer, wafer is provided strength support.By said method, can not spend
Except the wafer material below wafer pad liner, can realize causing the wafer pad liner signal of telecommunication mesh of wafer second surface
, solve wafer ratio at wafer pad liner relatively thin, easy fracture, the problem that package strength reliability is the highest.
Embodiment two
Based on same inventive concept, the embodiment of the present invention two provides chip-packaging structure, and the embodiment of the present invention two provides
Chip-packaging structure may refer to Fig. 2 n.Describe in detail as a example by Fig. 2 n below.Seeing 2n, chip-packaging structure includes
Wafer 10.Wafer 10 can be silicon, germanium or other semiconductor substrate materials.Wafer 10 has first surface 100 and with first
The second surface 200 that surface 100 is relative, wafer 10 first surface 100 is integrated with multiple chip unit (not shown).Chip unit
E.g. by repeatedly photoetching, ion implanting, etch and the technique such as evaporation is formed at wafer first surface and to have specific function
Multilayer electronic component composition circuit structure.
It is formed with the first groove between the pad liner 101 of adjacent chips unit.Pad liner 101 is equivalent to each chip
The extraction electrode of unit, pad liner 101 is connected with the circuit structure in chip unit.First groove such as can be by continuously
Photoetching and deep reaction ion etching technique are formed.
First groove is interior and wafer 10 first surface 100 is formed with the first insulating barrier 103, and the first insulating barrier 103 has
Multiple hatch frames, hatch frame exposed pad liner 101.First insulating barrier 103 can be by thermally grown or deposit work
Skill is formed at wafer 10 first surface 100.Alternatively, the first insulating barrier 103 can be SiO2.When the first insulating barrier 103 is SiO2
Time, SiO2Can by thermally grown or deposit by the way of generate.Thermally grown technique is i.e. allowed to brilliant by being externally supplied high purity oxygen gas
Circle (such as silicon chip) reaction, forms layer of oxide layer at silicon chip surface, and this oxide layer is the first insulating barrier 103.Deposit is the most logical
Cross and be externally supplied oxygen and silicon source, make them react in cavity, thus form layer of oxide layer thin film at silicon chip surface, i.e. the
One insulating barrier 103.Hatch frame such as can by patterned mask plate when crystal column surface forms the first insulating barrier 103,
Reserve hatch frame；The system of hatch frame such as can also be completed by etching technics after forming the first insulating barrier 103
Make.
The surface of the first insulating barrier 103 is formed with first line layer 105, and first line layer 105 is electrically connected with pad liner 101
Connect.Alternatively, the first line layer 105 on the surface of the first insulating barrier 103 can include one or more layers metal.First line
The preparation technology of layer 105 can be such as magnetron sputtering technique.The signal of telecommunication of pad liner 101 is drawn by first line layer 105
First surface 100 to wafer 10.It should be noted that multiple layer metal forms first line layer 105 relatively layer of metal forms the
One line layer 105 can preferably electrically connect with being formed between pad liner 101.Exemplarily, on the first insulating barrier 103 surface
Splash-proofing sputtering metal titanium, then sputter layer of metal copper by magnetron sputtering at metallic titanium surface, thus complete the making of metal wiring layer.
The first glue 106 of solidification it is filled with in first groove.First glue 106 can be such as the high scores such as epoxy resin
Sub-material, after overcuring, can increase the mechanical strength of wafer 10.
Wafer 10 second surface 200 is formed with the second groove 107, and the second groove 107 is positioned at the lower section of the first groove 1, and
The first insulating barrier 103 is exposed bottom second groove 107.Second groove 107 such as can pass through photoetching and deep reaction ion etching
Technique is formed.
Alternatively, before the second surface 200 of wafer 10 forming the second groove 107, it is also possible at the of wafer 10
One surface 100 bonding supports substrate, and the second surface 200 of wafer 10 is carried out reduction processing.Bonding substrate is to subtract
Thin technical process increases mechanical strength.Reduction process can be such as chemical mechanical milling tech.Relatively thin wafer substrate material
Material can reduce dry etching, the difficulty of the technique such as machine cuts and rewiring, and meanwhile, thinner wafer thickness can be improved
Chip cooling, and make product become thinner.
Second groove 107 is interior and wafer 10 second surface 200 is formed with the second insulating barrier 108.Second insulating barrier 108 can
Being to be formed on wafer 10 second surface 200 surface by thermally grown or depositing technics.It is formed with the 3rd in second groove 107
Groove 109, the 3rd groove 109 exposed portion first line layer 105.Depend in second insulating barrier 108 surface and the 3rd groove 109
Secondary the second line layer 110 and the solder mask 111 of being formed, the second line layer 110 electrically connects with first line layer 105.So complete
The signal of telecommunication in wafer 10 causes by way of first line layer 105 and the second line layer 110 from chip unit to pad liner 101
The transmittance process of wafer 10 second surface 200.Compared to by the signal of telecommunication being caused wafer at 101 times formation through holes of pad liner
The structure of second surface, in the embodiment of the present invention, the wafer material under pad liner is the most thinning, therefore can avoid in envelope
In process of assembling, at pad liner, wafer material is relatively thin, is susceptible to fracture, the problem causing the interruption of the signal of telecommunication.
Seeing Fig. 2 n, the cutting of multiple chip units is formed multiple individual chips by the center along the second groove 107.Cut
Cut technique such as to be cut by line.
Owing to being bonded support substrate at the first surface 100 of wafer, and the second surface 200 of wafer 10 is carried out thinning
Process.Alternatively, in order to reduce the thickness of diced chip, before the cutting of multiple chip units is formed multiple individual chips also
Support substrate can be removed.Before diced chip unit, remove support substrate in previous process step, both enhance wafer machine
Tool intensity, reduces cutting difficulty for cutting technique again.
It should be noted that the chip-packaging structure described in the embodiment of the present invention can be prepared by said chip method for packing
Formed.
The chip-packaging structure that the embodiment of the present invention provides, owing to need not remove the wafer material below wafer pad liner
Material, can realize causing the wafer pad liner signal of telecommunication purpose of wafer second surface, therefore solve wafer pad liner
Place's wafer ratio is relatively thin, easy fracture, the problem that package strength reliability is the highest.
Alternatively, setting can be docked with the bottom of the first groove in the bottom of the second groove 107, i.e. as shown in Fig. 2 n.Figure
Setting is docked in the bottom of bottom and the first groove that what 2n was exemplary arrange the second groove 107, and not to the embodiment of the present invention
Restriction, in other embodiments, can according to actual application scenarios difference the first groove and the shape of the second groove 107 are set
Shape, size and position, as long as ensureing that the second groove 107 is positioned at the lower section of the first groove, and expose the bottom the second groove 107
One insulating barrier.In other embodiments, seeing shown in Fig. 2 p, the bottom of the first groove may be located on the second groove
In 107.
Exemplary, as shown in Fig. 2 n, may be located at bottom the 3rd groove 109 in first groove, the side of the 3rd groove 109
Wall exposed portion first line layer 105.See shown in Fig. 2 q, it is also possible to be exposed portion first line bottom the 3rd groove 109
Layer 105.It should be noted that the 3rd groove 109 can be formed by kinds of processes, as long as the 3rd groove 109 exposed portion the
One line layer 105.
Alternatively, see Fig. 2 n, the 3rd groove 109 can be formed in the second groove 107 by mechanical cutting processes, the
The first groove it is positioned at, the sidewall exposed portion first line layer 105 of the 3rd groove 109 bottom three grooves 109.
Alternatively, Fig. 2 q is seen, it is also possible to etch the first insulating barrier 103 and the second insulation bottom the second groove 107
Layer 108, forms the 3rd groove 109；Exposed portion first line layer 105 bottom 3rd groove 109.Etching technics can be such as
Dry etching or wet etching.
It should be noted that the making of the second groove 107 and the 3rd groove 109 is so that first line layer 105 He
Second line layer 110 of follow-up preparation realizes electrical connection, completes the signal of telecommunication by wafer 10 first surface 100 to second surface 200
The signal of telecommunication draw.And in the process, do not remove the wafer material under pad liner 101 so that wafer pad liner
Wafer material is there is not thin at 101, easy fracture, the problem that package strength reliability is the highest.
Alternatively, seeing Fig. 2 r, in the second groove 107 and the 3rd groove, 109 can also be filled with the second glue of solidification
112.Before cutting crystal wafer, in the second groove 107 and the 3rd groove 109, fill the second glue 112 and solidify, one can be entered
Step increases the mechanical strength of wafer.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious change,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although by above example, the present invention is carried out
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. chip packaging method, it is characterised in that described method includes:
Step 110, offer wafer, described wafer has first surface and the second surface relative with first surface, described crystalline substance
Circle first surface is integrated with multiple chip unit, and each described chip unit is provided with some pads lining at described first surface
Pad；
Step 120, between the pad liner of adjacent described chip unit, form the first groove；
Step 130, in described first groove and described wafer first surface forms the first insulating barrier, described first insulating barrier
Having multiple hatch frame, described hatch frame exposes described pad liner；
Step 140, make first line layer, described first line layer and described pad liner on the surface of described first insulating barrier
Electrical connection；
Step 150, in described first groove, fill the first glue and solidify；
Step 160, forming the second groove at described wafer second surface, described second groove is positioned under described first groove
Side, and described second bottom portion of groove exposes described first insulating barrier；
Step 170, in described second groove and described wafer second surface makes the second insulating barrier；
Step 180, in described second groove, form the 3rd groove, first line layer described in exposed portion；
Step 190, in described second surface of insulating layer and described 3rd groove, sequentially form the second line layer and solder mask,
Described second line layer electrically connects with described first line layer；
Step 200, along described second groove cut the plurality of chip unit form multiple individual chips.
Method the most according to claim 1, it is characterised in that after described step 150, and in described step 160
Before, step 151 is also included:
Described first surface at described wafer is bonded and supports substrate, and the described second surface of described wafer is carried out thinning place
Reason；
After described step 190, and also included before described step 200: remove described support substrate.
Method the most according to claim 1, it is characterised in that after described step 190, and in described step 200
Before, step 201 is also included:
In described second groove and described 3rd groove, fill the second glue and solidify.
Method the most according to claim 1, it is characterised in that described step 180 includes:
Forming the 3rd groove in described second groove by mechanical cutting processes, described 3rd bottom portion of groove is positioned at described first
In groove, first line layer described in the sidewall exposed portion of described 3rd groove.
Method the most according to claim 1, it is characterised in that described step 180 includes:
Etch described first insulating barrier of described second bottom portion of groove and described second insulating barrier, form the 3rd groove；Described
First line layer described in 3rd bottom portion of groove exposed portion.
Method the most according to claim 1, it is characterised in that the bottom of described second groove and the end of described first groove
Portion's docking is arranged；Or, the bottom of described first groove is positioned at described second groove.
7. chip-packaging structure, it is characterised in that including:
Wafer, described wafer has first surface and the second surface relative with described first surface, described wafer the first table
Face is integrated with multiple chip unit；It is formed with the first groove between the pad liner of adjacent described chip unit；Described first recessed
In groove and described wafer first surface is formed with the first insulating barrier, described first insulating barrier has multiple hatch frame, described
Hatch frame exposes described pad liner；The surface of described first insulating barrier is formed with first line layer, described first line layer
Electrically connect with described pad liner；The first glue of solidification it is filled with in described first groove；Described wafer second surface is formed
There are the second groove, described second groove to be positioned at the lower section of described first groove, and described second bottom portion of groove exposes described first
Insulating barrier；In described second groove and described wafer second surface is formed with the second insulating barrier；Formed in described second groove
There is the 3rd groove, first line layer described in described 3rd groove exposed portion；Described second surface of insulating layer and the described 3rd
Being sequentially formed with the second line layer and solder mask in groove, described second line layer electrically connects with described first line layer.
Encapsulating structure the most according to claim 7, it is characterised in that the bottom of described second groove and described first groove
Bottom docking arrange；Or, the bottom of described first groove is positioned at described second groove.
Encapsulating structure the most according to claim 7, it is characterised in that
Described 3rd bottom portion of groove is positioned at described first groove, first line described in the sidewall exposed portion of described 3rd groove
Layer；Or, first line layer described in described 3rd bottom portion of groove exposed portion.
Encapsulating structure the most according to claim 7, it is characterised in that fill out in described second groove and described 3rd groove
It is filled with the second glue of solidification.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113555288A (en) * | 2020-07-15 | 2021-10-26 | 珠海越亚半导体股份有限公司 | Method for manufacturing package substrate |
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| US5910687A (en) * | 1997-01-24 | 1999-06-08 | Chipscale, Inc. | Wafer fabrication of die-bottom contacts for electronic devices |
| EP0926723A1 (en) * | 1997-11-26 | 1999-06-30 | STMicroelectronics S.r.l. | Process for forming front-back through contacts in micro-integrated electronic devices |
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