CN106205735A - Embedded chip method of testing and system - Google Patents
Embedded chip method of testing and system Download PDFInfo
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- CN106205735A CN106205735A CN201510214829.6A CN201510214829A CN106205735A CN 106205735 A CN106205735 A CN 106205735A CN 201510214829 A CN201510214829 A CN 201510214829A CN 106205735 A CN106205735 A CN 106205735A
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Abstract
A kind of embedded chip method of testing and system, described system includes: tester, test platform and latch, wherein: described tester, is suitable to generate test signal and exported by test signal output part；Described test platform, including: test signal input part, latch control terminal and test result outfan, wherein: described test signal input part couples with the test signal output part of described tester and the test signal input part of described embedded chip respectively, and described latch control terminal couples with described latch；Described test result outfan couples with the test result input of described tester；Described latch, including: response signal input part, couple with the data output end of described embedded chip；Latch data outfan, couples with described test result outfan.Use described method and system, it is possible to reduce the test time delay of embedded chip, promote test speed.
Description
Technical field
The present invention relates to chip testing field, particularly relate to a kind of embedded chip method of testing and system.
Background technology
There is not external pin in in-line memory IP, it is possible to saves pad (PAD) space and pin institute
The space occupied, is therefore widely used in system level chip (SOC).
In actual applications, before in-line memory dispatches from the factory, can be to the function of in-line memory
Test, to know whether current in-line memory can normally work.Due to embedded storage
Device does not has pin, only electrode contacts, therefore directly cannot be entered it by existing apparatus for testing chip
Row test.
In the prior art, built-in self-test (Built In Self Test, BIST) is generally used to come indirectly
In-line memory is tested by ground, by probe card and connect wire etc. by in-line memory with
Test device connects, thus tests in-line memory.
But, when using existing BIST approach that in-line memory is tested, test device
All there is time delay in input and output port, there is the problem that test time delay is longer, causes cannot be carried out at a high speed
Frequency test.
Summary of the invention
The problem that the embodiment of the present invention solves is how to reduce the test time delay of embedded chip, promotes test
Speed.
For solving the problems referred to above, the embodiment of the present invention provides a kind of embedded chip test system, including:
Tester, test platform and latch, wherein:
Described tester, is suitable to generate test signal and exported by test signal output part；
Described test platform, including: test signal input part, latch control terminal and test result output
End, wherein: described test signal input part respectively with the test signal output part of described tester and described
The test signal input part of embedded chip couples, and described latch control terminal couples with described latch；Institute
The test result input stating test result outfan and described tester couples；
Described latch, including: response signal input part, with the data output end of described embedded chip
Couple, be suitable to the response signal receiving described embedded chip to generating after described testing signal process；
Latch data outfan, couples with described test result outfan, is suitable to receiving described latch control
By described response signal latch during the latch signal that end sends, and the response signal after latching inputs extremely
Described test result outfan.
Optionally, described latch control terminal couples with the external clock preset, and described latch is suitable to receive
The clock signal that described external clock generates, and when described clock signal level saltus step being detected, by institute
State response signal latch.
Optionally, described latch control terminal couples with the controller preset, and described latch is suitable to receive institute
State the control signal that controller generates, control described latch by described response signal latch.
Optionally, described test platform includes: probe card and the pad coupled with described probe card, institute
Stating probe card and include many probes, the quantity of described probe is more than or equal to described embedded chip electrode contacts
Quantity.
Optionally, described embedded chip is in-line memory.
For solving the problems referred to above, the embodiment of the present invention additionally provides a kind of embedded chip method of testing, bag
Include:
Receive the test signal that tester generates, and by the input of described test signal to embedded core to be tested
Sheet；
Receive the response signal after the latch of latch output, and by the response signal after described latch
Input is to described tester, wherein: described response signal is that described embedded chip to be tested is to described survey
Trial signal generates after processing, and described response signal is carried out by described latch when receiving latch signal
Latch, the response signal after being latched.
Optionally, described response signal is latched by described latch when receiving latch signal, bag
Include: described latch receives the clock signal that peripheral clock generates, and described clock signal detected
During level saltus step, by described response signal latch.
Optionally, described response signal is latched by described latch when receiving latch signal, bag
Include: when described latch receives the control signal that default controller generates, by described response signal lock
Deposit.
Optionally, described embedded chip is in-line memory.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantage that
By the test signal input part input test signal of test platform, by latch control terminal to latch
Device input and latch signal.When receiving the latch signal that latch control terminal sends, latch is to response letter
Number carry out latching and inputting to test result outfan.Owing to the signal of test result outfan output is lock
Response signal after depositing, therefore, the time delay of test platform outfan is not to the response after latching
The state of signal produces impact, therefore can ignore output time delay, such that it is able to reduce test time delay, improves
Test speed.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing a kind of embedded chip test system；
Fig. 2 be existing embedded chip test system carry out test chip time sequential chart；
Fig. 3 is a kind of embedded chip test system structure schematic diagram in the embodiment of the present invention；
Fig. 4 be in the embodiment of the present invention a kind of embedded chip test system carry out test chip time time
Sequence figure；
Fig. 5 is the flow chart of a kind of embedded chip method of testing in the embodiment of the present invention.
Detailed description of the invention
In the prior art, built-in self-test (Built In Self Test, BIST) is generally used to come indirectly
In-line memory is tested by ground, by probe card and connect wire etc. by in-line memory with
Test device connects, thus tests in-line memory.But, using existing BIST side
When in-line memory is tested by method, all there is time delay in the input and output port of test device, deposits
In the problem that test time delay is longer, cause cannot be carried out fast frequency test.
With reference to Fig. 1, give the structural representation of a kind of embedded chip of the prior art test system,
Including: tester 101, test platform 102, wherein:
Tester 101 is coupled by signal transmssion line with test platform 102, and test platform 102 includes many
Individual pad 1021 and the probe 1022 of correspondence, the electrode contacts of embedded chip 104 to be tested and survey
Multiple pads 1021 in examination platform 102 couple.
Tester 101 generates test signal, and inputs to test platform 102.Due to embedded chip 104
The pad 1021 of electrode contacts and test platform 102 couple, therefore test platform 102 can will be tested
Signal inputs to embedded chip 104.Test signal is processed by embedded chip 104, generates correspondence
Response signal, and response signal is inputted to tester 101, tester 101 via test platform 102
Judge whether the embedded chip 104 of test can normally work according to response signal.
With reference to Fig. 2, give the test system sequential when embedded chip 104 is tested in Fig. 1
Figure.In Fig. 2, ADD is expressed as the sequential chart of address signal, and it is raw that AE_PAD is expressed as tester 101
The sequential chart of the test signal become, AE_int is expressed as the test signal that embedded chip 104 receives
Sequential chart, DOUT_int is expressed as the sequential chart of the response signal of embedded chip 104 output, DOUT
It is expressed as the sequential chart of the test result that tester 101 receives.
As in figure 2 it is shown, at t0In the moment, tester 101 generates test signal, tests signal AE_PAD
For high level, at t1In the moment, embedded chip 104 receives test signal AE_int, therefore, test
Signal AE_int is high level.It is to say, the test signal that tester 101 generates is being input to embedding
Time in formula chip 104, there is certain input delay, input delay time a length of: t1-t0.There is input
The reason of time delay is: test signal is being generated to input to embedded chip 104 from tester 101
During, need to be through signal transmssion line, probe 1022 and the transmission of pad 1021, input delay is
Produced when signal transmssion line, probe 1022 and the pad 1021 etc. by test.
At t2In the moment, embedded chip 104 output response signal, at t3In the moment, tester 101 receives
To response signal.It is to say, the response signal of embedded chip 104 output is being input to tester 101
Time middle, there is certain output time delay, time a length of t of output time delay3-t2.Output time delay exist reason with
The reason that input delay exists is identical, does not repeats.
At t4In the moment, complete a test period, say, that a test of existing test system
Cycle is t0～t4, and it is true that at t3In the moment, test process is over.
Understanding in from the discussion above, there is input delay and output time delay in existing test system, i.e. deposits
In the problem that test time delay is bigger, therefore chip cannot be carried out fast frequency test.In output time delay relatively
Time big, the state of the response signal that tester receives, it may happen that change, causes tester to receive
The state of response signal may be different from virtual condition, and such as, response signal virtual condition is normal condition,
And tester receives the problem of the abnormal state responding signal, cause the generation of erroneous judgement situation.
In embodiments of the present invention, by the test signal input part input test signal of test platform, logical
Cross latch control terminal to latch input and latch signal.Receiving the latch signal that latch control terminal sends
Time, response signal is latched and inputs to test result outfan by latch.Owing to test result is defeated
The signal going out end output is the response signal after latching, and therefore, the time delay of test platform outfan is not
There is the state on the response signal after latching to produce impact, therefore output time delay can be ignored, such that it is able to
Reduce test time delay, improve test speed.
Understandable for enabling the above-mentioned purpose of the embodiment of the present invention, feature and advantage to become apparent from, knot below
Close accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiments providing a kind of embedded chip test system, with reference to Fig. 3, embedded chip is surveyed
Test system includes: tester 101, test platform 102 and latch 103, wherein:
Tester 101, is suitable to generate test signal, and it is defeated that the test signal generated is passed through test output terminal
Go out.In actual applications, tester 101 can be used exclusively for specific a certain or various chips
Performance carry out the instrument tested.Such as, tester can be specifically designed to and survey in-line memory
The instrument of examination.
In embodiments of the present invention, test signal can be address enable signal.In the present invention, other are implemented
In example, test signal can also be other kinds of signal, carries out embedded chip performance as long as meeting
Test.
Test platform 102, couples with tester 101 and embedded chip 104 to be tested respectively, makes
Obtain tester 101 can embedded chip 104 be tested.In embodiments of the present invention, embedded
Chip 104 can be in-line memory, it is also possible to for other embedded element.
In being embodied as, test platform 102 may include that test signal input part IN, latches control
End CON and test result outfan OUT, wherein:
Test signal input part IN can respectively with the test signal output part of tester 101 and to be tested
The test signal input part of embedded chip 104 couple, receive the test signal output of tester 101
The test signal of end output, and input the test signal input part to embedded chip 104 to be tested.
Latch control terminal CON can couple with latch 103, is suitable to believe to latch 103 input and latch
Number, to control latch 103 by current demand signal latch.
Embedded chip 104 to be tested, after receiving test signal, can generate with to test signal relative
The response signal answered.In embodiments of the present invention, after embedded chip 104 generates response signal, and
It not the test result outfan OUT that response signal is directly output to test platform 102, but will ring
Induction signal inputs to latch 103.
In being embodied as, latch 103 can include responding signal input part and latch data output
End.After embedded chip 104 generates response signal, by the response of response signal output to latch 103
Signal input part.Latch 103 receives response signal, and is receiving latch control terminal CON output
During latch signal, the response signal received is latched.
From the operating characteristic of latch, the response signal being currently entered can be latched by latch,
Preserve the current state of the response signal of input.After response signal is latched, will be after latching
Response signal input to the test result outfan of test platform.
The test result outfan OUT of test platform 102 can input with the test result of tester 101
End couples, the response after the response signal after the latch receiving latch 103 output, after latching
Signal, namely test result, input is to tester 101.By tester 101, test result is carried out
Judge, i.e. would know that the embedded chip 104 currently carrying out testing is the most normal.
In embodiments of the present invention, with reference to Fig. 3, test platform 102 can by probe and with probe card coupling
The pad composition connect, wherein, the number of probe is more than or equal to the quantity of embedded chip electrode contacts.?
In Fig. 3, black box is expressed as pad, is connected with pad and stretches out the straight line of test platform 102 for visiting
Pin, the electrode contacts of embedded chip 104 to be tested couples with pad.
Tester 101 can be coupled with probe by signal transmssion line, after output test signal, and test
Signal inputs to pad via probe.Electrode contacts due to pad Yu embedded chip 104 to be tested
Couple, therefore can be by test signal input to embedded chip 104 to be tested.
In actual application, test platform also 102 can be other structures, as long as meeting tester
101 couple with embedded chip 104 to be tested so that embedded chip can be carried out by tester 101
Test and obtain corresponding test result, do not repeat.
In embodiments of the present invention, latch control terminal CON can control device with the latch of peripheral hardware and couple,
Control, to receive to latch, the latch signal that device generates, and send to latch 103.To embedded chip
104 when testing, and latches and controls device and timing can send latch signal to latch control terminal CON,
Latch control terminal CON timing is made to send latch signal to latch 103, so that latch 103
Response signal is latched by timing.
In embodiments of the present invention, when embedded chip 104 is tested, in each test period
In, timing sends the time point of latch signal and can be: embedded chip 104 to be tested is from starting reception
Test signal extremely generates the time slot point t that the duration needed for responding signal is corresponding.
It is to say, within each test period, reach t at the duration that embedded chip 104 is tested
Time, latch and control device generation latch signal and send to latch control terminal CON, latch control terminal CON
The latch signal that forwarding latch control device generates is to latch 103, to control latch 103 by current
Response signal latch.
In embodiments of the present invention, latching control device can be external clock.Latch control terminal CON with
External clock couples, and the clock signal generated by external clock sends to latch 103 as latch signal,
The latch operation of latch 103 is i.e. controlled by clock signal.
When latch signal is clock signal, the dutycycle of clock signal can be configured so that
When testing so that in the clock cycle, the hopping edge of clock signal and time a length of t of initial time.
It is to say, when clock signal generation saltus step, latch 103 is by current response signal latch.
It is understood that in actual applications, it is contemplated that the problems such as input delay, in each test week
In phase, the duration that the time point of timing transmission latch signal is corresponding can also be t+ △ t, and wherein △ t is input
Time delay.The duration of △ t can obtain according to reality test, it is also possible to is set according to actual needs, only
The time point regularly sending latch signal is in current test period.
In actual applications, it is also possible to trigger latch signal in other way.In another reality of the present invention
Executing in example, latch control terminal CON couples with the controller preset, and the controller timing preset generates and controls
Signal, and input to latch control terminal CON, i.e. latch signal be control signal.Latch 103 is connecing
After receiving control signal, response data is cached.
Within each test period, the acquisition of the time point that controller timing generates and sends control signal can
With reference to the above embodiment of the present invention, not repeat.
The embedded chip test system provided for the above embodiment of the present invention, below to above-mentioned embedded
The workflow of chip test system is described in detail.
When testing, tester 101 generates test signal, and is exported by test signal output part.
Tester 101 is coupled by the test signal input part IN of signal transmssion line with test platform 102, will survey
Trial signal inputs the test signal input part IN to test platform 102.
External clock generates clock signal and exports, and external clock passes through signal transmssion line and latch control terminal
CON couples, and latch control terminal CON couples with latch 103, thus the clock signal of generation is sent out
Delivering to latch 103, now, latch signal is clock signal.
Test signal is inputted to embedded chip 104 by test platform 102, and embedded chip 104 is to test
Signal processes, and generates the response signal corresponding with testing signal, and the response signal input that will generate
To latch 103.
Latch 103 receive embedded chip 104 output response signal and external clock input time
Clock signal.When detecting that clock signal is in rising edge, response signal is carried out latch operation, and will
Response signal through latching is exported to tester by test result outfan OUT.
Tester 101 receives the response signal through latching, and judges response signal, knows and works as
Before the embedded chip 104 that carries out testing whether be normal chip.
With reference to Fig. 4, chip is being entered by the embedded chip test system that giving during the present invention one implements provides
Sequential chart during row test.
Wherein, CLK is expressed as the sequential chart of the clock signal that latch 103 receives.
It should be noted that the clock signal that the test signal that tester 101 generates generates with peripheral clock
Synchronization is separately input into embedded chip 104 and latch 103.Therefore, latch 103 receives
Clock signal there is also input delay, and input delay receives when testing signal with embedded chip 104
The duration of input delay is equal, is t1-t0。
Within a test period, the original levels of clock signal is low level.Level in clock signal
When being high level by low transition, i.e. at t2During the moment, response signal is latched by latch 103,
And will export through the signal latched.Owing to when latching, the state of response signal will not change,
Therefore, even if there is output time delay when output, also the response signal after latching will not be produced impact,
That is: output time delay can be ignored.
Compared with embedded chip test system compare, the embodiment of the present invention provide embedded chip
Test system is without considering output time delay, and the duration of a test period is only t0～t3, test period is big
Big shortening.
As can be seen here, by the test signal input part input test signal of test platform, believed by clock
The clock signal that number input input peripheral clock generates, test signal and clock signal synchronization are input to treat
Surveying in embedded chip, test signal time delay and clock signal time delay are equal.By inciting somebody to action of latch timing
Response signal latch, and will latch after response signal export to test result outfan, test result
There is the signal of output time delay in outfan output, i.e. by latching through the signal latched rather than output
Response signal, can eliminate output time delay, such that it is able to reduce test time delay, therefore can improve test
Speed.Further, owing to latching response data, the state of the response signal that tester receives is not
Can change, the situation of erroneous judgement therefore can be avoided to occur.
The embodiment of the present invention additionally provides a kind of embedded chip method of testing, with reference to Fig. 5, below by way of tool
Body step is described in detail.
Step S501, receives the test signal that tester generates, and by the input of described test signal to be measured
Examination embedded chip.
In embodiments of the present invention, tester generates test signal and inputs to embedded chip to be tested
Process is referred to the above embodiment of the present invention, does not repeats.
Step S502, receives the response signal after the latch of latch output, and by after described latch
The input of response signal to described tester.
In embodiments of the present invention, described response signal is that described embedded chip to be tested is to described test
Generating after signal processing, described response signal is locked by described latch when receiving latch signal
Deposit, the response signal after being latched.
In embodiments of the present invention, described response signal is entered by described latch when receiving latch signal
Row latches, including: described latch receives the clock signal that peripheral clock generates, and detecting
When stating clock signal level saltus step, by described response signal latch.
In embodiments of the present invention, described response signal is entered by described latch when receiving latch signal
Row latches, including: when described latch receives the control signal that default controller generates, by described
Response signal latch.
In embodiments of the present invention, described embedded chip can be in-line memory.
Above-mentioned steps S501～S502 all can refer in the above embodiment of the present invention the embedded chip provided
The workflow of test system, here is omitted.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment
Suddenly the program that can be by is to indicate relevant hardware to complete, and this program can be stored in a computer can
Reading in storage medium, storage medium may include that ROM, RAM, disk or CD etc..
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (9)
1. an embedded chip test system, it is characterised in that including: tester, test platform and lock
Storage, wherein:
Described tester, is suitable to generate test signal and exported by test signal output part；
Described test platform, including:
Test signal input part, latch control terminal and test result outfan, wherein: described test signal is defeated
Enter end to input with the test signal output part of described tester and the test signal of described embedded chip respectively
End couples, and described latch control terminal couples with described latch；Described test result outfan and described survey
The test result input of examination instrument couples；
Described latch, including: response signal input part, couple with the data output end of described embedded chip,
Be suitable to the response signal receiving described embedded chip to generating after described testing signal process；Latch number
According to outfan, couple with described test result outfan, be suitable to receiving the transmission of described latch control terminal
Latch signal time by described response signal latch, and the response signal input after latching is to described survey
Test result outfan.
2. embedded chip test system as claimed in claim 1, it is characterised in that described latch control terminal
Coupling with default external clock, described latch is suitable to receive the clock signal that described external clock generates,
And when described clock signal level saltus step being detected, by described response signal latch.
3. embedded chip test system as claimed in claim 1, it is characterised in that described latch control terminal
Coupling with default controller, described latch is suitable to receive the control signal that described controller generates, control
Make described latch by described response signal latch.
4. embedded chip test system as claimed in claim 1, it is characterised in that described test platform bag
Including: probe card and the pad coupled with described probe card, described probe card includes many probes, described
The quantity of probe is more than or equal to the quantity of described embedded chip electrode contacts.
5. embedded chip test system as claimed in claim 1, it is characterised in that described embedded chip
For in-line memory.
6. an embedded chip method of testing, it is characterised in that including:
Receive the test signal that tester generates, and by the input of described test signal to embedded chip to be tested；
Receive the response signal after the latch of latch output, and the response signal after described latch is inputted
To described tester, wherein: described response signal is that described embedded chip to be tested is to described test letter
Number process after generate, described response signal is latched by described latch when receiving latch signal,
Response signal after being latched.
7. embedded chip method of testing as claimed in claim 6, it is characterised in that described latch is connecing
When receiving latch signal, described response signal is latched, including: when described latch receives peripheral hardware
The clock signal that clock generates, and when described clock signal level saltus step being detected, by described response signal
Latch.
8. embedded chip method of testing as claimed in claim 6, it is characterised in that described latch is connecing
When receiving latch signal, described response signal is latched, including: described latch receives default
During the control signal that controller generates, by described response signal latch.
9. embedded chip method of testing as claimed in claim 6, it is characterised in that described embedded chip
For in-line memory.
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| CN111693847B (en) * | 2020-05-18 | 2022-08-12 | 大唐微电子技术有限公司 | Chip testing method and device |
| CN115047319A (en) * | 2022-07-01 | 2022-09-13 | 深圳市灵明光子科技有限公司 | Test circuit for multiple chips under same package |
| CN115047319B (en) * | 2022-07-01 | 2024-04-30 | 深圳市灵明光子科技有限公司 | Test circuit for multiple chips under same package |
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