CN106200741B - The heavy load circuit of electric current and low pressure difference linear voltage regulator - Google Patents
The heavy load circuit of electric current and low pressure difference linear voltage regulator Download PDFInfo
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- CN106200741B CN106200741B CN201610596446.4A CN201610596446A CN106200741B CN 106200741 B CN106200741 B CN 106200741B CN 201610596446 A CN201610596446 A CN 201610596446A CN 106200741 B CN106200741 B CN 106200741B
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention provides a kind of heavy load circuit of electric current and low pressure difference linear voltage regulator, the low pressure difference linear voltage regulator to include：The heavy load circuit of one bandgap reference circuit, an amplifier, 1 the 12nd MOS transistor, a second resistance, a 3rd resistor, one first electric capacity and an electric current, the heavy load circuit of the electric current is parallel to the both ends of a load, one end of the load is connected to the drain electrode of the 12nd MOS transistor, other end ground connection.When the low pressure difference linearity wave filter is carrying out pattern switching, load circuit is sunk using the electric current to reduce the frequency of the total load current of the low pressure difference linearity wave filter, so that the low pressure difference linear voltage regulator has enough time responding, while will not also waste excessive electric current, power consumption is saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a current sink load circuit and a low dropout regulator.
Background
Recently, there are more and more occasions where it is necessary to use LDO (low dropout linear regulator) to power a chip. Referring to fig. 1, fig. 1 shows a schematic structural diagram of a currently used LDO. The conventional LDO includes: a bandgap reference circuit 101, an amplifier 102, a twelfth MOS transistor M12, a second resistor R2, a third resistor R3 and a first capacitor C1, wherein, the output end of the band gap reference circuit 101 is connected with the inverting input end of the amplifier 102, the output terminal of the amplifier 102 is connected to the gate of the twelfth MOS transistor M12, the source of the twelfth MOS transistor M12 is connected to the second voltage VDD, the drain is connected to one end of the second resistor R2, the other end of the second resistor R2 and one end of the third resistor R3 are connected in series at a third node, the other end of the third resistor R3 is grounded, the third node is connected to the non-inverting input terminal of the amplifier 102, one end of the first capacitor C1 is connected to the drain of the twelfth MOS transistor M12, and the other end is connected to ground, the output voltage of the drain of the twelfth MOS transistor M12 is the output voltage VOUT1 of the conventional LDO.
When the load current of the LDO changes rapidly, for example, 1ns or several ns, it is difficult for the conventional LDO to respond to the change of the output voltage of the LDO in such a short time. This is mainly due to the limited loop bandwidth of the LDO. The current solutions are: one is to filter out the ripple wave by using an off-chip capacitor; the other is with a sufficiently large on-chip capacitance. In any case, a capacitor needs to be introduced, and if the capacitor is not used for stabilizing the output voltage of the LDO, the ripple of the output voltage of the LDO is large.
Disclosure of Invention
The invention aims to provide a current sink load circuit and a low dropout regulator, which are used for reducing ripples of output voltage of an LDO (low dropout regulator) on the basis of not introducing a capacitor.
In order to achieve the above object, the present invention provides a current sinking load circuit, comprising: an RC filter circuit, a first resistor and a first MOS transistor; the grid electrode of the first MOS transistor is connected to the output end of the RC filter circuit, the source electrode of the first MOS transistor is grounded through the first resistor, and the drain electrode of the first MOS transistor is connected to a first voltage.
Preferably, in the above current sinking load circuit, the RC filter circuit includes: a second MOS transistor, a third MOS transistor, a fourth resistor, a fifth MOS transistor, a fifth resistor, a seventh MOS transistor, a second capacitor, a third capacitor, a tenth MOS transistor, and an eleventh MOS transistor;
the grid electrode of the second MOS transistor is connected with the grid electrode of the third MOS transistor, the source electrode of the second MOS transistor is connected with a second voltage, one end of the fourth resistor and the drain electrode of the fifth MOS transistor are connected with the drain electrode of the second MOS transistor, and the other end of the fourth resistor and the source electrode of the fifth MOS transistor are connected with a first node;
one end of the fifth resistor and the source electrode of the seventh MOS transistor are connected to the first node, the other end of the fifth resistor and the drain electrode of the seventh MOS transistor are connected to the drain electrode of the third MOS transistor, and the source electrode of the third MOS transistor is grounded;
one end of the second capacitor is connected to the second voltage, the other end of the second capacitor and one end of the third capacitor are connected to a second node, and the other end of the third capacitor is grounded;
a source of the tenth MOS transistor is connected to a drain of the eleventh MOS transistor, a drain of the tenth MOS transistor is connected to the second node, and a source of the eleventh MOS transistor is connected to the second voltage;
the first node and the second node are connected to a gate of the first MOS transistor.
Preferably, in the above current sink load circuit, the fourth resistor and/or the fifth resistor is/are a MOS transistor; wherein,
when the fourth resistor is a fourth MOS transistor, a drain of the fourth MOS transistor and a drain of the fifth MOS transistor are connected to a drain of the second MOS transistor, a source of the fourth MOS transistor and a source of the fifth MOS transistor are connected to the first node, and a gate of the fourth MOS transistor is grounded;
when the fifth resistor is a sixth MOS transistor, the source of the sixth MOS transistor and the source of the seventh MOS transistor are connected to the first node, the drain of the sixth MOS transistor and the drain of the seventh MOS transistor are connected to the drain of the third MOS transistor, and the gate of the sixth MOS transistor is connected to the second voltage.
Preferably, in the current sink load circuit, the second capacitor and/or the third capacitor is/are a MOS transistor; wherein,
when the second capacitor is an eighth MOS transistor, the source and the drain of the eighth MOS transistor are turned on and connected to the second voltage, and the gate is connected to the second node;
when the third capacitor is a ninth MOS transistor, the source and the drain of the ninth MOS transistor are turned on and connected to ground, and the gate is connected to the second node.
Preferably, in the current sink load circuit, a first control signal is simultaneously input to the gate of the second MOS transistor, the gate of the third MOS transistor, and the gate of the tenth MOS transistor.
Preferably, in the current sink load circuit, a second control signal is simultaneously input to the gate of the fifth MOS transistor and the gate of the seventh MOS transistor.
Preferably, in the current sink load circuit, an identification signal is input to the gate of the eleventh MOS transistor.
Preferably, in the current sink load circuit, the second MOS transistor, the fifth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are all P-type MOS transistors; the first MOS transistor, the third MOS transistor and the seventh MOS transistor are all N-type MOS transistors.
The present invention also provides a low dropout regulator, comprising: the current sinking load circuit is connected in parallel with two ends of a load, one end of the load is connected with the output voltage of the low dropout regulator, and the other end of the load is grounded.
Preferably, in the aforementioned low dropout linear regulator, the voltage regulator further comprises: a bandgap reference circuit, an amplifier, a twelfth MOS transistor, a second resistor, a third resistor, and a first capacitor, wherein an output terminal of the bandgap reference circuit is connected to an inverting input terminal of the amplifier, an output terminal of the amplifier is connected to a gate of the twelfth MOS transistor, a source of the twelfth MOS transistor is connected to a second voltage, a drain of the twelfth MOS transistor is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are connected in series to a third node, the other end of the third resistor is grounded, the third node is connected to a non-inverting input terminal of the amplifier, one end of the first capacitor is connected to a drain of the twelfth MOS transistor M12, and the other end of the first capacitor is connected to ground; one end of the load is connected with the drain electrode of the twelfth MOS transistor, and the output voltage of the drain electrode of the twelfth MOS transistor is the output voltage of the low dropout linear regulator.
In the current sink load circuit and the low dropout linear regulator provided by the invention, when the low dropout linear filter is switched in a mode, the current sink load circuit is utilized to reduce the frequency of the total load current of the low dropout linear filter, so that the low dropout linear regulator can respond well, and meanwhile, excessive current cannot be wasted, and the power consumption is saved.
Drawings
FIG. 1 is a schematic diagram of a conventional LDO;
FIG. 2 is a schematic structural diagram of an LDO according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a current sinking load circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a current sinking load circuit according to another embodiment of the present invention;
FIG. 5 is a graph illustrating the variation of load current ILOAD over time;
FIGS. 6a, 6b and 6c are schematic diagrams showing the change of ICS with time;
FIG. 7 is a graph illustrating the variation of load currents ILOAD, ICS and total load current (ILOAD + ICS) over time;
FIG. 8 is a waveform diagram of the first control signal and the second control signal in the long idle mode;
in the figure: 101-bandgap reference current; 102-an operational amplifier;
201-bandgap reference current; 202-an operational amplifier; 203-current sink load circuit; 204-load; 2031-an RC filter circuit.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, fig. 2 shows a schematic structural diagram of a low dropout regulator (LDO) provided in an embodiment of the present invention. The low dropout linear regulator comprises a current sinking load circuit, wherein the current sinking load circuit is connected in parallel with two ends of a load, one end of the load is connected with the output voltage of the low dropout linear regulator, and the other end of the load is grounded. Namely, one end of the current sink load circuit is also connected to the output voltage of the low dropout regulator, and the other end is grounded.
In an embodiment of the present invention, the low dropout linear regulator includes: a bandgap reference circuit 201, an amplifier 202, a twelfth MOS transistor M12, a second resistor R2, a third resistor R3, a first capacitor C1, and a current sinking load circuit 203. The output end of the bandgap reference circuit 201 is connected to the inverting input end of the amplifier 202, and provides the required bias voltage VREF for the low dropout regulator. The output end of the amplifier 202 is connected to the gate of the twelfth MOS transistor M12, the source of the twelfth MOS transistor M12 is connected to the second voltage VDD, the drain of the twelfth MOS transistor M12 is connected to one end of the second resistor R2, the other end of the second resistor R2 and one end of the third resistor R3 are connected in series to a third node, the other end of the third resistor R3 is grounded, the third node is connected to the non-inverting input end of the amplifier 202, one end of the first capacitor C1 is connected to the drain of the twelfth MOS transistor M12, and the other end of the first capacitor C1 is grounded. The current sinking load circuit 203 is connected in parallel to two ends of a load 204, one end of the load 204 is connected to the drain of the twelfth MOS transistor M12, and the other end is grounded. The output voltage of the drain M12 of the twelfth MOS transistor is the output voltage VOUT of the low dropout regulator.
The operational amplifier 202, the twelfth MOS transistor M12, the second resistor R2, and the third resistor R3 form an amplification feedback loop, and the amplification feedback loop stabilizes the output voltage VOUT of the low dropout linear regulator at VREF (1+ R2/R3). ILOAD in fig. 2 represents the current flowing through the load 204, i.e., the load current. The ICS is the current flowing through the current sink load circuit 203.
In other embodiments of the present invention, the low dropout linear regulator is not limited to the above-mentioned structure, and may be in other structures as long as the current sinking load circuit and the load of the low dropout linear regulator are ensured to be connected in parallel, so as to achieve the purpose of reducing the total load current frequency of the low dropout linear filter by using the current sinking load circuit.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a current sinking load circuit according to an embodiment of the present invention. The current sink load circuit 203 includes: an RC filter circuit 2031, a first resistor R1 and a first MOS transistor M1; the gate of the first MOS transistor M1 is connected to the output terminal of the RC filter circuit 2031, the source is connected to ground through the first resistor R1, and the drain is connected to the first voltage. The first voltage is an output voltage of the drain M12 of the twelfth MOS transistor, that is, an output voltage VOUT of the low dropout regulator.
Wherein the RC filter circuit 2031 comprises: a second MOS transistor M2, a third MOS transistor M3, a fourth resistor R4, a fifth MOS transistor M5, a fifth resistor R5, a seventh MOS transistor M7, a second capacitor C2, a third capacitor C3, a tenth MOS transistor M10, and an eleventh MOS transistor M11.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a current sinking load circuit according to an embodiment of the invention. The gate of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3, the source is connected to the second voltage VDD, one end of the fourth resistor R4 and the drain of the fifth MOS transistor M5 are connected to the drain of the second MOS transistor M2, and the other end of the fourth resistor R4 and the source of the fifth MOS transistor M5 are connected to a first node a; one end of the fifth resistor R5 and the source of the seventh MOS transistor M7 are connected to the first node a, the other end of the fifth resistor R5 and the drain of the seventh MOS transistor M7 are connected to the drain of the third MOS transistor M3, and the source of the third MOS transistor M3 is grounded; one end of the second capacitor C2 is connected to the second voltage VDD, the other end and one end of the third capacitor C3 are connected to a second node B, and the other end of the third capacitor C3 is connected to ground; the source of the tenth MOS transistor M10 is connected to the eleventh MOS transistor, the drain of M11 and the drain of M3526 are connected to the second node B, and the source of the eleventh MOS transistor M11 is connected to the second voltage VDD; the first node a and the second node B are connected to the gate of the first MOS transistor M1.
The first MOS transistor M1, the third MOS transistor M3, the seventh MOS transistor M7 and all the N-type MOS transistors are N-type MOS transistors. The second MOS transistor M2, the fifth MOS transistor M5, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are all P-type MOS transistors. Further, the fourth MOS transistor M4 and the sixth MOS transistor M6 are MOS resistors, and the eighth MOS transistor M8 and the ninth MOS transistor M9 are MOS capacitors.
The fourth capacitor R4 and the fifth resistor R5 may be MOS transistor resistors or polysilicon resistors. The second capacitor C2 and the third capacitor C3 may be MOS transistor capacitors or polysilicon capacitors, and are not described in detail herein.
Further, the fourth resistor R4 and the fifth resistor R5 may be resistors of the same type, for example, the fourth resistor R4 and the fifth resistor R5 may be MOS transistor resistors, polysilicon resistors, or other types of resistors. Similarly, the fourth resistor R4 and the fifth resistor R5 may be two different types of resistors, for example, the fourth resistor R4 is one type of resistor, and the fifth resistor R5 is another type of resistor. Further, for example, the fourth resistor R4 is a MOS transistor resistor, and the fifth resistor R5 is a polysilicon resistor. Alternatively, the fourth resistor R4 is a polysilicon resistor, and the fifth resistor R5 is a MOS transistor resistor.
When the fourth resistor R4 is a MOS transistor resistor, for example, the fourth resistor R4 is a fourth MOS transistor M4, the fourth MOS transistor M4 is a P-type MOS transistor. And the drain of the fourth MOS transistor M4 and the drain of the fifth MOS transistor M5 are connected to the drain of the second MOS transistor M2, the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are connected to the first node, and the gate of the fourth MOS transistor M4 is grounded.
When the fifth resistor R5 is a MOS transistor resistor, for example, the fifth resistor R5 is a sixth MOS transistor M6, the sixth MOS transistor M6 is an N-type MOS transistor. A source of the sixth MOS transistor M6 and a source of the seventh MOS transistor M7 are connected to the first node a, a drain of the sixth MOS transistor M6 and a drain of the seventh MOS transistor M7 are connected to a drain of the third MOS transistor M3, and a gate of the sixth MOS transistor M6 is connected to the second voltage VDD.
The second capacitor C2 and the third capacitor C3 may be MOS transistor capacitors, polysilicon capacitors, or other capacitors. The second capacitor C2 and the third capacitor C3 may be capacitors of the same form or different forms. For example, the second capacitor C2 and the third capacitor C3 may be both MOS transistor capacitors or polysilicon capacitors. Alternatively, the second capacitor C2 may be one type of capacitor, and the third capacitor C3 may be another type of capacitor. For example, the second capacitor C2 is a MOS transistor capacitor, and the third capacitor C3 is another type of capacitor, such as a polysilicon capacitor. Alternatively, the second capacitor C2 may be a polysilicon capacitor, and the third capacitor C3 may be a MOS transistor capacitor.
When the second capacitor C2 is a MOS transistor capacitor, such as an eighth MOS transistor M8, the eighth MOS transistor M8 is a P-type MOS transistor. Further, the source and the drain of the eighth MOS transistor M8 are turned on and connected to the second voltage VDD, and the gate is connected to the second node B.
When the third capacitor C3 is a MOS transistor capacitor, such as a ninth MOS transistor M9, the ninth MOS transistor M9 is an N-type MOS transistor. Further, the source and the drain of the ninth MOS transistor M9 are turned on and connected to ground, and the gate is connected to the second node B.
Fig. 4 is a schematic diagram showing a structure of a current sinking load circuit in still another embodiment of the present invention. At this time, the fourth resistor R4, the fifth resistor R5, the second capacitor C2 and the third capacitor C3 are all MOS transistors. The specific connection is shown in fig. 4.
The drain of the fourth MOS transistor M4 and the drain of the fifth MOS transistor M5 are connected to the drain of the second MOS transistor M2, the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are connected to the first node, and the gate of the fourth MOS transistor M4 is grounded. A source of the sixth MOS transistor M6 and a source of the seventh MOS transistor M7 are connected to the first node a, a drain of the sixth MOS transistor M6 and a drain of the seventh MOS transistor M7 are connected to a drain of the third MOS transistor M3, and a gate of the sixth MOS transistor M6 is connected to the second voltage VDD. The source and the drain of the eighth MOS transistor M8 are turned on and connected to the second voltage VDD, and the gate is connected to the second node B. The source and drain of the ninth MOS transistor M9 are turned on and connected to ground, and the gate is connected to the second node B.
A first control signal in1 is simultaneously input to the gate of the second MOS transistor M2, the gate of the third MOS transistor M3 and the gate of the tenth MOS transistor M10. A second control signal in2 is simultaneously inputted to the gate of the fifth MOS transistor M5 and the gate of the seventh MOS transistor M7. A flag _ longblank signal is input to the gate of the eleventh MOS transistor M11.
The first control signal in1 and the second control signal in2 are formed by some simple logic combinations, and the waveforms are shown in fig. 8, and fig. 8 shows the waveforms of the first control signal in1 and the second control signal in2 in the long idle mode according to the embodiment of the present invention. Hs _ en is a high-speed mode enable signal of the load 204, hs _ pre is an advance signal of the high-speed mode of the load 204, and generally he _ pre is earlier than hs _ en by Tre, wherein Tre should be longer than the response time of the LDO. Specifically, Tre > 1/(2 × pi × BW), BW is the response bandwidth of the low dropout regulator LDO, and 1/(2 × pi × BW) is the response time of the low dropout regulator LDO.
In2 ═ hs _ en | hs _ pre, In1 ═ hs _ en |, In2_ dealy, and In2_ dealy show waveforms delayed by a certain time In2, and In fig. 8 of the present embodiment show waveforms delayed by 5 ns. That is, the second control signal in2 is a calculation result of an or operation of the high speed mode enable signal hs _ en and a high speed mode advance signal hs _ pre, and the first control signal in1 is a calculation result of an or operation of the high speed mode enable signals hs _ en and in2_ default. And then sampling the high-speed mode enabling signal hs _ en by utilizing the rising edge of the high-speed mode enabling signal hs _ pre, and then inverting to obtain the identification signal flag _ longblank.
The load current ILOAD is time-varying, and its variation with time is shown in fig. 5. The load current ILOAD is large when the low dropout linear regulator is in a high speed mode (HS); the load current ILOAD is small when the low dropout linear regulator is in an idle mode (LP). When the low dropout regulator needs to switch between two modes, which is usually completed within one or two nanoseconds, the currently commonly used low dropout regulator LDO does not respond at all, and the current sink load circuit 203 is used to provide a current sink load, so that the change of the amplitude and the frequency of (ILOAD + ICS) are maintained within a certain range, especially the change of the frequency is maintained within a certain range, so that the low dropout regulator in the present scheme can have enough time to respond.
Specifically, the idle mode can be divided into three types according to the duration of the idle mode: a long idle mode (long idle mode), a medium idle mode (medium idle mode), and a short idle mode (short idle mode). The long idle mode means that the duration of the low power consumption mode is greater than 2 Tre, and the medium idle mode means that the duration of the low power consumption mode is less than 2 Tre and is greater than Tre. The short idle mode means that the low power mode lasts less than Tre. Wherein, Tre is larger than the response time of the low dropout regulator LDO, Tre > 1/(2 × pi × BW), BW is the response bandwidth of the low dropout regulator LDO, and 1/(2 × pi × BW) is the response time of the 1/(2 × pi × BW) LDO.
The time-varying form of the ICS is also different for the three different idle modes. Specifically, referring to FIG. 6a, FIG. 6b and FIG. 6c, FIG. 6a is a variation of ICS in long idle mode; FIG. 6b is a variation of ICS in medium idle mode; FIG. 6c is a variation of ICS in short idle mode. Variations of the ICS in these three modes can be achieved by adjusting the identification signal. When the flag _ longblank is 1, the low dropout linear regulator is in a long idle mode, the eleventh MOS transistor M11 is turned off, and the ICS is changed as shown in fig. 6 a. When the flag _ longblank is 0, the low dropout linear regulator is in the medium idle mode or the short idle mode, the eleventh MOS transistor M11 is turned on, and a variation of the ICS is shown in fig. 6b or fig. 6 c. Therefore, the amplitude and frequency of the total load current (ILOAD + ICS) can be maintained within a certain range, so that the low dropout regulator can respond well, excessive current cannot be wasted, and power consumption is saved. The total load current (ILOAD + ICS) as a function of time is shown in FIG. 7. As can be seen from the figure, the frequency of the total load current (ILOAD + ICS) of the low dropout linear regulator during mode switching is controlled within a certain range, so that the low dropout linear regulator has a certain response time.
For a specific working principle, refer to fig. 7. When the low dropout linear regulator is in the long idle mode, the flag _ longblank is 1, and as can be seen from fig. 7, when hs _ en changes from high to low, the first control signal in1 also changes from high to low, the second MOS transistor M2 is turned on, and the second control signal in2 is low at this time, so that the fifth MOS transistor M5 is turned on, the gate voltage of the first MOS transistor M1 is pulled high rapidly, so that the first MOS transistor M1 is turned on, and the current ICS is extracted from the drain of the first MOS transistor M1. After lasting about several nanoseconds, the first control signal in1 goes high, the second MOS transistor M2 is turned off, the third MOS transistor M3 is turned on, and the third MOS transistor M3 slowly discharges toward the second node B through the ninth MOS transistor M9, causing the voltage of the second node B to gradually decrease, so that the drain circuit ICS of the first MOS transistor M1 gradually decreases.
Further, when hs-pre goes from low to high, the first control signal in1 goes low, the second control signal in2 goes high, the second MOS transistor M2 is turned on, the third MOS transistor M3 is turned off, and the fifth MOS transistor M5 is turned off. The second MOS transistor M2 charges slowly to the second node B through the fourth MOS transistor M4, causing the voltage of the second node B to gradually increase, so that the current ICS at the drain of the first MOS transistor M1 gradually increases.
Further, when hs _ en is changed from low to high, the first control signal in2 is high, the second control signal in2 is low, the third MOS transistor M3 is turned on, the seventh MOS transistor M7 is turned on, the second MOS transistor M2 is turned off, and the third MOS transistor M3 is rapidly discharged to the second node B through the seventh MOS transistor M7, resulting in a rapid decrease in the voltage of the second node B, so that the ICS current at the drain of the first MOS transistor M1 is 0.
When the low dropout linear regulator is in the medium idle mode, the flag _ longblank is 1, which is shown in fig. 7. The operation principle is the same as that of the low dropout linear regulator in the long idle mode, and the difference is that the time that hs _ en is 0 is short, the current ICS at the drain of the first MOS transistor M1 gradually rises as soon as it falls to 0.
When the low dropout linear regulator is in a short idle mode, the flag _ longblank is 0, the second control signal in2 is high, i.e., in2 is 1, when hs _ en changes from high to low, the first control signal also changes from high to low, the second MOS transistor M2 is turned on, the tenth MOS transistor M10 is turned on, the eleventh MOS transistor M11 is turned on, the tenth MOS transistor M10 and the eleventh MOS transistor M11 charge the second node quickly, and the first MOS transistor M1 is turned on. When hs _ en is changed from low to high, the first control signal in1 goes high, the third MOS transistor M3 is turned on, the seventh MOS transistor M7 is turned on, the second MOS transistor M2 is turned off, the tenth MOS transistor M10 is turned off, and the third MOS transistor M3 is rapidly discharged to the second node B through the seventh MOS transistor M7, causing the voltage of the second node B to rapidly decrease, so that the drain current ICS of the first MOS transistor M1 becomes 0.
In summary, in the current sinking load circuit and the low dropout regulator provided in the embodiments of the present invention, when the low dropout linear filter is performing mode switching, the current sinking load circuit is used to reduce the frequency of the total load current of the low dropout linear filter, so that the low dropout linear regulator can respond well, and at the same time, excessive current is not wasted, and power consumption is saved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A current sinking load circuit, wherein the current sinking load circuit is connected in parallel across a load in a low dropout linear regulator, the current sinking load circuit comprising: an RC filter circuit, a first resistor and a first MOS transistor; the grid electrode of the first MOS transistor is connected to the output end of the RC filter circuit, the source electrode of the first MOS transistor is grounded through the first resistor, and the drain electrode of the first MOS transistor is connected to the output end of the low dropout linear regulator;
the RC filter circuit includes: a second MOS transistor, a third MOS transistor, a fifth MOS transistor, a seventh MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, two resistors and two capacitors;
the grid electrode of the second MOS transistor is connected with the grid electrode of the third MOS transistor, the source electrode of the second MOS transistor is connected with a second voltage, and the drain electrode of the second MOS transistor is connected with the drain electrode of the fifth MOS transistor; the source electrode of the third transistor is grounded, and the drain electrode of the third transistor is connected to the drain electrode of the seventh transistor; the source electrode of the fifth MOS transistor and the source electrode of the seventh MOS transistor are connected to a first node;
the source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor, the drain of the tenth MOS transistor is connected to a second node, and the source of the eleventh MOS transistor is connected to the second voltage;
the first node and the second node are connected to the grid electrode of the first MOS transistor;
a resistor is connected in parallel to two ends of the source and the drain of the fifth MOS transistor, another resistor is connected in parallel to two ends of the source and the drain of the seventh MOS transistor, one end of a capacitor is connected to the second node, the other end of the capacitor is connected to the second voltage, one end of another capacitor is connected to the second node, and the other end of the another capacitor is grounded;
a first control signal is simultaneously input to the grid electrode of the second MOS transistor, the grid electrode of the third MOS transistor and the grid electrode of the tenth MOS transistor; a second control signal is simultaneously input to the grid electrode of the fifth MOS transistor and the grid electrode of the seventh MOS transistor; a grid electrode of the eleventh MOS transistor inputs an identification signal; the second control signal is a calculation result of performing an or operation on a high-speed mode enable signal of the load and a high-speed mode advance signal of the load, the first control signal is a calculation result of performing an or operation on the high-speed mode enable signal and a delay signal of the second control signal, the high-speed mode enable signal is sampled by using a rising edge of the high-speed mode advance signal and then inverted to obtain the identification signal, wherein the high-speed mode advance signal is earlier than the high-speed mode enable signal by a predetermined time, the predetermined time is greater than the reaction time of the low dropout linear regulator, and the delay signal of the second control signal is delayed by a certain time than the second control signal.
2. The current sink load circuit according to claim 1, wherein the two resistors and the two capacitors are respectively: a fourth resistor, a fifth resistor, a second capacitor and a third capacitor;
one end of the fourth resistor is connected to the drain of the second MOS transistor, and the other end of the fourth resistor is connected to the first node;
one end of the fifth resistor is connected to the first node, and the other end of the fifth resistor is connected to the drain electrode of the third MOS transistor;
one end of the second capacitor is connected to the second voltage, the other end of the second capacitor and one end of the third capacitor are connected to a second node, and the other end of the third capacitor is grounded.
3. The current sink load circuit according to claim 2, wherein the fourth resistor and/or the fifth resistor is a MOS transistor; wherein,
when the fourth resistor is a fourth MOS transistor, a drain of the fourth MOS transistor and a drain of the fifth MOS transistor are connected to a drain of the second MOS transistor, a source of the fourth MOS transistor and a source of the fifth MOS transistor are connected to the first node, and a gate of the fourth MOS transistor is grounded;
when the fifth resistor is a sixth MOS transistor, the source of the sixth MOS transistor and the source of the seventh MOS transistor are connected to the first node, the drain of the sixth MOS transistor and the drain of the seventh MOS transistor are connected to the drain of the third MOS transistor, and the gate of the sixth MOS transistor is connected to the second voltage.
4. The current sink load circuit according to claim 2, wherein the second capacitor and/or the third capacitor is a MOS transistor; wherein,
when the second capacitor is an eighth MOS transistor, the source and the drain of the eighth MOS transistor are turned on and connected to the second voltage, and the gate is connected to the second node;
when the third capacitor is a ninth MOS transistor, the source and the drain of the ninth MOS transistor are turned on and connected to ground, and the gate is connected to the second node.
5. The current sink load circuit according to claim 2, wherein the second MOS transistor, the fifth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are P-type MOS transistors; the first MOS transistor, the third MOS transistor and the seventh MOS transistor are all N-type MOS transistors.
6. A low dropout linear regulator comprising: a current sinking load circuit as claimed in any one of claims 1 to 5 connected in parallel across a load, the load having one terminal connected to the output voltage of the low dropout linear regulator and the other terminal connected to ground.
7. The low dropout regulator of claim 6, further comprising: a bandgap reference circuit, an amplifier, a twelfth MOS transistor, a second resistor, a third resistor, and a first capacitor, wherein an output terminal of the bandgap reference circuit is connected to an inverting input terminal of the amplifier, an output terminal of the amplifier is connected to a gate of the twelfth MOS transistor, a source of the twelfth MOS transistor is connected to a second voltage, a drain of the twelfth MOS transistor is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are connected in series to a third node, the other end of the third resistor is grounded, the third node is connected to a non-inverting input terminal of the amplifier, one end of the first capacitor is connected to a drain of the twelfth MOS transistor M12, and the other end of the first capacitor is connected to ground; one end of the load is connected with the drain electrode of the twelfth MOS transistor, and the output voltage of the drain electrode of the twelfth MOS transistor is the output voltage of the low dropout linear regulator.
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| CN107678480A (en) * | 2017-11-13 | 2018-02-09 | 常州欣盛微结构电子有限公司 | A kind of linear voltage manager for low-power consumption digital circuit |
| CN110187733B (en) * | 2019-06-20 | 2024-03-12 | 江苏润石科技有限公司 | Low-dropout linear voltage stabilizer capable of eliminating early phenomenon |
| US10866607B1 (en) | 2019-12-17 | 2020-12-15 | Analog Devices International Unlimited Company | Voltage regulator circuit with correction loop |
| CN115202427B (en) * | 2021-04-09 | 2023-12-12 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN115469706B (en) * | 2022-09-06 | 2024-02-09 | 北京空间机电研究所 | Low dropout voltage regulator |
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| CN101398694A (en) * | 2007-09-30 | 2009-04-01 | Nxp股份有限公司 | Non-capacitance low voltage difference constant voltage regulator with rapid excess voltage response |
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| CN101398694A (en) * | 2007-09-30 | 2009-04-01 | Nxp股份有限公司 | Non-capacitance low voltage difference constant voltage regulator with rapid excess voltage response |
| CN102868299A (en) * | 2011-07-05 | 2013-01-09 | 盛群半导体股份有限公司 | Low-voltage-drop voltage stabilizer without externally-hung voltage stabilizing capacitor and voltage stabilizing method thereof |
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