CN106199394A

CN106199394A - RAM chip engineering detecting method based on FPGA

Info

Publication number: CN106199394A
Application number: CN201610595507.5A
Authority: CN
Inventors: 尚娟; 王冬华
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2016-07-26
Filing date: 2016-07-26
Publication date: 2016-12-07

Abstract

The invention discloses a kind of RAM chip engineering detecting method based on FPGA.Being frequently found during PCB debugs, the reading and writing data mistake of high integration Large Copacity RAM memory module is to be caused by faults such as data/address bus and the short circuit of address bus, dry joint, rosin joints.When RAM is directly controlled by FPGA, quick diagnosis and location is carried out for this type of fault, the diagnostics routines of RAM is generated by programmable device FPGA, use specific test data that data wire and address wire are scanned diagnosis, utilize on-line debugging software Chipscope instrument to carry out device function confirmation and fault location.The present invention first completes the diagnosis of scans of data/address bus, then completes the diagnosis of scans of address bus.Main method is to carry out particular data test for data/address bus, carries out the two way classification readwrite tests of address wire for address bus.

Description

RAM chip engineering detecting method based on FPGA

Technical field

The invention belongs to the on-line testing technique field of device, examine particularly to a kind of RAM chip engineering based on FPGA Survey method, it is achieved the location abnormal to chip Denso fault and pin.

Background technology

Along with the scale of digital circuit and being continuously increased of complexity, the packaged type small of electric appliance component, number Word Circuit Measurement Technology becomes an important link in digital circuit industrial chain, and the testing cost of digital circuit accounts for whole The proportion of research and development of products funds is the most increasing.

Common digital circuit failure mainly has bad, the own damage of components and parts of components and parts pins contact etc., thus causes There is logical error in digital circuit, and fault occurs.And the jumbo RAM chip of high integration is due to data, address bus Pin is more, BGA package foot not Easy Test, if there are the situations such as Denso exception, quick and precisely fault point seems the heaviest Want.The most conventional diagnostic method has: visual inspection method, sequence detection method, relative method, substitution method, wave detection etc., but on State diagnostic method and there is problems such as diagnosing, location efficiency is low.

The present invention proposes a kind of RAM chip engineering detecting method based on FPGA, decreases for auxiliary than additive method The dependency of assistant engineer's tool, simultaneously effective improves Method for Digital Logic Circuit Fault Diagnosis ability.Additionally the cross-species transferability of the present invention is big Reduce greatly the test period of Mass storage module.

Summary of the invention

The present invention proposes a kind of RAM chip engineering detecting method based on FPGA, it is adaptable to RAM chip data and address are total The quick diagnosis that the Denso faults such as the short circuit of line I/O pin, dry joint, rosin joint or part I/O pin self damage.Main passing through can Programming device FPGA generates the diagnostics routines of RAM, uses and specifically tests data, M-bit data line and the N bit address line to RAM Being scanned diagnosis, the on-line debugging software Chipscope instrument utilizing ISE to carry carries out accident analysis to RAM.At a base In the system that FPGA controls, address bus belongs to unidirectional output IO for FPGA, and data/address bus then belongs to two-way IO, when When RAM portion pin exists the faults such as short circuit, dry joint, rosin joint, the respective pin of address bus and data/address bus is fixed to height Level or low level, on the premise of address bus breaks down, using the write of individual data to read method of testing again will not The impact fault detect to data/address bus, after the detection of complete paired data bus, recycling failure-free data position is total to address Line carries out fault detect.The present invention utilizes above-mentioned characteristic, first completes the diagnosis of scans of data/address bus, then completes sweeping of address bus Retouch diagnosis.Main method is to carry out particular data test for data/address bus, carries out memory element two way classification reading for address wire Write test.

Accompanying drawing illustrates:

Fig. 1 hardware composition frame chart.

Fig. 2 data wire testing process schematic diagram.

Fig. 3 address wire testing process schematic diagram.

Detailed description of the invention:

This technological invention realizes based on FPGA, when, after system electrification to be measured, programmable device FPGA load fault detects journey Sequence.After pending fault program loaded, implement corresponding testing procedure, complete the detection abnormal to RAM Denso fault and pin. Hardware composition frame chart is as shown in Figure 1.It is as follows that the present invention realizes step:

1, the diagnosis of scans of data/address bus

(1) test data are determined.Preparing two groups of test data, each data bit low and high level each other in two groups, with 32 As a example by position datawire, first group of test data can be: 0xAAAAAAAA, and binary system is: 10101010101010101010101010101010, then second group of test data is: 0x55555555, and binary system is: 01010101010101010101010101010101.When data wire is M position, test data should be designed as a example by 32 Same form.

(2) data compare and diagnose.Utilize Chipscope that the two groups of test data read are compared, if the read out Two groups of data under binary form 0,1 relatively, data bit is the most misaligned, then the data wire fault-free of RAM, if two groups There is a certain position or the situation of a few bit data position coincidence in data under binary form, then the data wire of RAM exists fault, and Location of fault is the part overlapped.Schematic flow sheet is as shown in Figure 2.

(3) reject the data bit broken down, remaining data position is defined as new data/address bus, for address ram The fault detect of position.

2, the diagnosis of scans of address bus

(1) by two points of the N bit address line of RAM to be measured, the memory space of RAM equal two parts will be divided into.By height N/2 position is fixed as 0 as high address, low N/2 bit address, utilizes the test number that FPGA is incremented by the write of the address of combinations thereof According to 0～2^N/2-1, after traversal write completes, recycle Chipscope sequential read out by writing address；Using low N/2 position as low Bit address, high N/2 bit address are fixed as 0, repeat aforesaid operations.

(2) data judge.If there is non-staged output result as shown in Figure 3 in the data utilizing Chipscope to read, Address bit pointed by explanation has exception.

(3) packet test is continued.The N/2 bit address line that will appear from mistake is divided into high N/4 position and low N/4 position, repeats above-mentioned Step (1), the operation of step (2).

(4) utilize the operation of step 1, step 2, step 3, each address bit broken down may finally be navigated to, Thus realize fail address line is accurately positioned.Use two way classification test philosophy, abnormal address will occur in test every time Line is divided into high N/2n position and low N/2n position, and wherein n is integer, and n > 2.Until determining a certain position of data wire or several appearance Fault, the diagnosis of complete paired data line.

(5) quantity of the N bit address position of RAM to be measured is if not the power of 2, equally uses the thought of two way classification in fact Existing, do not affect diagnostic analysis.

Claims

1. RAM chip engineering detecting method based on FPGA, it is possible to quick diagnosis RAM memory module whether exist Denso fault and Pin exception also positions fault pin, it is characterised in that:

Step 1: complete the diagnosis of scans of RAM data line: specific for data bit test of the fixing address of RAM chip write Data, thus realize the accident analysis to RAM data position；

Step 2: complete the diagnosis of scans of address ram line: by address wire two points, i.e. divide RAM memory space, is dividing After memory space in write incremental test data, according still further to write sequence of addresses read test data, the test of reading Data are shown by Chipscope, judge that address wire is the most faulty according to display result, continue out of order address area Two points, until locking abort situation.

RAM chip engineering detecting method based on FPGA the most according to claim 1, it is characterised in that described step 1 is wrapped Include:

1. determining test data, test data are two groups, each data bit low and high level each other in two groups；

2. test result is analyzed, does not occurs 0, the fault bit that data bit is data/address bus of 1 change；

3. fault bit is by disallowable.

3. according to the RAM chip engineering detecting method based on FPGA described in claim 1 or claim 2, it is characterised in that Described step 2 includes:

1. utilizing the test data that FPGA is incremented by the write of the address of Combination nova, wherein data/address bus is the data fixed a breakdown Position；

2. utilize two way classification that RAM memory space is divided, until locking all address bus causing abnormal conditions to produce On abort situation.