CN106158958B - FinFET with source/drain overlay - Google Patents

Abstract

A kind of device includes semiconductor substrate and extends to isolated area in semiconductor substrate.Semiconductor fin is located between the opposite segments of isolated area, wherein semiconductor fin is located at the top face of isolated area.Gate stack is Chong Die with semiconductor fin.Source/drain regions are located on the side of gate stack and are connected to semiconductor fin.Source/drain regions include the outside of the inside and internally positioned outside thinner than semiconductor fin.The component of the inside of semiconductor fin and source/drain regions IV race semiconductor having the same.The invention further relates to the FinFET with source/drain coating.

Description

FinFET with source/drain overlay

Priority Statements and Cross-References

This application is related to the following commonly assigned US Patent Application Serial No. 14/451,503, filed August 5, 2014, entitled "Nonplanar Device and Strain-Generating Channel Dielectric," the entire contents of which are incorporated herein by reference.

technical field

The present invention relates to integrated circuit devices, and more particularly, to FinFETs with source/drain capping layers.

Background technique

Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest feature (or line) that can be fabricated using a fabrication process) has decreased. This scale-down process generally provides benefits by increasing production efficiency and reducing associated costs.

This scaling down also increases the complexity of processing and manufacturing ICs, and further developments in IC processing and manufacturing are also required in order to continue to achieve these advances. For example, three-dimensional transistors such as fin field effect transistors (FinFETs) have been introduced to replace planar transistors. While existing FinFET devices and methods of making them have generally served their intended purpose, they have not been fully satisfactory in all respects. Improvements in this area are expected.

SUMMARY OF THE INVENTION

In order to solve the problems existing in the prior art, the present invention provides a device, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin located between opposite parts of the isolation region, wherein the semiconductor fins are located above the top surfaces of the isolation regions; a gate stack overlaps the semiconductor fins; and source/drain regions are located on sides of the gate stack and connected to The semiconductor fin, wherein the source/drain region includes an interior thinner than the semiconductor fin, wherein the interior of the semiconductor fin and the source/drain region have the same Group IV a component of a semiconductor; and an exterior, located outside the interior.

In the above device, wherein a top surface of the interior is lower than a top surface of the semiconductor fin.

In the above device, wherein the first width of the interior of the source/drain region is about 50% to about 70% of the second width of the semiconductor fin, wherein the source/drain region includes the source The first width and the second width are measured in a direction perpendicular to the source-to-drain direction of the fin field effect transistor (FinFET) in the /drain region.

In the above device, wherein the gate stack and the source/drain regions are included in an n-type fin field effect transistor (FinFET), and the interior includes silicon and is free of germanium, and wherein, The outer portion includes silicon phosphorus.

In the above device, wherein the gate stack and the source/drain regions are included in an n-type fin field effect transistor (FinFET), and the interior includes silicon and is free of germanium, and wherein, The outer portion includes silicon phosphorus, wherein the device further includes: two _SiGeOx regions, wherein the inner portion of the _SiGeOx regions overlaps the semiconductor fin.

In the above device, wherein the gate stack and the source/drain regions are included in an n-type fin field effect transistor (FinFET), and the interior includes silicon and is free of germanium, and wherein, The outer portion includes silicon phosphorus, wherein the device further includes: two SiGeO _x regions, wherein the inner portion of the SiGeO _x region overlaps the semiconductor fin, wherein the device further includes: a silicon germanium region located in between the two SiGeO _x regions.

In the above device, wherein the gate stack and the source/drain regions are included in a p-type fin field effect transistor (FinFET), and the interior includes silicon germanium having a first germanium percentage, And the outer portion includes silicon germanium having a second germanium percentage greater than the first germanium percentage.

In the above device, wherein the gate stack and the source/drain regions are included in a p-type fin field effect transistor (FinFET), and the interior includes silicon germanium having a first germanium percentage, and the outer portion includes silicon germanium having a second germanium percentage greater than the first germanium percentage, wherein the device further includes: a silicon layer underlying the inner portion of the source/drain regions; and an additional A silicon germanium layer under the silicon layer and over the semiconductor substrate.

According to another embodiment of the present invention, there is provided a device comprising: a silicon substrate; an isolation region extending into the silicon substrate; and a p-type fin field effect transistor (FinFET) comprising: a silicon germanium fin , the silicon germanium fin includes a middle portion and ends on opposite sides of the middle portion, wherein a top surface of the middle portion is higher than a top surface of the end portion, and wherein the silicon germanium a fin having a first germanium percentage; a gate stack overlapping the middle portion of the silicon germanium fin; and a source/drain region including as interior one of the ends of the silicon germanium fin and a silicon germanium region on the inner outer side, wherein the silicon germanium region has a second germanium percentage higher than the first germanium percentage.

In the above device, wherein the source/drain regions further comprise additional silicon germanium regions outside the silicon germanium regions, wherein the additional silicon germanium regions have a third germanium percentage higher than the second germanium Germanium percentage.

In the above device, wherein the silicon germanium fin extends to a level lower than the top surface of the isolation region, and the device further comprises: a silicon layer located under the silicon germanium fin; an additional silicon germanium layer located on the under the silicon layer; and a silicon strip under the additional silicon germanium layer, wherein the silicon strip is continuously connected to the silicon substrate.

In the above device, wherein the end portions of the silicon germanium fins are thinner than the middle portions of the silicon germanium fins.

In the above device, wherein the ends of the silicon germanium fins are thinner than the middle portions of the silicon germanium fins, wherein the ends of the silicon germanium fins have a first width that is smaller than the silicon germanium fins a second width of the middle portion of a germanium fin, wherein the first is measured in a direction perpendicular to a source-to-drain direction of a fin field effect transistor (FinFET) including the source/drain regions width and the second width.

In the above device, wherein the ends of the silicon germanium fins are thinner than the middle portions of the silicon germanium fins, wherein the ends of the silicon germanium fins have a first width that is smaller than the silicon germanium fins a second width of the middle portion of a germanium fin, wherein the first is measured in a direction perpendicular to a source-to-drain direction of a fin field effect transistor (FinFET) including the source/drain regions a width and the second width, wherein the first width is between about 50% and about 70% of the second width.

According to yet another embodiment of the present invention, there is provided a method comprising recessing isolation regions on opposite sides of a semiconductor strip to form semiconductor fins, wherein the semiconductor fins are located over top surfaces of the isolation regions ; forming gate stacks on top surfaces and sidewalls of intermediate portions of the semiconductor fins; thinning the ends of the semiconductor fins; and performing epitaxy to grow semiconductor on the thinned ends of the semiconductor fins region, wherein the thinned end of the semiconductor fin and the semiconductor region combine to form source/drain regions of a fin field effect transistor (FinFET).

In the above method, wherein the thinning is performed after forming the gate stack.

In the above method, wherein the FinFET is an n-type FinFET and the semiconductor fin is a germanium-free silicon fin, and wherein the epitaxy includes growing a silicon phosphorous region.

In the above method, wherein the semiconductor strip includes a silicon strip overlapping a silicon germanium strip, and the method further comprises: oxidizing the outside of the silicon germanium strip, wherein in the oxidation, the silicon The germanium is concentrated in the interior of the germanium bar.

In the above method, wherein the FinFET is a p-type FinFET and the semiconductor fin includes a silicon germanium fin having a first germanium percentage, and wherein the epitaxy includes growing a second germanium fin having a higher germanium percentage than the first germanium percentage Two germanium percent silicon germanium boron regions.

In the above method, wherein the FinFET is a p-type FinFET and the semiconductor fin includes a silicon germanium fin having a first germanium percentage, and wherein the epitaxy includes growing a second germanium fin having a higher germanium percentage than the first germanium percentage A two germanium percent silicon germanium boron region, further comprising, prior to recessing the isolation regions: etching the tops of the silicon strips between the isolation regions to form recesses; and growing silicon in the recesses A germanium strip, the silicon germanium strip being grown from the bottom of the silicon strip, wherein the silicon germanium strip has the first germanium percentage.

Description of drawings

Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1-4A, 5-10A, and 11-12A are perspective views at intermediate stages in the fabrication of exemplary fin field effect transistors (FinFETs), while FIGS. 4B, 10B, and 12B-12C is a cross-sectional view at an intermediate stage in the fabrication of an exemplary Fin Field Effect Transistor (FinFET).

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming a first part over or on a second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include an embodiment that may be formed between the first part and the second part Additional parts so that the first part and the second part may not be in direct contact with one embodiment. Furthermore, the present disclosure may repeat reference numerals and/or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe what is shown in the figures. The relationship of one element or part to another (or other) elements or parts. In addition to the orientation shown in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Before discussing the illustrated embodiments, features and aspects of the invention will be discussed in general. In general, but not limited to, the present invention relates to complementary metal oxide semiconductor (CMOS) devices including P-type metal oxide semiconductor (PMOS) FinFET devices and N-type metal oxide semiconductor (NMOS) FinFET devices. Methods of forming CMOS devices are provided in accordance with various exemplary embodiments. Intermediate stages of forming exemplary FinFETs are shown and discussed, including variations of embodiments. The same reference numerals are used to refer to the same elements throughout the various views and illustrative embodiments.

FIG. 1 shows a wafer 10 including a substrate 20 and semiconductor layers 22 and 24 overlying the substrate 20 . According to some embodiments, substrate 20 includes crystalline silicon and may be free of germanium. In some embodiments, wafer 10 is a bulk monocrystalline semiconductor wafer. In other embodiments, wafer 10 comprises a silicon-on-insulator (SOI) wafer as known in the art. The semiconductor layer 22 includes silicon germanium (SiGe). According to some embodiments of the present invention, the percentage of germanium in semiconductor layer 22 is in the range of about 30% and about 80%. The thickness of the semiconductor layer 22 may be in the range of about 20 nm and about 90 nm. According to some embodiments, semiconductor layer 24 may be a germanium-free silicon layer. In alternative embodiments, the semiconductor layer 24 may include silicon phosphorus (SiP).

Wafer 10 includes illustrative regions 100 and 200 . Region 100 is an n-type FinFET region in which n-type FinFETs will be formed. Region 200 is a p-type FinFET region in which p-type FinFETs will be formed. Although the figures throughout this disclosure show regions 100 and 200 as being separated from each other, regions 100 and 200 are part of the same wafer 10 and may be located in the same chip. For example, substrate 20 shown in regions 100 and 200 is part of the same continuous substrate, and semiconductor layers 22 and 24 are also part of the same continuous layer.

Referring to FIG. 2 , layers 22 and 24 are subjected to a patterning process to form a plurality of trenches 26 extending into wafer 10 . Trenches 26 define semiconductor substrate 20 and some unpatterned portions of semiconductor layers 22 and 24 as a plurality of semiconductor strips 128 and 228 located in regions 100 and 200, respectively. The semiconductor strips 128 include portions 120 of the patterned substrate 20 , portions 122 of the patterned semiconductor layer 22 , and portions 124 of the patterned semiconductor layer 24 . The semiconductor strip 228 includes a portion 220 of the patterned substrate 20 , a portion 222 of the patterned semiconductor layer 22 , and a portion 224 of the patterned semiconductor layer 24 . According to some embodiments, semiconductor strips 128 and 228 have respective widths of between about 4 nm and about 10 nm. Throughout the specification, strips 120, 220, 124, and 224 are referred to as silicon strips, while strips 122 and 222 are referred to as SiGe strips.

FIG. 3 shows the formation of hard mask 30 and the subsequent oxidation process. As shown in FIG. 3 , hard mask 30 is formed on the top surfaces and sidewalls of semiconductor strips 128 and 228 and covers the exposed top surfaces of semiconductor substrate 20 (ie, the respective bottoms of trenches 26 ). Further, a hard mask 30 is formed in the n-type FinFET region 100 and the p-type FinFET region 200 . Next, a patterning process is performed to remove portions of the hard mask 30 from the middle portions of the semiconductor strips 128 . Portions of hardmask 30 on opposite ends of semiconductor strips 128 remain intact. Additionally, portions of hard mask 30 in p-type FinFET region 200 are not patterned. As shown in FIG. 3 , the entire fin 228 in the area 200 is covered, but the middle portion of the fin 128 in the area 100 is uncovered.

The hard mask 30 is formed as a conformal layer having horizontal portions and vertical portions whose thicknesses are relatively close to each other. According to some embodiments, hard mask 30 includes silicon nitride, silicon carbide, silicon oxynitride, titanium nitride, tantalum nitride, or other materials with high etch selectivity relative to semiconductor strips 128 and 228 and relative to silicon oxide.

Next, oxidation is performed such that the middle portions of SiGe strips 122 ( FIG. 2 ) not covered by hard mask 30 are oxidized to form silicon germanium oxide (SiGeO _x ) regions 132 . The ends of the SiGe strips 222 and, more particularly, the SiGe strips 122 are protected by the hard mask 30 and are therefore not oxidized. After oxidation, hard mask 30 is removed and the resulting structure is shown in FIG. 4A , which shows SiGeO _x region 132 in the middle of semiconductor strip 128 .

Figure 4B shows a cross-sectional view of one of the strips 128, where the cross-sectional view is taken from the vertical plane containing the line 4B-4B in Figure 4A. A single semiconductor strip 128 is shown for clarity. As shown in Figure 4B, the interior of the SiGe strips 122 remains unoxidized. The middle portions of silicon strips 120 and 124 that are not covered by hardmask 30 (FIG. 3) may also be partially oxidized. However, the oxidation rate of the middle portion of SiGe strip 122 is much higher (sometimes 30 times higher) than that of silicon strips 120 and 124 . The resulting oxide (not shown) on the surfaces of the silicon strips 120 and 124 is therefore very thin (which may have less than about approx. thickness), and are therefore not shown here. Oxidation may be performed, for example, by furnace oxidation, eg, by exposing wafer 10 to an oxygen atmosphere having an oxidation temperature between about 400°C and about 600°C. The duration of the oxidation process may range from about 20 minutes to about 40 minutes. The duration of the oxidation process depends on the temperature. Lower temperatures require longer durations of oxidation and vice versa. Alternatively, the oxidation can be carried out using chemical oxidation methods at low temperatures (eg, between about 20°C and 80°C), eg, using a _hydrogen peroxide (H2O2 ₎ solution as the oxidant. The resulting SiGeO _x region 132 may include two portions formed on opposite sides of the remaining SiGe strips 122 . According to some embodiments, SiGeO _x region 132 has a corresponding thickness of between about 3 nm and about 10 nm.

While expected to be bound by any particular theory below, it is believed that during the oxidation process, germanium atoms in the SiGe strips 122 tend to migrate inward from the _SiGeOx regions 132 and towards the center (interior) of the corresponding SiGe strip 122, This results in the concentration of germanium in the interior of the SiGe strips 122 . As a result, the remaining portion (ie, the unoxidized portion) of SiGe strip 122 has a higher germanium concentration than the corresponding germanium concentration in SiGe strip 222 (FIG. 4A).

Due to the oxidation process, the volume of the _SiGeOx regions 132 expands to be larger than the volume of the portion of the SiGe strips 122 from which the _SiGeOx regions 132 are generated. Thus, the expansion of the material results in the creation of lateral tensile strain to drive the source/drain regions 154 (FIG. 12A) apart from each other. Vertical strain is also generated to push up the silicon strips 124 that will be used to form the channel of the resulting n-type FinFET. Thus, oxidation of the SiGe strips 122 advantageously results in the creation of the desired strain in the resulting n-type FinFET. Instead, the SiGe strips 222 in the region 200 are masked to prevent undesired strain from forming in the resulting p-type FinFET.

5, dielectric pads 134 and 234 are formed on the top surfaces and sidewalls of semiconductor strips 128 and 228, respectively. In addition, dielectric liners 134 and 234 extend onto and contact the sidewalls of _SiGeOx region 132 (FIG. 4A ₎ . According to some embodiments of the present invention, dielectric liners 134 and 234 are formed of silicon nitride, aluminum oxide (Al ₂ O ₃ ), silicon oxynitride, silicon carbide, combinations thereof, or multiple layers thereof. In some embodiments, for example, dielectric liners 134 and 234 may be formed simultaneously in regions 100 and 200 using the same process and materials. Dielectric liners 134 and 234 are formed as conformal layers having vertical and horizontal portions having thicknesses that are equal to or substantially close to each other (eg, with a thickness difference of less than about 20%). The thickness of the dielectric liners 134 and 234 may be in the range of about 2 nm and about 6 nm.

Next, isolation regions are formed in trenches 26 in regions 100 and 200 . The resulting isolation regions 136 and 236 are shown in FIG. 6 and are also referred to as shallow trench isolation (STI) regions 136 and 236 throughout the specification. In the formation of STI regions 136 and 236, trench 26 is first filled with a dielectric material (FIG. 5). For example, the dielectric material may be formed using a method selected from spin coating, flowable chemical vapor deposition (FCVD), and the like. Dielectric materials may include highly flowable materials as known in the art. According to an alternative embodiment, the dielectric material is deposited using deposition methods such as High Density Plasma Chemical Vapor Deposition (HDPCVD) and High Aspect Ratio Process (HARP).

In some embodiments, an annealing step may then be performed on wafer 10, thereby curing the dielectric material. For example, the annealing may include steam annealing using in-situ steam generation (ISSG), wherein a combined gas of hydrogen ( _H2 ) and oxygen ( _O2 ) is used to generate the steam.

After the dielectric material is formed, chemical mechanical polishing (CMP) is performed to remove excess portions of the dielectric material over the top surface portions of the dielectric pads 134 and 234 , and thus form the STI regions 136 and 236 . According to some embodiments of the present invention, the top surface portions of dielectric liners 134 and 234 serve as CMP stop layers. The remainder of the dielectric material forms STI regions 136 and 236 . For example, STI regions 136 and 236 may comprise silicon oxide, although other dielectric materials may also be used. The top surfaces of STI regions 136 and 236 may be substantially flush with each other and with the top surfaces of dielectric liners 134 and 234 .

Referring also to FIG. 6, a hard mask 138 is formed and patterned. In the illustrated embodiment, the structures in the n-type FinFET region 100 are covered by the hard mask 138 and the structures in the p-type FinFET region 200 are exposed. In FIG. 6 and subsequent figures, in order to show additional hidden components, some portions of preceding components, such as STI regions 136 and 236, are omitted from the figures so that additional components may be shown. It will be understood that omitted portions of these components still exist. According to some embodiments of the present invention, hard mask 138 is formed of silicon nitride, silicon oxide, or other suitable material. Furthermore, in some embodiments, hard mask 138 may be formed of a different material than that of dielectric liners 134 and 234 , such that dielectric liners 134 and 234 may be etched without etching hard mask 138 ,vice versa.

FIG. 7 shows the indentation of the silicon strips 224 , thus forming grooves 240 in the region 200 . As an example, the etching may be performed using wet etching such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). According to some embodiments of the present invention, the etching is stopped before the SiGe strips 222 are exposed. Therefore, the bottoms of the silicon strips 224 still cover the SiGe strips 222 after etching. It should be understood that while the remaining silicon strips 224 are shown as having a flat top surface, in alternative embodiments, the top surface may also form a V-shape. According to other embodiments, after the etching, the silicon strips 224 are removed, and the SiGe strips 222 are exposed. Hardmask 138 ensures that strips 128 are not etched during this process.

Next, as shown in FIG. 8, SiGe strips 242 are epitaxially grown in the grooves 240 (FIG. 7). Thus, SiGe strips 242 are grown over and in contact with silicon strips 224 or SiGe strips 222, depending on the embodiment. According to some embodiments of the present invention, the SiGe strips 242 have a first germanium (atomic) percentage in a range between about 30% and about 50%. SiGe can be epitaxially grown to be flush with the top surface of STI region 236 , or can be grown to a level higher than the top surface of STI region 236 , and then a CMP process is used to planarize the top surface of SiGe and the top surface of STI region 236 . The remainder of the epitaxially grown SiGe material forms SiGe strips 242 .

Next, hard mask 138 is removed, and STI regions 136 and 236 are subsequently recessed. The resulting structure is shown in FIG. 9 . In region 100 , silicon strips 124 have tops that are higher than the top surfaces of remaining STI regions 136 , where the tops of silicon strips 124 are hereinafter referred to as semiconductor fins (silicon fins) 144 . According to some embodiments of the invention, the top surfaces of the remaining STI regions 136 are flush with or higher than the top of the _SiGeOx regions 132 (FIGS. 4A and 4B) covered _by the dielectric liner 134 in FIG. 9. Top of 132.

At the same time that STI region 136 is recessed, STI region 236 is also recessed. The SiGe strips 242 have tops that are higher than the top surfaces of the remaining STI regions 236 , where the tops of the SiGe strips 242 are hereinafter referred to as semiconductor fins (SiGe fins) 244 . According to some embodiments, semiconductor fins 144 and 244 have a height of between about 20 nm and about 40 nm. The top surfaces of the remaining STI regions 236 may be flush with or higher than the tops of the remaining silicon strips 224 (if present), or the remaining silicon strips 224 if the silicon strips 224 were completely removed in the previous step. The top surfaces of the STI regions 236 may be flush with or higher than the top surfaces of the SiGe strips 222 .

As shown in FIG. 9, portions of dielectric liners 134 and 234 are exposed. These portions of dielectric liners 134 and 234 are then removed. Next, as shown in FIG. 10A , dummy gate stacks 146 and 246 are formed to cover intermediate portions of semiconductor fins 144 and 244 ( FIG. 9 ), respectively. The ends of semiconductor fins 144 and 244 are not covered. According to some embodiments, gate stack 146 includes dummy gate 148 and mask layers 150 and/or 152 , and gate stack 246 includes dummy gate 248 and mask layers 250 and/or 252 . According to some embodiments, dummy gates 148 and 248 may be formed of polysilicon, although other materials may be used. In some exemplary embodiments, mask layers 150 and 250 are formed of silicon nitride, and mask layers 152 and 252 are formed of silicon oxide. Although not shown in FIG. 9 , a dummy gate dielectric, such as a silicon oxide layer, may be formed under dummy gates 148 and 248 . Dummy gates 148 and 248 are formed on the top surfaces and sidewalls of semiconductor fins 144 and 244 (FIG. 9), respectively. In addition, the gate stacks 146 and 246 may include gate spacers 153 and 253, respectively, which are formed on sidewalls of the dummy gates 148 and 248, respectively.

FIG. 10A also shows the formation of source and drain regions (hereafter referred to as source/drain regions) 154 in region 100 and the formation of source/drain regions 254 in region 200 . The source/drain regions 154 include silicon strips 124 as central portions and epitaxial regions 156 located outside the silicon strips 124 . Source/drain regions 254 include SiGe strips 242 as central portions and epitaxial regions 256 located outside of SiGe strips 242 . The formation of source/drain regions 154 and 254 is discussed with reference to FIG. 10B.

10B includes cross-sectional views of source/drain regions 154 and 254, wherein the cross-sectional view of source/drain region 154 is obtained from the vertical plane containing lines 10BN-10BN in FIG. The vertical plane of lines 10BP-10BP takes a cross-sectional view of source/drain regions 254 .

In the formation of the source/drain regions 154 , the semiconductor fins 144 , which in some embodiments include silicon strips 124 , are first thinned. For example, the thinning may include wet etching, and the etchant may include a solution of HF, _hydrogen peroxide (H2O2), and acetic _acid ( _CH3COOH ). Dashed line 158 shows the location of the edge and top surface of silicon strip 124 prior to thinning. Due to the thinning, the width of the thinned silicon strips 124 (fins 144 ) is reduced from the original width W2 before thinning to the width W1 after thinning. According to some embodiments, width W1 is between about 50% and about 70% of width W2, although width W1 may be larger or smaller. The widths W1 and W2 can be measured from the middle height of the silicon strip 124 . As shown in FIG. 10B , widths W1 and W2 are measured at 1/2 height H above the top surface of STI region 136 . As also shown in FIG. 10B , the dashed sidewalls of the original semiconductor fins 144 extend from the sidewalls of the STI regions 136 . However, the sidewalls 124A of the thinned silicon strips 124 are recessed toward the centerlines 160 of the silicon strips 124 . Due to the thinning, the top surface of the silicon strips 124 is also lowered.

An n-type epitaxial region 156 is epitaxially grown from the thinned silicon strips 124 . According to some embodiments, n-type epitaxial region 156 includes SiP, wherein phosphorous may be doped in-situ when n-type epitaxial region 156 is grown. Other n-type impurities (such as arsenic) other than phosphorus can also be used. Since the lattice constant of the n-type epitaxial region 156 is smaller than the lattice constant of the underlying SiGe strips 122, tensile strain is generated in the channel region of the corresponding n-type FinFET through the source/drain regions 154. Advantageously, by thinning the semiconductor strips 124 prior to the epitaxial growth process, the resulting n-type epitaxial regions 156 are contoured more like ellipses than diamonds. According to some exemplary embodiments, the concentration of phosphorus in the resulting source/drain regions 154 is in the range of about 5E20/cm ³ and about 2E21/cm ³ . Furthermore, when the silicon strips 124 are formed in the steps shown in FIGS. 1 and 2 , the silicon strips 124 may not be doped with phosphorus. However, in the thermal process following the steps shown in FIGS. 10A and 10B , the phosphorus diffuses into the thinned silicon strips 124 . There may or may not be a significant drop in phosphorus concentration at the interface between SiP region 156 and thinned silicon strip 124 . Also, a gradient of doping concentration can be created, wherein the outer portions of the silicon strips 124 adjoining the SiP regions 156 have a higher concentration of n-type impurities (phosphorus) than the inner portions of the silicon strips 124 . The n-type doping concentration may gradually and continuously increase from the inner region to the outer region of the thinned silicon strip 124 .

As also shown in FIG. 10B , in the formation of the source/drain regions 254 , the semiconductor fins 244 , which in some embodiments include SiGe strips 242 , are first thinned. _In some embodiments, the thinning may include wet etching, and the etchant may include a solution comprising _NH3OH and _H2O2 . In alternative embodiments, for example, the etchant includes HF, hydrogen peroxide (H ₂ O ₂ ), and acetic acid (CH ₃ COOH). Dashed line 258 shows the location of the edge and top surface of SiGe strip 242 prior to thinning. Due to the thinning, the width of the thinned semiconductor fin 244 is reduced from the original width W2' before thinning to the width W1'. According to some embodiments, width W1' is between about 50% and about 70% of width W2', although width W1' may be larger or smaller. The widths W1 ′ and W2 ′ can be measured from the middle height of the SiGe strip 242 . As shown in FIG. 10B , the dashed sidewalls 258 of the original semiconductor fins 244 extend from the sidewalls of the STI regions 236 . However, the sidewalls 242A of the thinned SiGe strips 242 are recessed toward the centerline 260 of the SiGe strips 242 . Due to the thinning, the top surface of the thinned SiGe strips 242 is also lowered.

A p-type epitaxial region 256 is epitaxially grown from the thinned SiGe strip 242 . According to some embodiments, p-type epitaxial region 256 includes SiGeB, wherein boron may be doped in situ when p-type epitaxial region 256 is grown. Other p-type impurities other than boron (such as indium) can also be used. Since the lattice constant of the p-type epitaxial region 256 is greater than the lattice constant of the underlying Si stripes 224 and/or SiGe strips 222, compressive strain is generated in the channel region of the corresponding p-type FinFET through the source/drain regions 254. According to some exemplary embodiments, the concentration of p-type impurities, such as boron, in the resulting source/drain regions 254 is in the range of about 5E20/ ^cm3 and about 2E21/ ^cm3 . Furthermore, when the SiGe strips 242 are epitaxially grown, the SiGe strips 242 may not be doped with p-type impurities, such as boron. However, in the thermal process following the steps in FIGS. 10A and 10B , the boron diffuses into the thinned SiGe strips 242 . Also, a gradient of doping concentration can be formed, wherein the outer portion of SiGe strip 242 adjacent to SiGeB region 256 has a higher p-type impurity concentration than the inner portion. The p-type doping concentration may gradually increase from the inner region to the outer region of the thinned SiGe strip 242 .

The SiGeB region 256 may be a homogeneous region with a high germanium percentage that is higher than the first germanium percentage of the SiGe strips 242 . The germanium percentage of SiGeB region 256 may range from about 70% to about 100% (this refers to germanium without silicon). According to an alternative embodiment, SiGeB regions 256 include SiGeB regions 256A having a second germanium percentage higher than the first germanium percentage of SiGe strips 242 . The second germanium percentage may be in the range of about 60% and about 80%. SiGeB region 256B is formed outside SiGeB region 256A, SiGeB region 256B having a third germanium percentage higher than the second germanium percentage of SiGeB region 256A. According to some embodiments, the third germanium percentage may be in the range of about 80% and about 100%. SiGeB regions 256, 256A, and 256B may have gradient germanium percentages, with the outer portion having an increasingly higher germanium percentage than the inner portion.

FIG. 11 shows a perspective view of the structure after forming an interlayer dielectric (ILD) 62 . The ILD 62 includes a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. CMP may be performed to make the top surface of ILD 62 flush with the top surface of dummy gate stacks 146 and 246 (FIG. 10A). Next, as shown in FIG. 11 , the dummy gate stacks 146 and 246 are removed by an etching step such that recesses 164 and 264 are formed in the ILD 62 . Grooves 164 and 264 are located in regions 100 and 200, respectively. Accordingly, middle portions of semiconductor fins 144 and 244 are exposed to recesses 164 and 264, respectively.

FIGS. 12A and 12B illustrate the formation of replacement gates 165 and 265 , which include gate dielectrics 166 and 266 and gate electrodes 168 and 268 . FinFETs 170 and 270 are thus formed. Figure 12A shows a perspective view. FIG. 12B shows a cross-sectional view taken from a plane perpendicular to the source-to-drain direction of FinFETs 170 and 270 . As shown in FIG. 12B , the silicon strip 124 includes a portion 124 - 1 that overlaps the replacement gate stack 165 (which is part of the fin 144 ) and a thinned portion 124 - that serves as the interior of the source/drain regions 154 2. For example, portions 124-1 and 124-2 have the same composition of group IV semiconductor elements such as silicon. Furthermore, the top surface of the thinned portion 124-2 is lower than the top surface of the non-thinned portion 124-1.

The SiGe strip 242 includes a portion 242 - 1 that overlaps the replacement gate stack 265 and a thinned portion 242 - 2 that serves as the interior of the source/drain regions 254 . For example, portions 242-1 and 242-2 have the same composition of Group IV semiconductor elements such as silicon and germanium, wherein the germanium percentage and silicon percentage in portion 242-1 are equal to the corresponding germanium percentages and the corresponding germanium percentages in portion 242-2. Silicon percentage. Throughout the specification, when two regions are referred to as having the same composition of Group IV semiconductor elements, the two regions have the same silicon percentage and the same germanium percentage. Furthermore, the top surface of the thinned portion 242-2 is lower than the top surface of the non-thinned portion 242-1. Silicide regions 172 and 272 and source/drain contact plugs 174 and 274 are also shown in Figure 12B.

12C shows a cross-sectional view of FinFETs 170 and 270, where the cross-sectional view is taken across replacement gates 165 and 265 and in a direction perpendicular to the source-to-drain direction. As shown in FIG. 12C , SiGeO _x regions 132 have portions that overlap with silicon strips 124 .

Embodiments of the present invention have several advantageous features. The formation of the source/drain regions includes thinning, but not completely removing, the original portion of the semiconductor fin, and then epitaxially growing an epitaxial region on the thinned semiconductor fin. This has the advantageous feature of maintaining strain in the channel region. In comparison, if the original portion of the semiconductor fin is completely removed after regrowing the source/drain regions, the strain can be relaxed. On the other hand, if the original semiconductor fins are not thinned before growing the epitaxial regions, the corresponding n-type or p-type dopants of the source/drain regions cannot diffuse effectively throughout the source/drain regions.

According to some embodiments of the present invention, a device includes a semiconductor substrate and an isolation region extending into the semiconductor substrate. The semiconductor fins are located between opposing portions of the isolation regions, wherein the semiconductor fins are located above the top surfaces of the isolation regions. The gate stack overlaps the semiconductor fins. Source/drain regions are on the sides of the gate stack and are connected to the semiconductor fins. The source/drain regions include an inner portion thinner than the semiconductor fin and an outer portion located outside the inner portion. The interior of the semiconductor fins and the source/drain regions have the same composition of the group IV semiconductor.

According to an alternative embodiment of the present invention, a device includes a silicon substrate, an isolation region extending into the silicon substrate, and a p-type FinFET. The p-type FinFET includes a silicon germanium fin including a middle portion and end portions on opposite sides of the middle portion. The top surface of the middle part is higher than the top surface of the end parts. The silicon germanium fin has a first germanium percentage. The p-type FinFET also includes a gate stack and source/drain regions overlapping the middle portion of the silicon germanium fin. The source/drain regions include one of the ends of the inner silicon germanium fin and a silicon germanium region on the outer side of the inner. The silicon germanium region has a second germanium percentage that is higher than the first germanium percentage.

According to yet another alternative embodiment of the present invention, a method includes recessing isolation regions on opposite sides of a semiconductor strip to form semiconductor fins, wherein the semiconductor fins are located over top surfaces of the isolation regions; in the middle of the semiconductor fins forming gate stacks on portions of the top surface and sidewalls; thinning the ends of the semiconductor fins; and performing epitaxy to grow semiconductor regions on the thinned ends of the semiconductor fins. The thinned ends of the semiconductor fins and the semiconductor regions combine to form the source/drain regions of the FinFET. Depending on the type of FinFET, the semiconductor region includes silicon phosphorus or silicon germanium boron.

The features of several embodiments have been outlined above so that those skilled in the art may better understand aspects of the invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention .

Claims (19)

1. a kind of semiconductor devices, comprising:

Semiconductor substrate；

Isolated area extends in the semiconductor substrate；

Semiconductor fin, between the opposite segments of the isolated area, wherein the semiconductor fin is located at the top of the isolated area Above face；

Gate stack, it is Chong Die with the middle section of the semiconductor fin；And

Source/drain regions on the side of the gate stack and are connected to the semiconductor fin, wherein the source Pole/drain region includes:

Inside, including first part and second part, the bottom surface of the first part, which has, is equal to or less than the semiconductor The third width of second width of the middle section of fin, the second part is right above the first part and has There is first width equal with the width of the top surface of the first part, first width is less than the third width, wherein The component of the inside of the semiconductor fin and source/drain regions IV race semiconductor having the same；With

Outside is located at the internal outside.

2. semiconductor devices according to claim 1, wherein the top surface of the inside is lower than the top of the semiconductor fin Face.

3. semiconductor devices according to claim 1, wherein the first width of the inside of the source/drain regions Be the 50% to 70% of the second width of the semiconductor fin, wherein with the fin field effect including the source/drain regions First width, second width and described are measured on the source electrode of transistor (FinFET) to the vertical direction of drain directions Third width.

4. semiconductor devices according to claim 1, wherein the gate stack and the source/drain regions include In N-shaped fin formula field effect transistor (FinFET), and the inside includes silicon and not germanic, and wherein, the outside Including silicon phosphorus.

5. semiconductor devices according to claim 4, further includes:

Two SiGeO_xArea, wherein the SiGeO_xThe inside in area is Chong Die with the semiconductor fin.

6. semiconductor devices according to claim 5, further includes:

Silicon Germanium regions are located at described two SiGeO_xBetween area.

7. semiconductor devices according to claim 1, wherein the gate stack and the source/drain regions include In p-type fin formula field effect transistor (FinFET), and the inside includes the SiGe with the first germanium percentage, and institute Stating outside includes the SiGe with the second germanium percentage greater than the first germanium percentage.

8. semiconductor devices according to claim 7, further includes:

Silicon layer, below the inside of the source/drain regions；And

Additional germanium-silicon layer is located at below the silicon layer and is located above the semiconductor substrate.

9. a kind of semiconductor devices, comprising:

Silicon substrate；

Isolated area extends in the silicon substrate；And

P-type fin formula field effect transistor (FinFET), comprising:

SiGe fin, the SiGe fin include middle section and the end in the opposite sides of the middle section, wherein institute The top surface for stating middle section is higher than the top surface of the end, and wherein, the SiGe fin has the first germanium percentage；

Gate stack, it is Chong Die with the middle section of the SiGe fin；With

Source/drain regions including one in the end as the internal SiGe fin and are located at outside the inside The silicon Germanium regions of side, wherein the silicon Germanium regions have the second germanium percentage higher than the first germanium percentage；

Wherein, the inside of the source/drain regions includes first part and second part, and the bottom surface of the first part has etc. In or less than the SiGe fin middle section the second width third width, the second part is located immediately at described first Right above part and there is first width equal with the width of the top surface of the first part, first width is less than institute State third width.

10. semiconductor devices according to claim 9, wherein the source/drain regions further include being located at the silicon Germanium regions The additional silicon Germanium regions in outside, wherein the additional silicon Germanium regions have the third germanium percentage higher than the second germanium percentage.

11. semiconductor devices according to claim 9, wherein the SiGe fin extends below the top of the isolated area The horizontal plane in face, and the device further include:

Silicon layer is located at below the SiGe fin；

Additional germanium-silicon layer, is located at below the silicon layer；And

Silicon strip is located at the additional germanium-silicon layer in the following, wherein, the silicon strip is continuously connected to the silicon substrate.

12. semiconductor devices according to claim 11, wherein the first width of the end of the SiGe fin is less than Second width of the middle section of the SiGe fin, wherein brilliant with the fin field effect including the source/drain regions First width, second width and described are measured on the source electrode of body pipe (FinFET) to the vertical direction of drain directions Three width.

13. semiconductor devices according to claim 12, wherein first width between second width 50% And between 70%.

14. a kind of method for forming semiconductor devices, comprising:

Keep the isolated area in the opposite sides of semiconductor bar recessed to form semiconductor fin, wherein the semiconductor fin is located at institute State the top face of isolated area；

Gate stack is formed on the top surface of the middle section of the semiconductor fin and side wall；

The end of the semiconductor fin is thinned；And

Implement extension to grow semiconductor region on the thinned end in the semiconductor fin, wherein the institute of the semiconductor fin It states thinned end and the semiconductor region combines the source/drain regions to form fin formula field effect transistor (FinFET)；

The thinned end includes first part and second part, and the bottom surface of the first part has equal to or less than described The third width of second width of the middle section of semiconductor fin, the second part is right above the first part And there is first width equal with the width of the top surface of the first part, it is wide that first width is less than the third Degree.

15. according to the method for claim 14, wherein implement described be thinned after forming the gate stack.

16. according to the method for claim 14, wherein the fin formula field effect transistor is N-shaped fin field effect crystal Pipe, and the semiconductor fin is free from the silicon fin of germanium, and wherein, and the extension includes the growth area Gui Lin.

17. according to the method for claim 14, wherein the semiconductor bar includes the silicon strip Chong Die with SiGe item, and The method also includes:

Oxidation is implemented to the external of the SiGe item, wherein the germanium concentration in the oxidation, in the inside of the SiGe item.

18. according to the method for claim 14, wherein the fin formula field effect transistor is p-type fin field effect crystal Pipe, and the semiconductor fin includes the SiGe fin with the first germanium percentage, and wherein, and the extension includes that growth has Higher than the SiGe boron area of the second germanium percentage of the first germanium percentage.

19. according to the method for claim 18, further include, before keeping the isolated area recessed:

The top of the silicon strip between the isolated area is etched to form groove；And

SiGe item, SiGe item described in the bottom grown from the silicon strip, wherein the SiGe item has are grown in the groove The first germanium percentage.