CN106158883B

CN106158883B - Display panel, display device, array substrate and preparation method thereof

Info

Publication number: CN106158883B
Application number: CN201610854688.9A
Authority: CN
Inventors: 许喜爱; 李作银
Original assignee: Tianma Microelectronics Co Ltd; Xiamen Tianma Microelectronics Co Ltd
Current assignee: Tianma Microelectronics Co Ltd; Xiamen Tianma Microelectronics Co Ltd
Priority date: 2016-09-27
Filing date: 2016-09-27
Publication date: 2019-03-29
Anticipated expiration: 2036-09-27
Also published as: CN106158883A

Abstract

This application discloses a kind of display panels, display device, array substrate and preparation method thereof, wherein, the production method of the array substrate includes: offer first substrate, and the first substrate surface has pixel driver film layer and deviates from the flatness layer on the first substrate surface positioned at the pixel driver film layer；Reduction processing is carried out to the flatness layer, forms groove；Conductive layer and passivation layer are sequentially formed away from the first substrate side in the flatness layer；It is performed etching in the passivation layer and the groove corresponding region, forms through-hole, the through-hole is through the passivation layer and other flatness layers；The pixel electrode layer connecting by groove and through-hole with pixel driver film layer is formed away from one side surface of first substrate in passivation layer.The production method of the array substrate avoids the problem of passivation layer being likely to occur in etching process while to flatness layer and passivation layer completely removes, vertical etch occurs in flatness layer, the coating homogeneity difference and photoresist waste of photoresist.

Description

Display panel, display device, array substrate and preparation method thereof

Technical field

This application involves display panel preparation technical field, more specifically to a kind of display panel, display device, Array substrate and preparation method thereof.

Background technique

With the continuous development of display technology, display panel using more and more extensive.Important structure as display panel At part, the quality of array substrate is largely fixed the display effect of display panel, wherein through the flat of array substrate Smooth layer and passivation layer, and through-hole corresponding with the drain region of thin film transistor (TFT) not only decides the aperture opening ratio of display panel, and And decide the contact resistance of the drain electrode of the pixel electrode and thin film transistor (TFT) of display panel.

In order to increase the aperture opening ratio of display panel, and the contact resistance of pixel electrode and thin film transistor (TFT) drain electrode is reduced, The mode for generalling use flatness layer and passivation layer while etching in the prior art forms through-hole, but as display panel shows picture Prime number amount is continuously increased, and device (such as the thin film transistor (TFT) etc.) quantity carried needed for array substrate can also accordingly increase, This requires flatness layers to have biggish thickness, and so etching forms when through-hole that required etch period will at the same time It is longer, if the meeting when passivation layer surface coats relatively thin photoresist to passivation layer and flatness layer progress while etching forms through-hole So that occurring the case where passivation layer is completely removed after through-hole is formed, and flatness layer is made the problem of vertical etch occur, from And increase the broken string risk of the pixel electrode by through-hole and thin film transistor (TFT) drain electrode connection；And if coated in passivation layer surface When enough photoresists carry out passivation layer and flatness layer while etching forms through-hole, and the photoresist thickness that will appear coating reaches The case where to the board coating ability upper limit, causes the coating homogeneity of photoresist poor and the problem of photoresist wastes.

Summary of the invention

In order to solve the above technical problems, the present invention provides a kind of display panel, display device, array substrate and its production Method, with solve due to array substrate flatness layer have larger thickness, caused by while to flatness layer and passivation layer The passivation layer occurred in etching process completely removes, vertical etch occurs in flatness layer, the coating homogeneity of photoresist is poor and light The problem of photoresist wastes.

In order to solve the above technical problems, the embodiment of the invention provides following technical solutions:

A kind of production method of array substrate, comprising:

First substrate is provided, the first substrate surface has pixel driver film layer and is located at the pixel driver film layer Flatness layer away from the first substrate surface；

Reduction processing is carried out to the flatness layer, forms groove, the groove gos deep into the part flatness layer；

Conductive layer and passivation layer are sequentially formed away from the first substrate side in the flatness layer；

It is performed etching in the passivation layer and the groove corresponding region, forms through-hole, the through-hole runs through the passivation Layer and other described flatness layers, the projection of the through-hole on the first substrate are located at the groove on the first substrate Projection in；

Pixel electrode layer is formed away from one side surface of first substrate in the passivation layer, the pixel electrode layer passes through The groove and through-hole are connect with the pixel driver film layer.

Optionally, the forming process of the pixel driver film layer includes:

The first substrate surface formed a plurality of grid line arranged in the first direction, in a second direction arrange it is a plurality of Data line and the thin film transistor (TFT) in the grid line and the data line limited area, the first direction with it is described Second direction is intersected, wherein the pixel electrode layer is connect by the groove and through-hole with the drain electrode of the thin film transistor (TFT).

Optionally, described to carry out reduction processing to the flatness layer, forming groove includes:

The flatness layer is exposed using intermediate tone mask plate, is then developed again to the flatness layer after exposure, Removal is located at the part flatness layer of intermediate tone mask plate overlay area；

The flatness layer is made annealing treatment, groove, groove projection on the first substrate and institute are formed It is least partially overlapped to state the projection of the drain electrode of thin film transistor (TFT) on the first substrate.

Optionally, described to perform etching in the passivation layer and the groove corresponding region, forming through-hole includes:

Photoresist is coated away from one side surface of first substrate in the passivation layer；

The photoresist is exposed using mask plate, then is developed to the photoresist after exposure, is formed after development Region is fully retained in photoresist and photoresist completely removes region；Wherein, the photoresist completely removes region corresponding to described The drain region of thin film transistor (TFT)；

The passivation layer is performed etching using the photoresist after exposure development as exposure mask, it is complete that removal is located at the photoresist The passivation layer and flatness layer in region are removed, through-hole is formed；

By remaining photoresist lift off.

A kind of array substrate, comprising:

First substrate, the first substrate surface have pixel driver film layer and deviate from positioned at the pixel driver film layer The flatness layer on the first substrate surface；

Deviate from the conductive layer and passivation layer of the first substrate side positioned at the flatness layer；

Deviate from the pixel electrode layer of one side surface of first substrate positioned at the passivation layer, the pixel electrode layer passes through Groove and through-hole are connect with the pixel driver film layer, and the groove gos deep into the part flatness layer, and the through-hole is through described Passivation layer and other described flatness layers, the projection of the through-hole on the first substrate are located at the groove in first base In projection on plate.

Optionally, the pixel driver film layer includes: arranged in the first direction a plurality of positioned at the first substrate surface Grid line, the multiple data lines arranged in a second direction and positioned at the grid line with it is thin in the data line limited area Film transistor, the first direction intersect with the second direction, wherein the pixel electrode layer passes through the groove and through-hole It is connect with the drain electrode of the thin film transistor (TFT).

Optionally, the groove, the through-hole are perpendicular to the first substrate and along the grid line extending direction Section be it is trapezoidal, and the trapezoidal short side is located between its long side and the first substrate, and the trapezoidal long side is institute The longer a line of length in one group of trapezoidal parallel edges is stated, the trapezoidal short side is long in one group of trapezoidal parallel edges Spend shorter a line.

Optionally, the through-hole is with the passivation layer true by preset formula perpendicular to the thickness difference on the first substrate It is fixed；

The preset formula are as follows:Wherein, D2 be the through-hole with the passivation layer vertical Thickness difference on the first substrate direction；L1≤3.5 μm are the long side length of the through-hole；L2 is the short of the through-hole Edge lengths, value range are 0 μm of-L1, do not include endpoint value；θ is the supplementary angle of through-hole short side side interior angle.

Optionally, the base length that the groove retains in the through-hole two sides be greater than the passivation layer be parallel to it is described Thickness on first substrate direction.

A kind of display panel, including the array substrate being oppositely arranged and opposite substrate, wherein the array substrate is above-mentioned Described in any item array substrates.

A kind of display device, the display panel including at least one as described in above-mentioned one.

It can be seen from the above technical proposal that the embodiment of the invention provides a kind of display panel, display device, array bases Plate and preparation method thereof, wherein the flatness layer of the array substrate first carries out reduction processing, shape before the etching for carrying out through-hole At the groove for going deep into the part flatness layer, to reduce the flatness layer institute when etching simultaneously to the flatness layer and passivation layer The thickness that need to be etched, this reduces the times of etching needed for the flatness layer described when forming the through-hole, avoid etching In the process due to the case where the passivation layer is completely removed caused by coating relatively thin photoresist, also avoid due to longer Etch period make the flatness layer the problem of vertical etch occur；Meanwhile also just because of reducing to described flat The thickness that layer and passivation layer etch needed for the flatness layer when etching simultaneously applies to reduce needs in the passivation layer surface The photoresist thickness covered is avoided in the photoresist that coats to the flatness layer and passivation layer while when etching forms the through-hole Reach the board coating ability upper limit, caused by photoresist coating the problem of homogeneity is poor and photoresist wastes.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis The attached drawing of offer obtains other attached drawings.

Fig. 1 is the flow diagram of the production method for the array substrate that one embodiment of the present of invention provides；

Fig. 2, Fig. 5-Fig. 9 are the production flow diagram for the array substrate that one embodiment of the present of invention provides；

Fig. 3 is a kind of overlooking structure diagram for pixel driver film layer that one embodiment of the present of invention provides；

Fig. 4 is a kind of structural schematic diagram for thin film transistor (TFT) that one embodiment of the present of invention provides；

Figure 10 is a kind of forming process flow chart for pixel driver film layer that one embodiment of the present of invention provides；

Figure 11 be another embodiment of the present invention provides a kind of array substrate production method flow diagram；

Figure 12 is a kind of flow diagram of the production method for array substrate that another embodiment of the invention provides；

Figure 13 is a kind of structural schematic diagram for array substrate that one embodiment of the present of invention provides.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

The embodiment of the invention provides a kind of production methods of array substrate, and as shown in FIG. 1, FIG. 1 is the array substrates Production method flow diagram, comprising:

S101: providing first substrate, and the first substrate surface, which has pixel driver film layer and is located at the pixel, drives Dynamic film layer deviates from the flatness layer on the first substrate surface.

The first substrate can be glass substrate or quartz base plate, the present invention to the specific type of the first substrate simultaneously Without limitation, specific depending on actual conditions.

With reference to Fig. 2, Fig. 2 is cross section structure signal of the array substrate in addition to conductive layer, passivation layer and pixel electrode layer Figure；The first substrate 10, the pixel driver film layer 20 and the flatness layer 30 is shown in FIG. 2.

A specific embodiment of the invention provides a kind of specific composition of pixel driver film layer, as shown in figure 3, Fig. 3 For the structural schematic diagram of the pixel driver film layer 20, which includes:

Arranged in a crossed manner and mutually insulated multiple data lines 21 and grid line 22, the multiple data lines 21 and grid line 22 Limit multiple display pixels 23；

Be electrically connected with the data line 21 and the grid line 22 thin film transistor (TFT) (Thin Film Transistor, TFT), the grid G of the thin film transistor (TFT) is connect with the grid line 22, and source S is connect with the data line 21, when the battle array When column substrate is applied to liquid crystal display panel, the drain D of the thin film transistor (TFT) is connect with pixel electrode, in the grid line 22 Control under, the data that the data line 21 inputs are supply display signals to display pixel corresponding with the thin film transistor (TFT) 23。

It should be noted that the thin film transistor (TFT) can be top gate type thin film transistor, it is also possible to bottom gate thin film Transistor, the present invention to this and without limitation, specifically depending on actual conditions.Wherein, top-gated and bottom gate refer to thin film transistor (TFT) Position of the grid G relative to active layer (or be channel region) depending on, it may be assumed that the relatively described first substrate 10, when grid G is leaned on The nearly first substrate 10, when the active layer is far from the first substrate 10, the thin film transistor (TFT) is that bottom gate film is brilliant Body pipe, when grid G is far from the first substrate 10, when the active layer is close to the first substrate 10, the thin film transistor (TFT) For top gate type thin film transistor.

The structure of thin film transistor (TFT) will be illustrated by taking bottom gate thin film transistor as an example below, is with reference to Fig. 4, Fig. 4 A kind of structural schematic diagram for bottom gate thin film transistor that one embodiment of the present of invention provides；In Fig. 4, the active layer CR Grid G positioned at the thin film transistor (TFT) far from 10 side of first substrate, and be located at the thin film transistor (TFT) source S and Between drain D, the making material of the active layer CR is semiconductor material, and the semiconductor material is amorphous silicon, low-temperature polysilicon Silicon, metal oxide or low-temperature polysilicon oxide；Gate insulation layer GI is provided between the active layer CR and the grid G, and The active layer CR is set to the surface of the grid G, i.e., projection of the described active layer CR on the first substrate 10 is covered Cover projection of the grid G on the first substrate 10, wherein the gate insulation layer GI can be silicon nitride layer or silica Layer has buffer layer BF between the grid G of the thin film transistor (TFT) and the first substrate 10.

In addition, array substrate shown in Fig. 3 further includes data drive circuit 24 and gate driving circuit 25.The data Driving circuit 24 is connect with the data line 21, and the data drive circuit 24 is used to pass through the data line 21 in the display stage Signal is shown to 23 input data of display pixel, is shown with controlling the display panel；The gate driving circuit 25 with Grid line 22 is connected, for providing scanning signal to thin film transistor (TFT) by grid line 22 in the display stage, to control film crystalline substance Body pipe opens or closes.

S102: reduction processing is carried out to the flatness layer, forms groove, the groove gos deep into the part flatness layer.

With reference to Fig. 5, Fig. 5 is that the array substrate after reduction processing removes conductive layer, passivation layer and pixel electrode layer Outer cross section structure schematic diagram.Projection of the groove 31 on the first substrate 10 is thin with the pixel driver film layer 20 Projection of the drain electrode (being not shown in attached drawing 5) of film transistor on the first substrate 10 is least partially overlapped.

S103: conductive layer and passivation layer are sequentially formed away from the first substrate side in the flatness layer.

With reference to Fig. 6, Fig. 6 is cross section structure of the array substrate in addition to the pixel electrode layer after step S103 Schematic diagram；The first substrate 10, pixel driver film layer 20, flatness layer 30, conductive layer 40 and passivation layer are shown in attached drawing 6 50.The making material of the conductive layer 40 can be tin indium oxide (Indium Tin Oxides, ITO) or indium-doped zinc oxide (Indium-Doped Zinc Oxides, IZO), the present invention to this and without limitation, specifically depending on actual conditions.In addition institute Conductive film can be formed by magnetron sputtering by stating conductive layer 40, then perform etching to form the conductive layer to conductive film 40, the present invention to the specific forming process of the conductive layer 40 and without limitation, specifically depending on actual conditions.

S104: performing etching in the passivation layer and the groove corresponding region, forms through-hole, the through-hole is through described Passivation layer and other described flatness layers, the projection of the through-hole on the first substrate are located at the groove in first base In projection on plate.

With reference to Fig. 7 and Fig. 8, Fig. 7 and Fig. 8 are the array substrate after step S104 in addition to the pixel electrode layer Cross section structure schematic diagram；Shown in attached drawing 7 and attached drawing 8 first substrate 10, pixel driver film layer 20, flatness layer 30, Conductive layer 40 and passivation layer 50 and the through-hole TH and the groove 31.Fig. 7 and Fig. 8 respectively illustrates two kinds in the groove The structure after the through-hole TH, specifically, the bottom surface that the groove 31 described in Fig. 7 retains in the two sides the through-hole TH are formed in 31 Length W1 is equal to the passivation layer 50 in the thickness W2 being parallel on 10 direction of first substrate, in the structure shown in figure 7 When forming pixel electrode layer, the pixel electrode layer can be along the one of the formation of the side wall of the passivation layer 50 and the flatness layer 30 Ramp is directly connect with the pixel driver film layer 20, since the thickness of the flatness layer 30 is larger, the passivation layer 50 and the flatness layer 30 side wall formed ramp can be long, when forming the pixel electrode layer, will increase the picture The broken string risk of plain electrode layer；The groove 31 is greater than described in the base length W3 that the two sides the through-hole TH retain in fig. 8 Passivation layer 50 is in the thickness W2 being parallel on 10 direction of first substrate, and so in fig. 8, the passivation layer 50 is described logical The hole two sides TH can remain with a step FS respectively, the pixel electrode layer being subsequently formed in this way can by the step FS and Two shorter ramps are connect with the pixel driver film layer 20, reduce the pixel electrode layer by 31 He of groove Broken string risk when the through-hole TH is connect with the pixel driver film layer 20.

It should be noted that the passivation layer 50 refer in the thickness W2 being parallel on 10 direction of first substrate it is described The portion of the passivating layer 50 that a bevel edge of the groove 31 is parallel in passivation layer 50 is being parallel to 10 direction of first substrate On length (i.e. the length of the marked part W2 in Fig. 7 and Fig. 8).

S105: pixel electrode layer, the pixel electrode are formed away from one side surface of first substrate in the passivation layer Layer is connect by the groove and through-hole with the pixel driver film layer.

It is the cross section structure schematic diagram of the array substrate after step S105 with reference to Fig. 9, Fig. 9；It is shown in Fig. 9 described First substrate 10, pixel driver film layer 20, flatness layer 30, conductive layer 40, passivation layer 50 and pixel electrode layer 60.Likewise, institute The making material for stating pixel electrode layer 60 can be ITO or IZO, and the pixel electrode layer 60 can be formed by magnetron sputtering and be led Then electrolemma layer performs etching conductive film layer to form the pixel electrode layer 60, the present invention is to the pixel electrode layer 60 Making material and specific formation process and without limitation, specifically depending on actual conditions.

On the basis of the above embodiments, in one embodiment of the invention, as shown in Figure 10, Figure 10 is the pixel Drive the flow diagram of the forming process of film layer；The forming process of the pixel driver film layer includes:

S1011: a plurality of grid line 22 arranged in the first direction, in a second direction is formed on 10 surface of first substrate The multiple data lines 21 of arrangement and the thin film transistor (TFT) 23 in the grid line 22 and 21 limited area of data line, The first direction intersects with the second direction, wherein the pixel electrode layer passes through the groove 31 and through-hole TH and institute State the drain D connection of thin film transistor (TFT).

It should be noted that a plurality of grid line 22 and multiple data lines 21 can be formed by way of magnetron sputtering Then conductive film forms figure by etching technics, can also form conductive film by modes such as molecular beam epitaxies, make It can be ITO or IZO as material, can also be the metals such as metal material, such as molybdenum, aluminium, molybdenum aluminium alloy, molybdenum and tungsten alloy.This hair Bright making material and preparation process to a plurality of grid line 22 and multiple data lines 21 and without limitation, the specific practical feelings of view Depending on condition.

On the basis of the above embodiments, in another embodiment of the present invention, as shown in figure 11, Figure 11 is this implementation A kind of flow diagram of the production method for array substrate that example provides, it is described that reduction processing, shape are carried out to the flatness layer 30 Include: at groove 31

S1021: the flatness layer 30 is exposed using intermediate tone mask plate, then again to the flatness layer 30 after exposure Develop, removal is located at the part flatness layer 30 of intermediate tone mask plate overlay area.

The intermediate tone mask plate has the characteristic of partial light permeability, can carry out Partial exposure to the flatness layer 30, make The flatness layer 30 of its exposed portion can be developed with developed liquid to be removed, so that reaching removal is located at the intermediate tone mask plate The purpose of the part flatness layer 30 of overlay area.It in other embodiments of the invention, can also be with other with partial light permeability The mask plate of characteristic is that exposure mask is exposed the flatness layer 30, the present invention to the groove 31 is formed during use Mask plate type and without limitation, specifically depending on actual conditions.

S1022: making annealing treatment the flatness layer 30, forms groove 31, the groove 31 is in the first substrate Projecting on 10 is least partially overlapped with projection of the drain D of the thin film transistor (TFT) on the first substrate 10.

It should be noted that the purpose made annealing treatment to the flatness layer 30 is made through overexposure in step S1022 The stable structure of photodevelopment treated flatness layer 30, makes the dimensionally stable of the groove 31.

On the basis of the above embodiments, another embodiment of the invention provides a kind of to the passivation layer 50 and flat Smooth layer 30 performs etching, and forms the detailed process of the through-hole TH, and as shown in figure 12, Figure 12 is a kind of battle array provided in this embodiment The flow diagram of the production method of column substrate, it is described to be performed etching in the passivation layer 50 and 31 corresponding region of groove, Forming through-hole TH includes:

S1041: photoresist is coated away from 10 1 side surface of first substrate in the passivation layer 50.

In step S1041, since the flatness layer 30 carried out reduction processing, deviate from institute in the passivation layer 50 The thickness for stating 10 1 side surface of first substrate coating photoresist can be smaller, and does not have to coat 4.5 μm as in the prior art The photoresist of left and right thickness is carried out while being etched to flatness layer and passivation layer, it is however generally that, when coating photoresist using board, 4.5 μm have had reached the upper limit of board coating ability, and coat the poor (coating thickness of homogeneity of 4.5 μm of photoresist 11%) difference is greater than, this poor homogeneity will cause a large amount of wastes of photoresist.

S1042: being exposed the photoresist using mask plate, then develop to the photoresist after exposure, development Region is fully retained in formation photoresist afterwards and photoresist completely removes region；Wherein, it is corresponding to completely remove region for the photoresist In the drain region of the thin film transistor (TFT).

It should be noted that the flatness layer 30 and the passivation layer 50 that the photoresist completely removes region overlay are just It is the part for needing to perform etching, so that the pixel electrode layer is passed through the through-hole to expose the drain D of the thin film transistor (TFT) TH is connected thereto.

S1043: performing etching the passivation layer 50 using the photoresist after exposure development as exposure mask, and removal is located at the light Photoresist completely removes the passivation layer 50 and flatness layer 30 in region, forms through-hole TH.

Typically, in step S1043, it is preferred to use dry etching performs etching the passivation layer 50, with removal The passivation layer 50 and flatness layer 30 in region are completely removed positioned at the photoresist.But in other embodiments of the invention, may be used The passivation layer 50 is performed etching using wet etching, the present invention to the specific lithographic method of use and without limitation, specifically Depending on actual conditions.

S1044: by remaining photoresist lift off.

It should be noted that under normal circumstances, to form described lead to performing etching to the passivation layer 50 and flatness layer 30 It needs to carry out ashing processing after the TH of hole, to remove remaining photoresist, and plays the cleaning passivation layer 50 and flatness layer 30 Purpose.

Correspondingly, the embodiment of the invention also provides a kind of array substrate, as shown in figure 9, Fig. 9 is provided in this embodiment A kind of cross section structure schematic diagram of array substrate, the array substrate include:

First substrate 10,10 surface of first substrate have pixel driver film layer 20 and are located at the pixel driver film Layer 20 deviates from the flatness layer 30 of 10 1 side surface of first substrate；

Deviate from the conductive layer 40 and passivation layer 50 of 10 side of first substrate positioned at the flatness layer 30；

Deviate from the pixel electrode layer 60 of 10 1 side surface of first substrate, the pixel electrode positioned at the passivation layer 50 Layer 60 is connect by groove (not marking in attached drawing 9) and through-hole (not marking in attached drawing 9) with the pixel driver film layer 20, described Groove gos deep into the part flatness layer, and the through-hole exists through the passivation layer 50 and other described flatness layers 30, the through-hole Projection on the first substrate 10 is located at the groove in the projection on the first substrate 10.

A specific embodiment of the invention provides a kind of specific composition of pixel driver film layer 20, as shown in figure 3, figure 3 be the structural schematic diagram of pixel driver film layer 20, which includes:

In addition, array substrate shown in Fig. 3 further includes data drive circuit 24 and gate driving circuit 25.The data Driving circuit 24 is connect with the data line 21, and the data drive circuit 24 is used to pass through the data line 21 in the display stage Signal is shown to 23 input data of display pixel, is shown with controlling the flexible display panels；The gate driving circuit 25 are connected with grid line 22, thin to control for providing scanning signal to thin film transistor (TFT) by grid line 22 in the display stage Film transistor opens or closes.

It should also be noted that, a plurality of grid line 22 and multiple data lines 21 can by way of magnetron sputtering shape At conductive film, figure then is formed by etching technics, conductive film can also be formed by modes such as molecular beam epitaxies, Making material can be ITO or IZO, can also be the metals such as metal material, such as molybdenum, aluminium, molybdenum aluminium alloy, molybdenum and tungsten alloy.This To the making material and preparation process of a plurality of grid line 22 and multiple data lines 21 and without limitation, specific view is practical for invention Depending on situation.

On the basis of the above embodiments, in one embodiment of the invention, as shown in figure 13, Figure 13 is the present embodiment A kind of cross section structure schematic diagram of the array substrate provided, in the present embodiment, the groove, the through-hole are perpendicular to described First substrate 10 and section on the grid line extending direction are trapezoidal, and the trapezoidal short side is located at its long side and institute It states between first substrate 10, the trapezoidal long side is the longer a line of length in one group of trapezoidal parallel edges, described Trapezoidal short side is a line that length is shorter in one group of trapezoidal parallel edges.

The through-hole is determined perpendicular to the thickness difference on the first substrate 10 by preset formula with the passivation layer 50；

The preset formula are as follows:Wherein, D2 is that the through-hole and the passivation layer 50 are hanging down Directly in the thickness difference on the first substrate 10；L1≤3.5 μm are the long side length of the through-hole；L2 is the short of the through-hole Edge lengths, value range are 0 μm of-L1, do not include endpoint value；θ is the supplementary angle of through-hole short side side interior angle.

It should be noted that the groove is greater than institute in the base length W3 that the through-hole two sides retain in attached drawing 13 Passivation layer 50 is stated in the thickness W2 being parallel on 10 direction of first substrate, in this way in attached drawing 13, the passivation layer 50 exists The through-hole two sides can remain with a step respectively, and the pixel electrode layer 60 being subsequently formed in this way can pass through this described step And two shorter ramps are connect with the pixel driver film layer 20, reduce the pixel electrode layer 60 by described recessed Broken string risk when slot and the through-hole are connect with the pixel driver film layer 20.

It should also be noted that, the passivation layer 50 refers to institute in the thickness W2 being parallel on 10 direction of first substrate It states and is parallel to the portion of the passivating layer 50 of a bevel edge of the groove 31 in passivation layer 50 and is being parallel to 10 side of first substrate Upward length (i.e. the length of the marked part W2 in Figure 13).

But in other embodiments of the invention, the groove can also be waited in the base length that the through-hole two sides retain In the passivation layer 50 in the thickness being parallel on 10 direction of first substrate, but in these embodiments, the pixel electricity The ramp that pole layer 60 can be formed along the side wall of the passivation layer 50 and the flatness layer 30 directly with the pixel driver Film layer 20 connects, since the thickness of the flatness layer 30 is larger, the side wall shape of the passivation layer 50 and the flatness layer 30 At ramp can be long, when forming the pixel electrode layer 60, will increase the broken string risk of the pixel electrode layer 60.This Invention in the thickness relationship and without limitation of through-hole two sides remainder and the passivation layer 50, has the groove floor Depending on stereoscopic actual conditions.

Correspondingly, the embodiment of the invention also provides a kind of display panel, including the array substrate and opposite direction being oppositely arranged Substrate, wherein the array substrate is array substrate described in any of the above-described embodiment.

Correspondingly, the embodiment of the invention also provides a kind of display devices, including at least one is as described in above-described embodiment Display panel.

In conclusion the embodiment of the invention provides a kind of display panel, display device, array substrate and its production sides Method, wherein the flatness layer 30 of the array substrate first carries out reduction processing before the etching for carrying out through-hole, and part is goed deep into formation The groove of the flatness layer 30, to reduce when being etched simultaneously to the flatness layer 30 and passivation layer 50 needed for the flatness layer 30 The thickness of etching, this reduces the times of etching needed for the flatness layer 30 described when forming the through-hole, avoid etching In the process due to the case where the passivation layer 50 is completely removed caused by coating relatively thin photoresist, also avoid due to compared with Long etch period makes the flatness layer 30 the problem of vertical etch occur；Meanwhile also just because of reducing to described The thickness that flatness layer 30 and passivation layer 50 etch needed for the flatness layer 30 when etching simultaneously, to reduce needs described blunt Change 50 surface of layer coating photoresist thickness, avoid to the flatness layer 30 and passivation layer 50 simultaneously etch formed it is described lead to The photoresist coated when hole reaches the board coating ability upper limit, caused by photoresist coating homogeneity is poor and photoresist waste The problem of.

Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other The difference of embodiment, the same or similar parts in each embodiment may refer to each other.

The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one The widest scope of cause.

Claims

1. A method for fabricating an array substrate, comprising:

providing a first substrate, the surface of the first substrate has a pixel driving film layer and a flat layer located on the pixel driving film layer away from the surface of the first substrate;

performing a thinning process on the flat layer to form a groove, and the groove penetrates part of the flat layer;

forming a conductive layer and a passivation layer in sequence on the side of the flat layer away from the first substrate;

Etching is performed in the area corresponding to the passivation layer and the groove to form a through hole, the through hole penetrates the passivation layer and the remaining flat layer, and the through hole is located on the first substrate. the projection is located in the projection of the groove on the first substrate;

A pixel electrode layer is formed on the surface of the passivation layer on the side away from the first substrate, and the pixel electrode layer is connected to the pixel driving film layer through the groove and the through hole.

2 . The method for fabricating an array substrate according to claim 1 , wherein the forming process of the pixel driving film layer comprises: 3 .

A plurality of gate lines arranged in a first direction, a plurality of data lines arranged in a second direction, and thin film transistors located in regions defined by the gate lines and the data lines are formed on the surface of the first substrate, so that The first direction intersects with the second direction, wherein the pixel electrode layer is connected to the drain electrode of the thin film transistor through the groove and the through hole.

3 . The method for fabricating an array substrate according to claim 2 , wherein the thinning of the flat layer to form the groove comprises: 3 .

Expose the flat layer with a halftone mask, and then develop the exposed flat layer to remove part of the flat layer located in the area covered by the halftone mask;

The flat layer is annealed to form a groove, the projection of the groove on the first substrate at least partially overlaps the projection of the drain electrode of the thin film transistor on the first substrate.

4 . The manufacturing method of the array substrate according to claim 2 , wherein the etching in the region corresponding to the passivation layer and the groove to form the through hole comprises: 5 .

Coat a photoresist on the surface of the passivation layer away from the first substrate;

The photoresist is exposed by using a mask, and the exposed photoresist is developed, and after development, a photoresist completely reserved area and a photoresist completely removed area are formed; wherein, the photoresist is completely removed a region corresponding to the drain region of the thin film transistor;

The passivation layer is etched with the photoresist after exposure and development as a mask, and the passivation layer and the flat layer located in the completely removed area of the photoresist are removed to form through holes;

Strip the remaining photoresist.

5. An array substrate, comprising:

a first substrate, the surface of the first substrate has a pixel driving film layer and a flat layer located on the pixel driving film layer away from the surface of the first substrate;

a conductive layer and a passivation layer on the side of the flat layer away from the first substrate;

a pixel electrode layer located on the surface of the passivation layer away from the first substrate, the pixel electrode layer is connected to the pixel driving film layer through grooves and through holes, and the grooves penetrate into part of the flat layer , the through hole penetrates the passivation layer and the remaining flat layer, and the projection of the through hole on the first substrate is located within the projection of the groove on the first substrate.

6 . The array substrate according to claim 5 , wherein the pixel driving film layer comprises: a plurality of gate lines arranged along a first direction on the surface of the first substrate, a plurality of gate lines arranged along a second direction. 7 . a data line and a thin film transistor located in a region defined by the gate line and the data line, the first direction intersects the second direction, wherein the pixel electrode layer passes through the groove and the through hole connected to the drain of the thin film transistor.

7 . The array substrate according to claim 6 , wherein a cross section of the groove and the through hole perpendicular to the first substrate and along the extending direction of the gate line is a trapezoid, and the The short side of the trapezoid is located between its long side and the first substrate, the long side of the trapezoid is the longer side in a group of parallel sides of the trapezoid, and the short side of the trapezoid is the The shorter side of a set of parallel sides of a trapezoid.

8 . The array substrate according to claim 7 , wherein the thickness difference between the through hole and the passivation layer in a direction perpendicular to the first substrate is determined by a preset formula; 9 .

The preset formula is: Wherein, D2 is the thickness difference between the through hole and the passivation layer in the direction perpendicular to the first substrate; L1≤3.5μm, is the length of the long side of the through hole; L2 is the length of the through hole The length of the short side, the value range of which is 0 μm-L1, excluding the endpoint value; θ is the supplementary angle of the inner angle on one side of the short side of the through hole.

9 . The array substrate according to claim 5 , wherein the length of the bottom surface of the groove on both sides of the through hole is greater than the thickness of the passivation layer in a direction parallel to the first substrate. 10 .

10. A display panel, comprising an array substrate and an opposite substrate disposed opposite to each other, wherein the array substrate is the array substrate according to any one of claims 5-9.

11. A display device, comprising at least one display panel according to claim 10.