CN106158859A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device, comprising: a substrate; a first support layer and a second support layer on the substrate; the first nanowire and the second nanowire are made of different channel materials and are sequentially and alternately arranged in a direction perpendicular to the substrate. The invention forms the nanowire channel comprising different materials, the nanowires of different materials are formed on the supporting layer and are alternately arranged in the direction vertical to the substrate, the nanowire channel can be used for forming different types of devices, the performance of the devices is improved, and the process is simple and convenient and easy to integrate.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention belongs to the field of semiconductor manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof.

Background technique

With the high integration of semiconductor devices, the channel length of MOSFET continues to shorten, and a series of effects that can be ignored in the long channel model of MOSFET become more and more significant, and even become the dominant factor affecting the performance of the device. This phenomenon is collectively called short channel road effect. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio.

At present, UT-SOI (Ultra Thin-SOI, ultra-thin silicon-on-insulator) device and FinFET (fin field effect transistor) device are proposed to solve the short channel effect. However, the cost of UT-SOI is extremely high, and there is a problem of self-heating, and with the improvement of integration, the manufacture of UT-SOI devices is becoming more and more difficult. For FinFET devices, the driving current is effectively increased. However, as the integration level increases, the fins become thinner and thinner, which is easy to collapse during the manufacturing process and cannot be further miniaturized. At the same time, in order to further improve the mobility of the device, it will be Introduce new channel materials, and in the manufacturing process of integrated circuits, it is necessary to integrate different channel materials for NMOS and PMOS to improve their mobility respectively. How to realize the integration of different channel materials is one of the current device manufacturing processes. challenge.

Contents of the invention

The object of the present invention is to overcome the deficiencies in the prior art and provide a semiconductor device and a manufacturing method thereof.

To achieve the above object, the technical solution of the present invention is:

A semiconductor device comprising:

Substrate;

a first support layer and a second support layer on the substrate;

The first nanowire on the sidewall of the first support layer, and the second nanowire on the sidewall of the second support layer, wherein the first nanowire and the second nanowire have different channel materials, and the first nanowire and the second nanowire have different channel materials. The first nanowire and the second nanowire are arranged alternately along the direction perpendicular to the substrate.

Optionally, the first support layer and the second support layer are an integrated first dielectric layer, and the first nanowires and second nanowires are respectively formed on two opposite sides of the first dielectric layer.

Optionally, the first supporting layer is a first back gate insulating layer, the second supporting layer is a second back gate insulating layer, and a common back gate is formed between the first back gate insulating layer and the second back gate insulating layer. .

Optionally, a first doped region formed in the substrate is further included, and the common back gate is formed on the first doped region.

Optionally, the first supporting layer is a first back gate insulating layer, the second supporting layer is a second back gate insulating layer, and further includes: a first back gate on the other side wall of the first back gate insulating layer , the second back gate on the other side wall of the second back gate insulating layer, and the first isolation between the first back gate and the second back gate.

Optionally, it further includes a first well region and a second well region formed in the substrate, the first back gate is formed on the first well region, and the second back gate is formed on the second well region.

Optionally, the material of the first nanowire includes: Si, Ge, SiGe or a III-V compound semiconductor material, and the material of the second nanowire includes: SiGe, Ge or a III-V compound semiconductor material.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

provide the substrate;

forming alternate stacks in which the first channel material and the second channel material are sequentially stacked on the substrate;

A groove is formed in the alternate stacking, and the two sides of the groove are respectively the first stack and the second stack;

forming a first support layer and a second support layer on opposite sidewalls of the trench;

First nanowires including only the first channel material are formed in the first stack, and second nanowires including only the second channel material are formed in the second stack.

Optionally, the step of respectively forming the first support layer and the second support layer on the opposite side walls of the trench includes: filling the trench with a first dielectric material layer to form an integrated first support layer and second support layer layer.

Optionally, also include:

forming a dummy gate stack covering the first nanowire and the second nanowire;

Covering both sides of the dummy gate stack to form an interlayer dielectric layer;

removing the dummy gate stack and the first dielectric material layer;

Form a replacement gate.

Optionally, the step of respectively forming the first support layer and the second support layer on the opposite side walls of the trench includes:

Forming a first back gate insulating layer and a second back gate insulating layer on opposite side walls of the trench respectively, the first back gate insulating layer and the second back gate insulating layer are respectively a first support layer and a second support layer;

It also includes: filling to form a common back gate in the trench.

Optionally, the step of respectively forming the first support layer and the second support layer on the opposite side walls of the trench includes:

Forming a first back gate insulating layer and a second back gate insulating layer on opposite side walls of the trench respectively, the first back gate insulating layer and the second back gate insulating layer are respectively a first support layer and a second support layer;

It also includes: forming a first back gate on the sidewall of the first supporting layer, and forming a second back gate on the sidewall of the second supporting layer;

Filling is performed to form a first isolation in the trench.

Optionally, the step of forming grooves in the alternate stacking includes:

forming a first mask layer on the alternating stack;

forming mask spacers on sidewalls of the first mask layer;

Using the first mask layer and the mask spacer as a mask, etching the alternate stacks to form trenches, first stacks and second stacks;

The steps of forming the first nanowire and the second nanowire include:

removing the first mask layer;

Using the sidewall mask as a mask, etching the first stack and the second stack to form a first nanowire stack and a second nanowire stack respectively;

The second channel material in the first nanowire stack and the first channel material in the second nanowire stack are respectively removed to form first nanowires and second nanowires, respectively.

Optionally, the steps of forming the first nanowire and the second nanowire include:

patterning the first stack and the second stack to form a first nanowire stack and a second nanowire stack, respectively;

removing a portion of the thickness of the semiconductor substrate on and below the first nanowire stack, and removing a portion of the thickness of the semiconductor substrate on and below the second nanowire stack;

Filling with a second insulating material;

removing a partial thickness of the second isolation material on one side of the first nanowire stack, simultaneously removing the second channel material in the first nanowire stack, and removing a partial thickness of the second isolation material on one side of the second nanowire stack, and simultaneously removing The first channel material in the second nanowire stack to respectively form the first nanowire, the second nanowire and the second isolation.

The semiconductor device and its manufacturing method of the present invention form nanowire channels including different materials, and the nanowires of different materials are formed on the support layer and arranged alternately in the direction perpendicular to the substrate, which can be used to form different types of devices , improve the performance of the device, and the process is simple and easy to integrate.

Description of drawings

In order to more clearly illustrate the technical solutions implemented by the present invention, the following will briefly introduce the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

FIG. 1 shows a schematic diagram of a three-dimensional structure of a semiconductor device according to Embodiment 1 of the present invention;

FIG. 2 is a schematic cross-sectional structure diagram of the semiconductor device of FIG. 1;

3-18 are schematic cross-sectional structural diagrams of devices in various manufacturing processes of manufacturing semiconductor devices according to the method of Embodiment 1 of the present invention;

19 is a schematic diagram of a three-dimensional device structure of a semiconductor device manufactured according to the method of Embodiment 1 of the present invention after depositing gate materials;

20 is a schematic diagram of a three-dimensional cross-sectional structure of a semiconductor device manufactured according to the method of Embodiment 1 of the present invention after forming a gate and sidewalls. The cross-section is along the direction of the gate, and the viewing angle is one end of the gate;

21 is a schematic diagram of a three-dimensional cross-sectional device structure of a semiconductor device manufactured according to the method of Embodiment 1 of the present invention after forming source and drain regions. The cross-section is along the direction of the gate, and the viewing angle is the opposite end of the gate;

22 is a schematic diagram of a device cross-sectional structure of a semiconductor device manufactured according to the method of Embodiment 1 of the present invention after forming an interlayer dielectric layer, the cross-section is along the direction of the gate, and the viewing angle is the opposite end of the gate;

FIG. 23 is a schematic plan view of the top plan structure of the semiconductor device manufactured according to the method of Embodiment 1 of the present invention after the contact is formed;

Fig. 24 is a schematic cross-sectional structure diagram along the AA direction of Fig. 23;

25-26 are schematic cross-sectional structural diagrams of devices during the manufacturing process of manufacturing semiconductor devices according to the method of Embodiment 2 of the present invention;

27-28 are schematic cross-sectional structural diagrams of the semiconductor device during the manufacturing process according to the method according to the third embodiment of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Referring to Figures 1 and 2, and Figures 26 and 28, Figure 1 is a perspective view of a semiconductor device according to Embodiment 1 of the present invention, Figure 2 is a schematic cross-sectional structure diagram of Figure 1, and Figures 26 and 28 are respectively Embodiment 2 and a schematic cross-sectional structure of a semiconductor device in Embodiment 3, the semiconductor device includes: a substrate 100; a first support layer and a second support layer on the substrate 100; a first nanowire on a side wall of the first support layer 110, and the second nanowire 120 on the side wall of the second support layer, wherein the first nanowire 110 and the second nanowire 120 have different channel materials, the first nanowire 110 and the second nanowire 120 Alternately arranged in sequence along the direction perpendicular to the substrate.

In an embodiment of the present invention, the first support layer and the second support layer respectively provide supports for the first and second nanowires, so that other surfaces of the nanowires are exposed, and more surfaces of the nanowires can be used as channels, The operating current of the device is increased, and since two different channel materials are integrated, it can be used for the integration of different types of devices, further improving the performance of devices in the system. For example, covering the first gate stack and the second gate stack on the exposed surfaces of the first nanowire and the second nanowire respectively, and forming source and drain regions respectively at both ends of the first nanowire and the second nanowire, thereby forming an integrated CMOS and NMOS nanowire devices.

The first support layer and the second support layer can be provided by other components of the device, and simultaneously have a support function. In some embodiments, as shown in FIG. 1 and FIG. 2, the first supporting layer is a first back gate insulating layer 145-1, 146-1, and the second supporting layer is a second back gate insulating layer 145-2. , 146-2, at the same time, the first back gate 162 on the other side wall of the first back gate insulating layer 145-1, 146-1, the other side of the second back gate insulating layer 145-2, 146-2 The second back gate 160 on the wall, the first isolation 110 is formed between the first back gate 162 and the second back gate 162 . In the device of this embodiment, the first and second back gate insulating layers are stacked, including oxide layers 145-1, 145-2 and nitride layers 146-1, 146-2, wherein the oxide layer It is a thin layer with a thickness of 1nm or thinner. The first back gate 162 and the second back gate 160 are covered with an insulating layer 159, such as a dielectric material of silicon nitride, which can be used on the first back gate 162 and the second back gate. A first well region 104 and a second well region 102 are respectively formed in the substrate below 160 , and the electrical connection of the back gate is realized by forming contacts on the first well region 104 and the second well region 102 . In this embodiment, the first nanowire and the second nanowire form respective back gates, and the threshold voltage of the back gate is adjusted by the respective back gates, which is beneficial to accurately adjust the threshold voltage of the device and further improve the performance of the device.

In some other embodiments, as shown in FIG. 26, the first supporting layer is the first back gate insulating layer 145-1, 146-1, and the second supporting layer is the second back gate insulating layer 145-2, 146. -2. At the same time, a common back gate 161 is formed between the first back gate insulating layer and the second back gate insulating layer, and an insulating layer 141 is formed on the common back gate 161, such as a dielectric material of silicon nitride, which can be used A first doped region 103, such as an N-type well region, is formed in the substrate under the common back gate 161, and a contact is formed on the first doped region 103 to realize the electrical connection of the common back gate. In this embodiment, the threshold voltage of the back gate is adjusted by the adjacent nanowires through the same back gate, and the structure is simpler.

In some other embodiments, as shown in FIG. 28, the first support layer and the second support layer are first dielectric layers 147, 163, and the first dielectric layer may be a single-layer or multi-layer structure. In this embodiment , the first dielectric layer is a stack of oxide layer 147 and nitride layer 163, the oxide layer is a thin layer with a thickness of 1 nm or less, and the first dielectric layer is used as the first nanowire 110 and the second nanowire The isolation between 120, at the same time, its two sides provide support for the first nanowire and the second nanowire.

In an embodiment of the present invention, the first nanowire 110 is formed on the first device region 1001, the second nanowire 120 is formed on the second device region 1002, and the first nanowire 110 and the second nanowire 120 use different The channel material is used to form different types of devices to meet the integration of high-performance devices. The first nanowire 110 is, for example, the channel material used to form N-type devices, which helps to improve the carrier mobility of N-type devices , such as Si, Ge, SiGe or III-V compound semiconductor materials, etc., the second nanowire 120 is, for example, a channel material for forming a P-type device, and these materials help to improve the carrier mobility of the P-type device rate, for example, can be SiGe, Ge or III-V compound semiconductor materials, etc.; for the embodiments of the present invention, the first nanowire material of the N-type device is preferably Si, and the second nanowire material of the P-type device is SiGe, However, other suitable materials with mutual selectivity are not excluded.

In order to better understand the technical solutions and technical effects of the present invention, the following will describe the formation methods of specific embodiments in detail.

Embodiment one

First, in step S101 , a substrate 100 is provided, as shown in FIG. 3 .

In the embodiment of the present invention, the substrate may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) and the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other epitaxial Structures, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate is a bulk silicon substrate.

In this embodiment, well regions for forming N-type devices such as NMOS devices and P-type devices such as PMOS devices have been formed in the substrate 100, and p-wells can be formed in the N-type device regions by performing ion implantation respectively. , forming an n-well in the P-type device region. Specifically, as shown in FIG. 3 , the implantation of p-type impurities such as B and the like can be performed first to form the first well region 104 in the first device region 1001 of the substrate 100, and then the implantation of n-type impurities such as P or As can be performed. implantation, forming a second well region 102 in the second device region 1002 of the substrate 100, in the embodiment of the present invention, the first well region 104 and the second well region 102 are formed over the entire device region, and the device region includes the subsequent Contacts can be formed on the formed back gate and well regions 102 and 104 so as to realize the electrical connection of the back gate.

Next, in step S102 , an alternate stack in which the first channel material 110 and the second channel material 120 are sequentially stacked is formed on the substrate 100 , as shown in FIG. 3 .

In this embodiment, the first channel material is a channel material for N-type devices, such as Si, etc., and the second channel material is a channel material for P-type devices, such as SiGe, etc., the two types The layer number and thickness of the channel material can be set as required. As shown in FIG. 1 , the first channel material 110 and the second channel material 120 are epitaxially alternately epitaxially on the substrate 100 to form a four-layer stack, and the thickness of each layer may be 5-15 nm.

Then, in step S103 , trenches 142 are formed in the stack, as shown in FIG. 6 .

First, a cap layer 130 and a first mask layer 132 are sequentially formed on the stack, as shown in FIG. 3 .

The cover layer 130 is used as an etching stop layer in subsequent steps, and plays a role in protecting the upper surface of the nanowire stack, for example, it can be a silicon oxide layer with a thickness of 5-15nm, and the first mask layer can be a stacked structure, including a polysilicon layer 132 and a silicon nitride layer 134, the thickness of the polysilicon layer 132 can be 50-200nm, the thickness of the silicon nitride layer 134 can be 50-200nm, and the silicon nitride layer 134 of the first mask layer A photoresist layer 136 is formed thereon.

Next, under the mask of the photoresist layer 136, the first mask layer is etched, such as by RIE (Reactive Ion Etching) method for etching, and the etching stops on the cap layer 130, thereby forming a pattern Then, the photoresist layer 136 is removed.

Then, mask sidewalls 140 are formed on the sidewalls of the first mask layers 132 and 134 , as shown in FIG. 5 . The mask sidewall 140 can be formed by using a sidewall process, and the mask sidewall material is deposited first, such as a silicon nitride material, with a thickness of 3-30nm, and then RIE etching is performed, and only the first mask Mask sidewall materials remain on the sidewalls of the film layers 132, 134, thereby forming a mask sidewall 140, which is a mask layer for subsequent formation of nanowires, and the width of the mask sidewall, namely The thickness at the time of deposition substantially defines the width of the subsequently formed nanowires.

Next, using the first mask layers 132, 134 and the mask sidewall 140 as a mask, etch the nanowire stack, for example, RIE can be used to sequentially etch the capping layer 130, the nanowire stack, and the partial-thickness substrate. Etching, as shown in FIG. 6 , thereby forming a groove 142 in the nanowire stack, the two sides of the groove are the nanowire stack after the first patterning, that is, the first stack 150 and the second stack 152, this In the embodiment of the invention, the first stack 150 is a nanowire stack formed on the first device region 1001, the second stack 152 is a nanowire stack formed on the second device region 1002, and the trench exposes the first well region 104 and the second well region 102 , the trench 142 is used for forming a back gate and isolation.

Then, in step S104 , back gate dielectric layers 145 , 146 , back gates 160 , 162 and a first isolation 164 between the back gates are sequentially formed in the trench 142 , as shown in FIG. 10 .

Specifically, firstly, the back gate dielectric layer is deposited, in order to ensure the good connection between the subsequently formed nanowires and the back gate dielectric layer, avoid the falling off of the nanowires in the subsequent etching step, and at the same time ensure that the nanowires are free from nitride stress effects. In this embodiment, a back gate dielectric layer with an oxide layer 145 and a nitride layer 146 laminated is used, and the back gate dielectric layer can be formed by using a sidewall process, and a thermal oxidation process is first performed to form an oxide layer with a thickness of 1 nm or less. 145, and then, deposit a thicker nitride layer 146, and perform RIE etching, thereby forming a back gate dielectric layer in which the oxide layer 145 and the nitride layer 146 are stacked on the sidewall of the trench, as shown in Figure 7 shown. Next, form the back gate, you can continue to use the side wall process to form the back gate, first deposit the back gate material 148 of polysilicon, as shown in Figures 8 and 9, at this time, you can perform ion implantation with an angle, respectively for the first The back gate 162 of the device region 1001 and the back gate 160 of the second device region 1002 are implanted with different ions to adjust the threshold voltages of the back gates of the first type device and the second type device respectively. A back gate is formed in the trench and on the sidewall of the back gate dielectric layer, and the back gate may include the back gate 162 of the first device region and/or the back gate 160 of the second device region. Then, fill the isolation material, such as silicon nitride, and perform a planarization process, such as CMP (Chemical Mechanical Polishing), to remove the excess isolation material outside the trench, and further planarize to further remove the first mask. The silicon nitride layer 134 in the film layer is exposed until the polysilicon layer 132 in the first mask layer is exposed. In this embodiment, the polysilicon layer 132 is a CMP stop layer, as shown in FIG. 10 . In this way, two back gates 160, 162 and a first isolation 164 between the back gates are formed in the trench, and the structures of the two back gates can respectively control the back gate threshold voltage of the corresponding device.

Next, in step S105, a first nanowire 110 comprising only the first channel material is formed in the first stack, and a second nanowire 120 comprising only the second channel material is formed in the second stack, referring to FIG. 18 shown.

First, use the sidewall mask 140 as a mask to etch the first stack 150 and the second stack 152. For example, the method of RIE can be used to etch until the surface of the substrate is exposed, so that the first device region 1001 A first nanowire stack 170 is formed, and a second nanowire stack 172 is formed on the second device region 1002 , as shown in FIG. 11 .

Then, only the first nanowires 110 remain in the first nanowire stack 170, and only the second nanowires 120 remain in the second nanowire stack 172, thereby forming first-type device trenches on the first device region 1001 respectively. The first nanowire 110 of the channel material is formed, and the second nanowire 120 of the channel material of the second type device is formed on the second device region 1002 for integrating different types of devices, as shown in FIG. 18 .

Specifically, firstly, protective sidewalls 174 are formed on the sidewalls of the first nanowire stack 170 and the second nanowire stack 172, such as silicon oxide protective sidewalls, which can be formed by a sidewall process. deposition, followed by RIE etching to form protective spacers 174 . Then, under the cover of the protective sidewall 174, continue to etch the substrate 100 with a partial thickness, and form a sinking region 175 under the nanowire stacks 170, 172. As shown in FIG. 12, the sinking region 175 is used to form Separation between nanowires and substrate.

Next, filling is performed so as to remove the nanowire stacks in the first device region and the second device region respectively, and only keep the nanowire material of the device type in this region. The filling material can be selected according to specific needs. In this embodiment, a dielectric material is preferred, so that, at the same time, a second isolation can be formed in the sinking area.

Specifically, first fill the first dielectric material 176 such as silicon dioxide, and perform planarization, as shown in FIG. 13; then, as shown in FIG. 14, cover the photoresist layer 182 on the first device region 1001, Etching removes the first dielectric material 176 of the second device region 1002 in a partial thickness, and the etching stops under the second nanowire stack. At this time, the first dielectric material remains in the sinking region, thereby forming the second device region 1002 Next, remove the protective spacer 174 of the second nanowire stack, and further selectively remove the first channel material 110 in the second nanowire stack, thereby forming a Second nanowire 120; Next, remove the photoresist layer 182 on the first device region 1001, continue to fill the second dielectric material 182, such as silicon dioxide, and planarize, and form a photoresist on the second device region 1002 Resist layer 184, and then, etch and remove the first dielectric material 176 of the first device region 1001 with a partial thickness, and stop the etching under the first nanowire stack. At this time, the first dielectric material remains in the sinking region, In this way, the second isolation 180 of the first device region is formed, and then, the protective spacer 174 of the first nanowire stack is removed, and the second channel material 120 in the first nanowire stack is further selectively removed, so that, at the A first nanowire 110 is formed in one device region, as shown in FIG. 15 , and then the photoresist layer 184 on the second device region is removed. Next, releasing the first nanowire and the second nanowire, exposing other surfaces except the supporting surface with the back gate dielectric layer. In order to be easier to control the process, the release of the nanowires is realized through the following steps. First, continue to fill the second dielectric material 182 and perform planarization, as shown in FIG. 16 , and then, anisotropic etching removes the second Dielectric material 182 until the second isolation 180, as shown in FIG. 17 , and then wet etching can be used to remove the second dielectric material 182 between the cap layer 130 and the nanowires. Of course, at this time, the second isolation with a partial thickness 180 will also be removed, thereby releasing the first nanowire 110 and the second nanowire 120 to form the first nanowire 110 and the second nanowire 120 in the first device region 1001 and the second device region 1002, respectively, as shown in FIG. 18.

So far, the structure of the first nanowire and the second nanowire with two different channel materials has been formed, and the isolation between devices has been formed on the nanowire structure. On the basis of this structure, the desired type can be continuously manufactured. device.

The following will take the formation of a CMOS device on the above nanowire structure as an example to describe in detail the embodiment of respectively forming NMOS and PMOS devices on the above nanowire structure.

In step S106, subsequent device processing is performed.

First, as shown in FIG. 19, the gate dielectric layer 190 is deposited, which can be deposited by ALD. The material of the gate dielectric layer can be, for example, silicon oxide or a high-k dielectric material (which has a higher ratio than silicon dioxide. dielectric constant), the gate dielectric layer covers the three surfaces of the first nanowire 110 and the second nanowire 120, such as HfO ₂ in a specific embodiment, the thickness can be 0.8-1.5nm, then, as shown in Figure 20 As shown, the gate material 192 is covered, such as polysilicon, and then patterned to form a gate dielectric layer 190 covering the three surfaces of the first nanowire 110 and the second nanowire 120, and the gate on the gate dielectric layer 190 192, and then, a gate spacer 194 on the sidewall of the gate 192, the spacer is, for example, silicon nitride.

Next, a source-drain region is formed on the first nanowire 110 and the second nanowire 120 on both sides of the gate 192. Angled ion implantation can be used to form a source-drain region on the first nanowire 110 and the second nanowire 120 respectively. Doping with the desired type of impurity to form the source and drain regions. In a preferred embodiment, the epitaxial growth and in-situ doping can also be used to form the source and drain regions, so as to further increase the mobility of carriers in the source and drain regions and improve the performance of the device. In a more preferred embodiment, the source and drain regions of the required stress type can be grown on the first nanowire 110 and the second nanowire 120 respectively, and for the nanowire in the N-type device region, a material with tensile stress can be grown on it, Such as Si:C, for the nanowires in the P-type device region, a material with compressive stress, such as SiGe, is grown on it. In a specific embodiment, the second device region is first covered, and Si:C is grown on the first nanowire 110, wherein the atomic percentage of C can be 0.2-2%, as shown in FIG. 21 , in the first device region A source-drain region 196 of tensile stress is formed on the first nanowire 110, and then, the second device region is exposed and the first device region is covered, and SiGe is grown on the second nanowire 120, and the atomic percentage of Ge may be 15- 75%, a compressive source and drain region 197 is formed on the second nanowire in the second device region, and then an interlayer dielectric layer 198 is formed covering the source and drain regions 196 and 197, as shown in FIG. 22 .

In the gate-front process, the device structure is completed so far, and the contact and interconnect structure processing processes can be performed subsequently.

In the gate last process, further, the gate 192 and the gate dielectric layer 190 can be removed, and the gate dielectric layer and the replacement gate 1008 can be re-formed, and the gate dielectric layer and the replacement gate 1008 can be respectively formed on the first device region and the second device region. Alternative gates of different metal materials to tune the work function of N-type and P-type devices, respectively.

Then, the contact can be formed. After the contact hole is formed, a conductive material, such as W, Cu, etc., is filled in the contact hole and planarized to form the gate contact 1010, the first back gate contact 1015, the second back gate contact The gate contact 1016 , the source region contacts 1014 , 1013 and the drain region contact 1012 are shown in FIG. 23 (top view) and FIG. 24 (the cross-sectional schematic diagram of FIG. 23 ). Then, other interconnection structures can be continued to be completed, wherein, the first back gate contact 1015 is formed on the first well region 104 of the first device region 1001, and the second back gate contact 1016 is formed on the first well region 104 of the second device region 1002. On the second well region 102 , the back gate contacts are respectively drawn out through the well regions connected to the back gate.

So far, the device of Embodiment 1 of the present invention has been formed. In this method, nanowires of different materials are respectively formed as NMOS and PMOS channels, and NMOS and PMOS devices are respectively integrated on them to realize different channel The device integration of the material improves the performance of the device, and the process is simple and easy to integrate. In addition, the first nanowire and the second nanowire form respective back gates, and the threshold voltage of the back gate is adjusted by the respective back gates, which is beneficial to accurately adjust the threshold voltage of the device and further improve the performance of the device.

Embodiment two

In this embodiment, only the differences from the first embodiment are described, and the same parts as the first embodiment will not be repeated.

First, in step S201, a substrate 100 is provided, as shown in FIG. 25 .

In this embodiment, a first doped region 103 has been formed in the substrate 100, and the first doped region 103 may be an N-type well region, which may be formed by ion implantation, such as implanting P or As. The first doped region 103, on which a contact can be drawn out subsequently, is used to realize the electrical connection of the back gate.

Next, in step S202 , an alternate stack in which the first channel material 110 and the second channel material 120 are sequentially stacked is formed on the substrate 100 , as shown in FIG. 3 .

This step is the same as step S102 in the first embodiment.

Then, in step S203 , trenches 142 are formed in the stack, as shown in FIG. 6 .

This step is the same as step S103 in the first embodiment.

Next, in step S204 , the back gate dielectric layers 145 , 146 and the back gate 161 are sequentially formed in the trench 142 , as shown in FIG. 25 .

Specifically, firstly, the back gate dielectric layer is deposited, in order to ensure the good connection between the subsequently formed nanowires and the back gate dielectric layer, avoid the falling off of the nanowires in the subsequent etching step, and at the same time ensure that the nanowires are free from nitride stress effects. In this embodiment, a back gate dielectric layer with an oxide layer 145 and a nitride layer 146 laminated is used, and the back gate dielectric layer can be formed by using a sidewall process, and a thermal oxidation process is first performed to form an oxide layer with a thickness of 1 nm or less. 145, and then, deposit a thicker nitride layer 146, and perform RIE etching, thereby forming a back gate dielectric layer in which the oxide layer 145 and the nitride layer 146 are stacked on the sidewall of the trench, as shown in Figure 7 shown.

Next, fill the back gate material, such as polysilicon, after depositing the back gate material, perform a planarization process, such as CMP, and then remove part of the thickness of the back gate material to form a common back gate 161 in the trench, as shown in Figure 25 As shown, next, deposit an insulating material, such as silicon nitride, and perform a planarization process, such as CMP, until the polysilicon layer 132 in the first mask layer is exposed, thereby forming an insulating layer 141 on the common back gate .

Then, in step S205, a first nanowire 110 comprising only the first channel material is formed in the first stack, and a second nanowire 120 comprising only the second channel material is formed in the second stack, referring to FIG. 26 shown.

This step is the same as step S105 in the first embodiment.

So far, the structure of the first nanowire and the second nanowire with two different channel materials in this embodiment is formed, and the adjacent nanowires use a common back gate to adjust the threshold voltage. Based on this structure , you can proceed to fabricate the desired type of device.

Similar to step S106 in the first embodiment, devices can be processed on the nanowire structure in this embodiment, and subsequent devices can be formed using a gate-first process or a gate-last process.

Embodiment Three

In this embodiment, only the differences from the first embodiment are described, and the same parts as the first embodiment will not be repeated.

First, in step S301, a substrate 100 is provided, as shown in FIG. 27 .

Different from the first embodiment, the substrate 100 of this embodiment does not form a well region.

Next, in step S303 , trenches 142 are formed in the stack, as shown in FIG. 6 .

This step is the same as step S103 in the first embodiment.

Then, in step S304 , the first dielectric layers 147 and 163 are sequentially formed in the trench 142 , as shown in FIG. 27 .

In this embodiment, the first dielectric layer may be a single layer or a stack of layers, which not only serves as a support for the first nanowire and the second nanowire, but also serves as an isolation between the first nanowire and the second nanowire.

Specifically, first, a thermal oxidation process may be performed to form an oxide layer 147 on the inner surface of the trench, the thickness of the oxide layer may be 1 nm or less, then nitride deposition is performed, and then planarization is performed process, such as CMP, until the polysilicon layer 132 in the first mask layer is exposed, thereby forming the first dielectric layer stacked by the oxide layer 147 and the nitride layer 163 in the trench, and the first dielectric layer is the first dielectric layer The isolation between a nanowire and a second nanowire is shown in FIG. 27 .

Next, in step S305, a first nanowire 110 comprising only the first channel material is formed in the first stack, and a second nanowire 120 comprising only the second channel material is formed in the second stack, referring to FIG. 28 shown.

This step is the same as step S105 in the first embodiment.

So far, the structure of the first nanowire and the second nanowire with two different channel materials in this embodiment is formed, and the adjacent nanowires are separated. On the basis of this structure, it is possible to continue to manufacture the required type of device.

Similar to step S106 in the first embodiment, devices can be processed on the nanowire structure in this embodiment, and subsequent devices can be formed using a gate-first process or a gate-last process.

In some other embodiments in which the gate-last process is used to form subsequent devices, the following steps are used to perform the subsequent process: forming a dummy gate stack covering the first nanowire and the second nanowire; forming the first nanowire on both sides of the dummy gate stack The source and drain regions are respectively formed in the second nanowire; the two sides of the dummy gate stack are covered to form an interlayer dielectric layer; the dummy gate stack and the first dielectric layer are removed; and a replacement gate is formed. In the gate-last process of this embodiment, different from the first embodiment above, when removing the dummy gate stack, the first dielectric layer is removed at the same time, so that the first nanowire and the second nanowire can be completely released , that is, the surfaces of the gate regions of the first nanowire and the second nanowire are completely exposed, at this time, the first nanowire and the second nanowire are supported by the interlayer dielectric layer and/or the source-drain region, thus forming a replacement gate Finally, the replacement gate will completely surround the first nanowire and the second nanowire to form a fully surrounded nanowire device, further increasing the current of the channel and improving the performance of the device.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (14)

1. a semiconductor device, it is characterised in that including:

Substrate；

The first supporting layer on substrate and the second supporting layer；

The first nano wire on one sidewall of the first supporting layer, and on a sidewall of the second supporting layer Second nano wire, wherein, the first nano wire and the second nano wire have different channel material, and first Nano wire and the second nano wire are along being arranged alternately successively with substrate transverse direction.

Semiconductor device the most according to claim 1, it is characterised in that the first supporting layer and Two supporting layers are first medium layer, and the first nano wire and the second nano wire are respectively formed at first medium layer Two relative sides on.

Semiconductor device the most according to claim 1, it is characterised in that described first supporting layer Being the first backgate insulating barrier, the second supporting layer is the second backgate insulating barrier, the first backgate insulating barrier and It is formed with public backgate between two backgate insulating barriers.

Semiconductor device the most according to claim 3, it is characterised in that also include being formed at lining The first doped region at the end, public backgate is formed on the first doped region.

Semiconductor device the most according to claim 1, it is characterised in that described first supporting layer Being the first backgate insulating barrier, the second supporting layer is the second backgate insulating barrier, also includes: the first backgate is exhausted The first backgate on another sidewall of edge layer, the second backgate on another sidewall of the second backgate insulating barrier, The first isolation between first backgate and the second backgate.

Semiconductor device the most according to claim 5, it is characterised in that also include being formed at lining The first well region at the end and the second well region, the first backgate is formed on the first well region, the second backgate shape Become on the second well region.

7. according to the semiconductor device according to any one of claim 1-6, it is characterised in that first The material of nano wire includes: Si, Ge, SiGe or III-V compound semiconductor material, the second nano wire Material include: SiGe, Ge or III-V compound semiconductor material.

8. the manufacture method of a semiconductor device, it is characterised in that including:

Substrate is provided；

Substrate forms the first channel material and alternative stacked that the second channel material stacks gradually；

Described alternately build up in formed groove, groove both sides be respectively the first stacking and second stacking；

The relative sidewall of groove is formed the first supporting layer and the second supporting layer respectively；

The first nano wire only including the first channel material is formed in the first stacking, and at the second heap In folded, formation only includes the second nano wire of the second channel material.

Manufacture method the most according to claim 8, it is characterised in that in the relative side of groove The step forming the first supporting layer and the second supporting layer on wall respectively includes: fill first Jie in the trench Material layer, shape all-in-one-piece the first supporting layer and the second supporting layer.

Manufacture method the most according to claim 9, it is characterised in that also include:

Form the pseudo-grid stacking covering the first nano wire and the second nano wire；

Cover pseudo-grid stacking both sides, to form interlayer dielectric layer；

Remove pseudo-grid stacking and first medium layer；

Form replacement gate.

11. manufacture methods according to claim 8, it is characterised in that relative at groove The step forming the first supporting layer and the second supporting layer on sidewall respectively includes:

The first backgate insulating barrier and the second backgate insulating barrier is formed respectively on the relative sidewall of groove, First backgate insulating barrier and the second backgate insulating barrier are respectively the first supporting layer and the second supporting layer；

Also include: be filled with, to form public backgate in the trench.

12. manufacture methods according to claim 8, it is characterised in that relative at groove The step forming the first supporting layer and the second supporting layer on sidewall respectively includes:

The first backgate insulating barrier and the second backgate insulating barrier is formed respectively on the relative sidewall of groove, First backgate insulating barrier and the second backgate insulating barrier are respectively the first supporting layer and the second supporting layer；

Also include: on the sidewall of the first supporting layer, form the first backgate, at the sidewall of the second supporting layer Upper formation the second backgate；

It is filled with, to form the first isolation in the trench.

13. manufacture methods according to any one of-12 according to Claim 8, it is characterised in that in institute State and be alternately stacked the step of middle formation groove and include:

Described being alternately stacked is formed the first mask layer；

The sidewall of the first mask layer is formed mask side wall；

With the first mask layer and mask side wall for sheltering, be alternately stacked described in etching, with formed groove with And first stacking and second stacking；

The step forming the first nano wire and the second nano wire includes:

Remove the first mask layer；

With side wall mask for sheltering, etching the first stacking and the second stacking, to form the first nanometer respectively Line stacking and the second nano wire stacking；

Remove respectively in the second channel material in the first nano wire stacking and the second nano wire stacking First channel material, to form the first nano wire and the second nano wire respectively.

14. manufacture methods according to any one of-12 according to Claim 8, it is characterised in that formed The step of the first nano wire and the second nano wire includes:

Patterning the first stacking and the second stacking, to form the first nano wire stacking and the second nanometer respectively Line stacks；

Remove the first nano wire stacking side and Semiconductor substrate of lower segment thickness thereof, and removal Second nano wire stacking side and under the Semiconductor substrate of segment thickness；

Fill the second isolated material；

Remove the second isolated material of the first nano wire stacking side segment thickness, remove first simultaneously and receive The second channel material in rice noodle stacking, and remove the of the second nano wire stacking side segment thickness Two isolated materials, remove the first channel material in the second nano wire stacking, to form the respectively simultaneously One nano wire, the second nano wire and the second isolation.