CN106158786A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The insulating layer has an accommodation opening. The chip is arranged in the accommodating opening. The chip is provided with an active surface, a back surface opposite to the active surface and a side surface connecting the active surface and the back surface. The thermal interface material is filled in the accommodating opening to at least cover the side surface of the chip and expose the active surface. The redistribution layer and the heat dissipation cover body are respectively arranged at two sides of the insulation layer. The heat sink cover is thermally coupled to the chip via the thermal interface material. The redistribution layer covers the active surface of the chip and the thermal interface material, and is electrically connected with the chip. The semiconductor package has good heat dissipation efficiency.

Description

Semiconductor package and manufacturing method thereof

technical field

The present invention relates to a packaging body and its manufacturing method, and in particular to a semiconductor packaging body and its manufacturing method.

Background technique

In order to meet the requirements of light, thin and small electronic products, semiconductor packages, which are the core components of electronic products, are also developing in the direction of miniaturization. In recent years, the industry has developed a chip-scale package (Chip Scale Package, CSP for short) miniaturized semiconductor package, which is characterized in that the size of the aforementioned chip-scale package is approximately equal to the size of its chip or slightly larger than the size of its chip. size. On the other hand, in addition to miniaturization in size, the semiconductor package also needs to improve the integration (integrity) and the input/output terminals (Input/Output, referred to as I/O) for electrical connection with external electronic components such as circuit boards. ) to meet the high performance and high processing speed requirements of electronic products. In order to arrange more input/output terminals (I/O) on the limited area of the active surface of the chip, wafer-level semiconductor packages, such as Wafer Level Chip Scale Packaging (Wafer Level Chip Scale Packaging, referred to as WLCSP) came into being.

The conventional wafer-level chip size package is generally manufactured by firstly making the encapsulant coat the die back of the chip and the side surface connected to the die back through a molding process, and expose the active surface relative to the die back. Afterwards, a reconfiguration circuit layer is formed on the encapsulation compound and the active surface of the chip, and the input/output terminal (I/O) on the active surface of the chip is electrically connected to the reconfiguration circuit layer. Generally, the thickness of the encapsulant formed by the compression molding process is relatively thick, which is not conducive to the miniaturization of the WLCS package. In addition, due to the low thermal conductivity and poor heat dissipation effect of the encapsulant, most of the heat generated by the chip is transferred to the outside through the reconfiguration circuit. The heat dissipation area or heat dissipation path is limited, so the heat dissipation efficiency is not good. When the heat cannot be quickly transferred to the outside and accumulates inside the WLCSP, it is easy to cause warpage of the WLCSP.

Contents of the invention

The invention provides a semiconductor package and a manufacturing method thereof, which can produce a semiconductor package with good heat dissipation efficiency.

The invention provides a semiconductor packaging body, which includes an insulating layer, a chip, a thermal interface material, a heat dissipation cover and a reconfiguration circuit layer. The insulating layer has a receiving opening. The chip is disposed in the receiving opening. The chip has an active surface, a back surface opposite to the active surface, and a side surface connecting the active surface and the back surface. The thermal interface material is filled in the accommodating opening to at least cover the side surface of the chip and expose the active surface. The reconfiguration circuit layer and the heat dissipation cover are arranged on both sides of the insulating layer respectively, and the heat dissipation cover is thermally coupled with the chip through the thermal interface material. The reconfiguration circuit layer covers the active surface of the chip and the thermal interface material, and the reconfiguration circuit layer is electrically connected to the chip.

In an embodiment of the present invention, the above-mentioned thermal interface material covers the back surface and the side surface of the chip.

In an embodiment of the present invention, the heat dissipation cover is in contact with the insulating layer and the interface material.

In an embodiment of the present invention, the above-mentioned thermal interface material exposes the backside of the chip, and the heat dissipation cover is in contact with the insulating layer, the thermal interface material and the backside of the chip.

In an embodiment of the present invention, the above-mentioned insulating layer has a first surface and a second surface opposite to the first surface. The heat dissipation cover is arranged on the first surface, and the redistribution circuit layer is arranged on the second surface, and the backside of the chip is aligned with the first surface of the insulating layer.

In an embodiment of the present invention, the above-mentioned reconfiguration circuit layer includes at least one patterned conductive layer and at least one patterned dielectric layer stacked alternately.

In an embodiment of the present invention, the above-mentioned semiconductor package further includes a plurality of solder balls. These solder balls are electrically connected to the chip through the reconfiguration circuit layer.

The invention provides a method for manufacturing a semiconductor package, which includes the following steps. A heat dissipation cover is formed on the carrier. Forming an insulating layer on the heat dissipation cover has at least one accommodating opening to expose part of the heat dissipation cover. The chip is arranged in the receiving opening and the thermal interface material is filled in the receiving opening, so that the thermal interface material covers the chip and exposes the active surface of the chip. A reconfiguration circuit layer is formed on the insulating layer, the thermal interface material and the active surface of the chip, wherein the reconfiguration circuit layer is electrically connected to the chip.

In an embodiment of the present invention, the above-mentioned manufacturing method of the conductor package further includes forming a plurality of solder balls on the redistribution circuit layer, wherein the solder balls are electrically connected to the chip through the redistribution circuit layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the conductor package further includes separating the heat dissipation cover from the carrier.

The invention provides a method for manufacturing a semiconductor package, which includes the following steps. A heat dissipation material layer is formed on the carrier. An insulating material layer is formed on the heat dissipation material layer. The insulating material layer has a plurality of receiving openings to expose part of the heat dissipation material layer. A plurality of chips are respectively arranged in the receiving openings and the thermal interface material is filled in the receiving openings, so that the thermal interface material covers the chips and exposes the active surfaces of the chips. A reconfiguration circuit structure is formed on the insulating material layer, the thermal interface material, and the active surfaces of the chips, wherein the reconfiguration circuit structure includes a plurality of reconfiguration circuit layers, and each reconfiguration circuit layer is electrically connected to the corresponding chip.

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor package further includes forming multiple groups of solder balls on the reconfiguration circuit layers, wherein each group of solder balls is electrically connected to the corresponding chip through one of the reconfiguration circuit layers .

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor package further includes separating the heat dissipation material layer from the carrier.

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor package further includes cutting the heat dissipation material layer, the insulating material layer and the reconfiguration circuit structure along a predetermined cutting line to form a plurality of semiconductor packages.

Based on the above, the semiconductor package of the present invention can cover at least the side surface of the chip located in the accommodating opening of the insulating layer through the thermal interface material, and contact the thermal interface material with the heat dissipation cover, thus having good heat dissipation efficiency. On the other hand, the manufacturing method of the semiconductor package proposed by the present invention can manufacture the above-mentioned semiconductor package with good heat dissipation efficiency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1G show a manufacturing process of a semiconductor package according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a semiconductor package according to another embodiment of the present invention.

Explanation of reference signs:

10: carrier;

100, 100A: semiconductor package;

110: heat dissipation material layer;

110a: heat dissipation cover;

120: insulating material layer;

120a: insulating layer;

121: receiving opening;

121a: first surface;

122a: second surface;

130: chip;

131: active surface;

132: back;

133: side surface;

140: thermal interface material;

150: reconfigure the line structure;

151: Reconfigure the line layer;

151a, 151b: patterned conductive layer;

151c: patterning a dielectric layer;

B: solder ball;

D: spacing;

L: scheduled cutting line.

detailed description

1A to 1G illustrate the manufacturing process of a semiconductor package according to an embodiment of the present invention. Referring to FIG. 1A , a carrier 10 is provided first, and a heat dissipation material layer 110 is formed on the carrier 10 . For example, the carrier 10 can be a plate made of hard material or flexible material, or a release film (such as a thermal release adhesive film, an ultraviolet light release adhesive film or other suitable adhesive films), but the present invention is for The material of the carrier 10 is not limited in any way. Here, the heat dissipation material layer 110 is temporarily fixed on the carrier 10 by, for example, gluing, so as to facilitate subsequent manufacturing processes. In this embodiment, the heat dissipation material layer 110 may be made of aluminum, magnesium, copper, silver, gold or other metals or metal alloys with good thermal conductivity, or graphite or other non-metallic materials with good thermal conductivity.

Next, please refer to FIG. 1B, an insulating material layer 120 is formed on the heat dissipation material layer 110, wherein the material of the insulating material layer 120 can be polyimide (Polyimide), epoxy resin, silicon (Si), silicon oxide (SiO _x ) or other suitable insulating material. Here, the insulating material layer 120 may have a plurality of receiving openings 121 to expose part of the heat dissipation material layer 110 . For example, the insulating material layer 120 can be made by first forming a layer of insulating material on the heat dissipation material layer 110, and then forming the accommodating opening 121 in a specific area of the aforementioned insulating material through processes such as exposure and development or laser drilling. , to obtain a patterned insulating material layer 120 . Alternatively, the insulating material layer 120 with the accommodating opening 121 is directly formed on the heat dissipation material layer 110 by means of inkjet printing, screen printing, curtain printing, spray printing or dry film attachment, but the present invention There is no limitation on the fabrication method for forming the patterned insulating material layer 120 .

Next, please refer to FIG. 1C , a plurality of chips 130 are respectively disposed in the receiving openings 121 and filled with a thermal interface material 140 in the receiving openings 121, wherein the thermal interface material 140 can be thermally conductive glue, thermally conductive paste, or thermally conductive adhesive film. or thermal tape. It should be noted that the present invention does not limit the sequence of placing the chip 130 in the receiving opening 121 and filling the thermal interface material 140 in the receiving opening 121, for example, the thermal interface material 140 can at least cover the side surface of the chip 130 133 and the fabrication process that exposes the active surface 131 of the chip 130 is applicable.

In this embodiment, for example, first fill the thermal interface material 140 in the receiving opening 121, then place the chip 130 into the receiving opening 121 filled with the thermal interface material 140, and make the chip 130 relatively to the active surface The back surface 132 of the chip 131 maintains a distance D from the heat dissipation material layer 110 (that is, the back surface 132 of the chip 130 is not in contact with the heat dissipation material layer 110 ). In another embodiment, for example, the chip 130 is put into the receiving opening 121 first, so that the back surface 132 of the chip 130 is in contact with the heat dissipation material layer 110 . Next, fill the thermal interface material 140 into the receiving opening 121 along the gap between the side surface 133 of the chip 130 and the inner wall of the receiving opening 121 . In yet another embodiment, for example, the chip 130 is placed into the receiving opening 121 first, so that the back surface 132 of the chip 130 is in contact with the heat dissipation material layer 110 . Next, the thermally conductive tape or the thermally conductive adhesive film is pressed into the accommodating opening 121 by means of vacuum pressing. If necessary, the portion of the active surface 131 of the chip 130 covered by the thermally conductive tape or film is removed to expose the active surface 131 .

Next, please refer to FIG. 1D, a reconfiguration circuit structure 150 is formed on the insulating material layer 120, the thermal interface material 140, and the active surface 131 of each chip 130 by using a reconfiguration circuit process, wherein the reconfiguration circuit structure 150 includes a plurality of reconfiguration lines layer 151 , and each reconfiguration circuit layer 151 is electrically connected to the corresponding chip 130 . In detail, each reconfiguration circuit layer 151 includes alternately stacked patterned conductive layers 151a, 151b and patterned dielectric layer 151c, wherein each reconfiguration circuit layer 151 is an active mechanism for connecting the corresponding chip 130 to the patterned conductive layer 151a. surface 131 , and part of the patterned conductive layer 151 a will be in contact with the thermal interface material 140 . On the other hand, the patterned dielectric layer 151c exposes the patterned conductive layer 151b. It should be noted that the reconfiguration circuit layer is, for example, a multi-layer circuit structure, and the number of layers of the circuit can be increased or decreased according to actual needs.

Next, please refer to FIG. 1E , perform ball planting and reflow (reflow) processes to form multiple groups of solder balls B on these reconfiguration circuit layers 151, wherein each group of solder balls B is respectively connected to the corresponding reconfiguration circuit layer 151. The conductive layer 151b is patterned to be electrically connected to the corresponding chip 130 . Generally, the material of the solder ball B may include tin or tin-lead alloy or lead-free solder. Next, please refer to FIG. 1F , the carrier 10 is removed from the heat dissipation material layer 110 , that is, the heat dissipation material layer 110 and the carrier 10 are separated.

Finally, referring to FIG. 1F and FIG. 1G at the same time, a singulation process is performed along the predetermined cutting line L between any two adjacent chips 130 to form a plurality of semiconductor packages 100 . For example, a cutter or a laser cuts the patterned dielectric layer 151c passing through the heat dissipation material layer 110, the insulating material layer 120 and the reconfiguration circuit structure 150 along the predetermined cutting line L, mainly in order not to damage the solder balls B. in principle. So far, the fabrication of the semiconductor package 100 has been roughly completed, wherein the cut heat dissipation material layer 110 constitutes the heat dissipation cover 110a of the semiconductor package 100 , and the cut insulating material layer 120 constitutes the insulation layer 120a of the semiconductor package 100 .

Because in the manufacturing process of the semiconductor package 100, it can use the patterned insulating material layer 120 (that is, the insulating material layer 120 having a plurality of receiving openings 121) to replace the frame used in the existing compression molding process, Therefore, part of the manufacturing procedures and required auxiliary tools in the existing semiconductor package can be eliminated, thereby helping to reduce the packaging thickness of the semiconductor package 100 and reduce its manufacturing cost.

Please continue to refer to FIG. 1G , in this embodiment, the semiconductor package 100 includes a heat dissipation cover 110 a , an insulating layer 120 a , a chip 130 , a thermal interface material 140 and a reconfiguration circuit layer 151 . The chip 130 is disposed in the receiving opening 121 of the insulating layer 120a. The thermal interface material 140 is filled in the receiving opening 121 to cover the side surface 133 and the back surface 132 of the chip 130 and expose the active surface 131 . The reconfiguration circuit layer 151 and the heat dissipation cover 110a are respectively disposed on opposite sides of the insulating layer 120a. Since the heat dissipation cover 110a is in contact with the insulating layer 120a and the thermal interface material 140 but does not directly contact the back surface 132 of the chip 130, the present embodiment therefore The heat dissipation cover 110 a is thermally coupled to the chip 130 through a thermal interface material 140 , for example.

On the other hand, the reconfiguration circuit layer 151 covers the active surface 131 of the chip 130 and the thermal interface material 140, wherein the reconfiguration circuit layer 151 connects the active surface 131 of the chip 130 through the patterned conductive layer 151a to be electrically connected to the chip 130. connected, and part of the patterned conductive layer 151a will be in contact with the thermal interface material 140 . The solder balls B are respectively connected to the patterned conductive layer 151 b in the reconfiguration circuit layer 151 to be electrically connected to the chip 130 . Here, the solder balls B and the chip 13 are respectively located on opposite sides of the reconfiguration circuit layer 151 .

In this embodiment, the back surface 132 and the side surface 133 of the chip 130 are covered by the thermal interface material 140 , so the heat dissipation area of the chip 130 can be increased. Furthermore, the heat dissipation cover 110 a can be thermally coupled to the chip 130 through the thermal interface material 140 , so the heat generated by the chip 130 during operation can be quickly transferred to the outside through the thermal interface material 150 and the heat dissipation cover 110 a. In addition, since part of the patterned conductive layer 151a will be in contact with the thermal interface material 140, the heat generated in the reconfiguration circuit layer 151 can also be quickly transferred to the outside through the thermal interface material 140 and the heat dissipation cover 110a, or through Solder ball B passes to the outside world. Accordingly, the semiconductor package 100 is less likely to be warped due to heat accumulated inside it.

Other embodiments are listed below for illustration. It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 2 is a schematic diagram of a semiconductor package according to another embodiment of the present invention. Please refer to FIG. 2 , the semiconductor package 100A of this embodiment is substantially similar to the semiconductor package 100 of the above-mentioned embodiment, the main difference between the two is: the thermal interface material 140 of this embodiment exposes the back surface 132 of the chip 130, And the heat dissipation cover 110 a is in contact with the insulating layer 120 a , the thermal interface material 140 and the back surface 132 of the chip 130 . Specifically, the insulating layer 120a has a first surface 121a and a second surface 122a opposite to the first surface 121a, the heat dissipation cover 110a is disposed on the first surface 121a, and the redistribution circuit layer 151 is disposed on the second surface 122a , and the backside 132 of the chip 130 is, for example, aligned with the first surface 121a of the insulating layer 120a.

To sum up, the semiconductor package of the present invention can cover at least the side surface of the chip located in the receiving opening of the insulating layer through the thermal interface material, and contact the thermal interface material with the heat dissipation cover, so that the heat dissipation cover can pass through the thermal interface material. thermally coupled to the chip. In this way, the heat generated during the operation of the chip can be quickly transferred to the outside through the thermal interface material and the heat dissipation cover. In addition, since part of the patterned conductive layer will be in contact with the thermal interface material, the heat generated in the reconfiguration circuit layer can also be quickly transferred to the outside through the thermal interface material and the heat dissipation cover, or transferred to the outside through solder balls . Accordingly, the semiconductor package of the present invention has good heat dissipation efficiency and is not prone to warping due to heat.

On the other hand, the manufacturing method of the semiconductor package proposed by the present invention can not only produce the above-mentioned semiconductor package with good heat dissipation efficiency, but also utilize a patterned insulating material layer (that is, an insulating material with a plurality of receiving openings) Layer) to replace the frame used in the existing compression molding process, thereby eliminating part of the manufacturing process and the required auxiliary tools in the existing semiconductor package, so it helps to reduce the package thickness of the semiconductor package and reduce its production cost.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (15)

1. a semiconductor package body, it is characterised in that including:

Insulating barrier, has receiving opening；

Chip, is arranged in described receiving opening, and described chip has active surface, relative to described master Move the back side on surface and connect the side surface of described active surface and the described back side；

Thermal interface material, is filled in described receiving opening to be at least coated with the described side surface of described chip And expose described active surface；

Heat radiation lid；And

Reconfiguration line layer, wherein said reconfiguration line layer and described heat radiation lid are respectively arranged at described The both sides of insulating barrier, described heat radiation lid is by described thermal interface material and described chip thermal coupling, and institute State reconfiguration line layer and be covered in the described active surface of described chip and described thermal interface material, and described Reconfiguration line layer is electrically connected with described chip.

Semiconductor package body the most according to claim 1, it is characterised in that described thermal interface material It is coated with the described back side of described chip and described side surface.

Semiconductor package body the most according to claim 2, it is characterised in that described heat radiation lid with Described insulating barrier and the contact of described thermal interface material.

Semiconductor package body the most according to claim 1, it is characterised in that described thermal interface material Expose the described back side of described chip, and described heat radiation lid and described insulating barrier, described hot interface material Material and the described rear-face contact of described chip.

Semiconductor package body the most according to claim 4, it is characterised in that described insulating barrier has First surface and the second surface relative with described first surface, described heat radiation lid is configured at described first On surface, and described reconfiguration line layer is configured on described second surface, and the described back of the body of described chip Face trims the described first surface in described insulating barrier.

Semiconductor package body the most according to claim 1, it is characterised in that described in reconfigure circuit Layer includes at least one patterned conductive layer and at least one pattern dielectric layer being alternately stacked.

Semiconductor package body the most according to claim 1, it is characterised in that also include:

Multiple soldered balls, are electrically connected with described chip by described reconfiguration line layer.

Semiconductor package body the most according to claim 7, it is characterised in that more described soldered ball and institute State chip and lay respectively at the both sides of described reconfiguration line layer.

9. the manufacture method of a semiconductor package body, it is characterised in that including:

Carrier is formed heat radiation lid；

Forming insulating barrier on described heat radiation lid, described insulating barrier has at least one receiving opening to expose Go out the described heat radiation lid of part；

Chip it is configured in described receiving opening and inserts thermal interface material in described receiving opening, So that described thermal interface material is coated with described chip and exposes the active surface of described chip；And

The described active surface of described insulating barrier, described thermal interface material and described chip is formed weight Configuration line layer, wherein said reconfiguration line layer is electrically connected with described chip.

The manufacture method of semiconductor package body the most according to claim 9, it is characterised in that also Including:

Described reconfiguration line layer is formed multiple soldered ball, more wherein said soldered ball pass through described in reconfigure Line layer is electrically connected with described chip.

The manufacture method of 11. semiconductor package body according to claim 10, it is characterised in that also Including:

Described heat radiation lid is made to separate with described carrier.

The manufacture method of 12. 1 kinds of semiconductor package body, it is characterised in that including:

Carrier is formed heat radiation material layer；

Forming insulation material layer in described heat radiation material layer, described insulation material layer has multiple receiving and opens Mouth is to expose the described heat radiation material layer of part；

Multiple chips it is respectively arranged in more described receiving opening and inserts heat in those accommodate opening Interface material, so that described thermal interface material is coated with those chips and exposes the active table of those chips Face；And

The active surface of described insulation material layer, described thermal interface material and those chips is formed weight Layout line line structure, wherein said reconfiguration line structure includes multiple reconfiguration line layer, and each described Reconfiguration line layer is electrically connected with corresponding chip respectively.

The manufacture method of 13. semiconductor package body according to claim 12, it is characterised in that also Including:

Forming many assembly weldings ball in those reconfiguration line layer, the most each assembly welding ball is respectively by a wherein weight Configuration line layer is electrically connected with corresponding chip.

The manufacture method of 14. semiconductor package body according to claim 13, it is characterised in that also Including:

Described heat radiation material layer is made to separate with described carrier.

The manufacture method of 15. semiconductor package body according to claim 12, it is characterised in that also Including:

Along predetermined cuts line cut described heat radiation material layer, described insulation material layer and described in reconfigure line Line structure, to form multiple semiconductor package body.