CN106158660A - Groove-shaped VDMOS manufacture method - Google Patents

Abstract

The invention provides a trench type VDMOS manufacturing method. The method includes: depositing a hard mask layer on the N-type epitaxial layer; performing photolithography and etching on the middle area of the hard mask layer to form a first trench window area; The area is etched to form the first groove in the N-type epitaxial layer; the P-type epitaxy is grown on the upper surface of the hard mask layer, the window area of the first groove and the first groove; the hard mask is removed by chemical mechanical polishing process The P-type epitaxy on the upper surface of the film layer, the P-type epitaxy in the hard mask layer and the first trench window area, so that the P-type ion region is formed in the first trench; in the N-type epitaxial layer, the P-type ion region is two A second trench is formed in part of the side regions; a gate oxide layer is formed on the upper surface of the N-type epitaxial layer and the inner surface of the second trench; a polysilicon layer is deposited on the gate oxide layer in the second trench; a trench type Body region, source region, dielectric layer and metal layer of VDMOS.

Description

Trench VDMOS Manufacturing Method

technical field

Embodiments of the present invention relate to the technical field of semiconductor device manufacturing, and in particular, to a method for manufacturing a trench-type VDMOS.

Background technique

Trench-type vertical double-diffused metal-oxide-semiconductor transistors (referred to as: trench-type VDMOS) are channeled by forming a vertical diffusion distance difference after source ion and bulk ion implantation, and are widely used in the field of switching power supply and synchronous rectification. Compared with the planar VDMOS, the internal resistance of the trench VDMOS is very small because the JFET area is eliminated. However, due to the small radius of curvature at the corner of the bottom of the trench in the trench VDMOS, the breakdown voltage of the trench VDMOS is relatively low.

In the prior art, in order to increase the breakdown voltage of the trench-type VDMOS, a method of implanting P-type ions into the region of the metal contact hole is mainly adopted. As shown in Figure 1, after implanting P-type ions in the region of the metal contact hole, the P-type ion implantation region 15 shares part of the field strength at the bottom of the second trench 7, weakening the field strength at the bottom of the second trench 7, and then Improved breakdown voltage. Wherein, the closer the bottom of the P-type ion implantation region 15 is to the bottom of the second trench 7 , the more the field strength is shared. In the best case, as shown in FIG. 2, when the bottom of the P-type ion implantation region 15 is at the same level as the bottom of the second trench 7, the field strength at the bottom of the second trench 7 is the weakest, and the breakdown voltage reaches the highest .

However, in this method of implanting P-type ions in the region of the metal contact hole to increase the breakdown voltage, when the bottom of the P-type ion-implantation region 15 is pushed to the depth of the bottom of the second trench 7, the P-type ion-implantation region 15 is also pushed to the bottom of the second trench 7. Diffusion in the lateral direction changes the ion concentration in the channel region and changes the threshold voltage of the VDMOS, thereby making the trench VDMOS unable to work normally.

In order to prevent this from happening, as shown in FIG. 3 , the distance between the two second trenches 7 is increased, but this reduces the cell density of the trench VDMOS and weakens the driving capability of the trench VDMOS.

Contents of the invention

The embodiment of the present invention provides a trench-type VDMOS manufacturing method, which effectively improves the breakdown voltage of the trench-type VDMOS, and at the same time prevents the P-type ion region from laterally diffusing, ensuring that the threshold voltage of the trench-type VDMOS remains unchanged, so that The distance between the trenches for depositing the polysilicon layer remains unchanged, thereby maintaining the cell density and ensuring the driving capability of the trench VDMOS.

An embodiment of the present invention provides a trench-type VDMOS manufacturing method, including:

depositing a hard mask layer on the N-type epitaxial layer;

performing photolithography and etching on the middle region in the hard mask layer to form a first trench window region;

Etching the lower side region of the window region of the first trench to form a first trench in the N-type epitaxial layer;

growing P-type epitaxy on the upper surface of the hard mask layer, the first trench window region, and the first trench;

The P-type epitaxy on the upper surface of the hard mask layer is removed by a chemical mechanical polishing process, and the P-type epitaxy in the hard mask layer and the window area of the first trench is removed, so that the P-type epitaxy in the first trench is formed P-type ion region;

Forming second trenches in partial regions on both sides of the P-type ion region in the N-type epitaxial layer;

forming a gate oxide layer on the upper surface of the N-type epitaxial layer and the inner surface of the second trench;

depositing a polysilicon layer on the gate oxide layer in the second trench;

Forming the body region, source region, dielectric layer and metal layer of the trench type VDMOS.

Further, in the above-mentioned method, forming the second trenches in the partial regions on both sides of the P-type ion region in the N-type epitaxial layer respectively includes:

depositing a hard mask layer on the N-type epitaxial layer;

performing photolithography and etching on partial regions on both sides of the P-type ion region in the hard mask layer to form a second trench window region;

Etching the lower side region of the window region of the second trench to form a second trench in the N-type epitaxial layer.

Further, in the above method, the depth of the first groove is the same as that of the second groove.

Further, in the method as described above, after forming the second trench in the N-type epitaxial layer, it further includes:

rounding the bottom corner of the second groove;

The hard mask layer is removed.

Further, in the above-mentioned method, the dopant ions of the P-type epitaxy in the P-type ion region are boron ions, and the doping concentration of the P-type epitaxy is 1E19-1E20 atoms/cm3.

Further, in the method as described above, after depositing the polysilicon layer on the gate oxide layer in the second trench, it further includes:

The polysilicon layer is etched back so that the upper surface of the polysilicon layer, the upper surface of the P-type ion region and the upper surface of the N-type epitaxial layer are on the same plane.

Further, in the above method, the polysilicon layer has a thickness of 6000-12000 angstroms, and the gate oxide layer has a thickness of 400-1000 angstroms.

An embodiment of the present invention provides a trench-type VDMOS manufacturing method, by depositing a hard mask layer on the N-type epitaxial layer; performing photolithography and etching on the middle region of the hard mask layer to form the first trench window region ; The lower region of the first trench window area is etched to form a first trench in the N-type epitaxial layer; on the upper surface of the hard mask layer, grow P in the first trench window area and the first trench Type epitaxy; using a chemical mechanical polishing process to remove the P-type epitaxy on the upper surface of the hard mask layer, the P-type epitaxy in the hard mask layer and the window area of the first trench, so that a P-type ion region is formed in the first trench; Partial regions on both sides of the P-type ion region in the N-type epitaxial layer form second trenches; a gate oxide layer is formed on the upper surface of the N-type epitaxial layer and the inner surface of the second trench; the gate in the second trench Deposit a polysilicon layer on the oxide layer; form the body region, source region, dielectric layer and metal layer of the trench VDMOS. The breakdown voltage of trench VDMOS is effectively improved, and at the same time, the P-type ion region is no longer diffused laterally, which ensures that the threshold voltage of trench VDMOS remains unchanged, and the distance between the trenches where the polysilicon layer is deposited remains unchanged. The cell density is maintained and the driving capability of the trench VDMOS is guaranteed.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative efforts.

FIG. 1 is a schematic diagram of a first structure of a trench VDMOS in the prior art;

2 is a schematic diagram of a second structure of a trench VDMOS in the prior art;

3 is a schematic diagram of a third structure of a trench VDMOS in the prior art;

FIG. 4 is a flow chart of Embodiment 1 of the trench VDMOS manufacturing method of the present invention;

5 is a schematic structural diagram after depositing a hard mask layer on the N-type epitaxial layer in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

6 is a schematic diagram of the structure of the first trench window region after photolithography and etching are performed on the middle region of the hard mask layer in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

FIG. 7 is a schematic structural diagram after etching the lower region of the first trench window region and forming the first trench in the N-type epitaxial layer in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

8 is a schematic diagram of the structure after growing P-type epitaxy on the upper surface of the hard mask layer, the first trench window region, and the first trench in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

9 shows the P-type epitaxy on the upper surface of the hard mask layer removed by chemical mechanical polishing process in the trench VDMOS manufacturing method provided by Embodiment 1 of the present invention, and the P-type epitaxy in the hard mask layer and the window region of the first trench. , so that the structure schematic diagram after forming the P-type ion region in the first trench;

FIG. 10 is a schematic structural diagram of forming second trenches in parts of the N-type epitaxial layer on both sides of the P-type ion region in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

11 is a schematic structural view of a gate oxide layer formed on the upper surface of the N-type epitaxial layer and the inner surface of the second trench in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

12 is a schematic structural diagram after depositing a polysilicon layer on the gate oxide layer in the second trench in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

13 is a flow chart of forming a body region, a source region, a dielectric layer and a metal layer of a trench-type VDMOS in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

FIG. 14 is a schematic structural view after forming a body region in the N-type epitaxial layer of the trench-type VDMOS in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

15 is a schematic structural diagram after forming source regions in regions on both sides of the second trench in the body region in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

16 is a schematic structural diagram after depositing a dielectric layer on the gate oxide layer above the source region and removing the gate oxide layer in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

17 is a schematic structural diagram after depositing a metal layer of a trench-type VDMOS in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention;

FIG. 18 is the first flow chart of Embodiment 2 of the trench VDMOS manufacturing method of the present invention;

FIG. 19 is a second flow chart of Embodiment 2 of the trench VDMOS manufacturing method of the present invention.

Reference signs:

1-N-type substrate 2-N-type epitaxial layer 3-hard mask layer

4-First trench window area 5-First trench 6-P-type epitaxy

7-Second trench 8-Gate oxide layer 9-Polysilicon layer

10-body region 11-source region 12-dielectric layer

13-Front metal layer 14-Back metal layer 15-P-type ion implantation area

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment one

FIG. 4 is a flow chart of Embodiment 1 of the trench VDMOS manufacturing method of the present invention. As shown in FIG. 4 , the trench VDMOS manufacturing method provided in this embodiment includes:

Step 101 , depositing a hard mask layer 3 on the N-type epitaxial layer 2 .

In this embodiment, the N-type epitaxial layer 2 is grown on the N-type substrate 1 . Wherein, the N-type substrate 1 is a heavily doped N-type substrate, and the N-type epitaxial layer 2 is a lightly doped N-type epitaxial layer. The specific doping concentration of the N-type substrate 1 and the doping concentration of the N-type epitaxial layer 2 are the same as those in the prior art, and will not be repeated here.

In this embodiment, the hard mask layer 3 deposited on the N-type epitaxial layer 2 may be a silicon dioxide layer. The deposition process may be low pressure chemical vapor deposition. The deposited hard mask layer may have a thickness of 4000-7000 Angstroms. 5 is a schematic structural diagram after depositing a hard mask layer on the N-type epitaxial layer in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention.

Step 102 , performing photolithography and etching on the middle region of the hard mask layer 3 to form the first trench window region 4 .

In this embodiment, the hard mask layer 3 in the middle area is etched away by photolithography and etching techniques to form the first trench window area 4 . Wherein the first trench 5 is a trench for forming a P-type ion region. The first trench window area 4 is a window area for the first trench formed after etching. FIG. 6 is a schematic diagram of the structure after photolithography and etching are performed on the middle region of the hard mask layer in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention to form the first trench window region, as shown in FIG. 6 , the cross section of the first trench window region 4 is rectangular.

Optionally, the etching process in this embodiment may adopt a dry etching process.

Step 103 , etching the lower side region of the first trench window region 4 to form a first trench 5 in the N-type epitaxial layer.

In this embodiment, a dry etching process may be used to etch the lower side region of the first trench window region 4 to form the first trench 5 in the N-type epitaxial layer 2 . Wherein, the cross-sectional shape of the first trench 5 is rectangular, and the depth of the first trench 4 is smaller than the thickness of the N-type epitaxial layer 2 . Wherein, FIG. 7 is a structural diagram after etching the lower region of the window region of the first trench and forming the first trench in the N-type epitaxial layer in the trench VDMOS manufacturing method provided by Embodiment 1 of the present invention. As shown in FIG. 7 , the first trench 5 is located directly below the first trench window area 4 , and the side surfaces of the first trench 5 and the side surfaces of the first trench window area 4 are located on the same plane.

Step 104 , growing P-type epitaxy 6 on the upper surface of the hard mask layer 3 , in the first trench window region 4 and the first trench 5 .

In this embodiment, a P-type epitaxy 6 is grown on the upper surface of the hard mask layer 3 , the first trench window region 4 and the first trench 5 by using an epitaxial growth process. Wherein, the dopant ions in the P-type epitaxy 6 may be boron ions. Among them, FIG. 8 is a schematic diagram of the structure after growing P-type epitaxy on the upper surface of the hard mask layer, the first trench window region and the first trench in the trench-type VDMOS manufacturing method provided by Embodiment 1 of the present invention, as shown in FIG. As shown in FIG. 8 , in this embodiment, the P-type epitaxy 6 fills the first trench window region 4 and the first trench 5 .

Step 105, using a chemical mechanical polishing process to remove the P-type epitaxy 6 on the upper surface of the hard mask layer 3, the P-type epitaxy 6 in the hard mask layer 3 and the first trench window region 4, so that the first trench 5 A P-type ion region is formed.

In this embodiment, the chemical mechanical polishing process (Chemical Mechanical Polishing, referred to as CMP) is a process of obtaining a smooth surface by chemical and mechanical force. Epitaxy 6, the P-type epitaxy 6 in the hard mask layer 3 and the first trench window region 4, so that the P-type ion region is formed in the first trench 5, greatly improving the polishing accuracy and polishing speed, and improving the polishing efficiency. quality and reduced production costs.

In this embodiment, the first trench 5 and the P-type epitaxy 6 constitute a P-type ion region. Among them, FIG. 9 shows the P-type epitaxy on the upper surface of the hard mask layer removed by chemical mechanical polishing process in the trench VDMOS manufacturing method provided by Embodiment 1 of the present invention, and the P-type epitaxy in the hard mask layer and the first trench window area. Type epitaxy, so that the structure diagram of the P-type ion region is formed in the first trench.

Step 106 , forming second trenches 7 in parts of the N-type epitaxial layer 2 on both sides of the P-type ion region.

In this embodiment, the process used when forming the second trenches 7 in parts of the N-type epitaxial layer 2 on both sides of the P-type ion region can be photolithography, etching, or other processes. Examples are not limited to this.

In this embodiment, the second trench 7 is a trench for depositing a polysilicon layer. Among them, FIG. 10 is a schematic structural diagram of forming second trenches in parts of the N-type epitaxial layer on both sides of the P-type ion region in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention, as shown in FIG. 10 , the cross-sectional shape of the second trench 7 is rectangular, and the depth of the second trench 7 is smaller than the thickness of the N-type epitaxial layer 2 . There is a distance between the P-type ion regions and the second trenches 7 respectively.

Step 107 , forming a gate oxide layer 8 on the upper surface of the N-type epitaxial layer 2 and the inner surface of the second trench 7 .

In this embodiment, the upper surface of the N-type epitaxial layer 2 is the upper surface of the N-type epitaxial layer 2 without the second trench 7 . The gate oxide layer 8 in this embodiment may have a thickness of 400-1000 angstroms. Wherein, FIG. 11 is a schematic structural diagram after forming a gate oxide layer on the upper surface of the N-type epitaxial layer and the inner surface of the second trench in the trench VDMOS manufacturing method provided in Embodiment 1 of the present invention.

Step 108 , depositing a polysilicon layer 9 on the gate oxide layer 8 in the second trench 7 .

In this embodiment, the polysilicon layer 9 deposited on the gate oxide layer 8 in the second trench 7 has a thickness of 6000-12000 angstroms. Wherein, FIG. 12 is a schematic structural diagram after depositing a polysilicon layer on the gate oxide layer in the second trench in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention.

Step 109 , forming the body region 10 , the source region 11 , the dielectric layer 12 and the metal layer of the trench VDMOS.

Wherein, the metal layer includes a front metal layer 13 and a back metal layer 14 .

In this embodiment, FIG. 13 is a flow chart of forming a body region, a source region, a dielectric layer and a metal layer of a trench-type VDMOS in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention, as shown in FIG. 13 , Step 109 can be specifically divided into the following four steps for execution.

Step 109a, forming a body region 10 in the N-type epitaxial layer 2 of the trench VDMOS.

Specifically, when forming the body region 10 of the trench-type VDMOS, a P-type ion implantation process is used to form the body region 10, wherein the implanted P-type ions can be boron ions, and the dose can be 1.0E13-1.0E15 per square centimeter , the energy can be 60-120KEV, and then high-temperature driving can be carried out, the temperature can be 900-1150 degrees, and the driving time can be 40-100 minutes.

In this embodiment, FIG. 14 is a schematic diagram of the structure after the body region is formed in the N-type epitaxial layer of the trench-type VDMOS in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention. As shown in FIG. 14 , the trench-type VDMOS The body region 10 of VDMOS is formed in the N-type epitaxial layer 2 , and the thickness of the body region 10 is smaller than the thickness of the N-type epitaxial layer 2 .

Step 109 b , forming source regions 11 in regions on both sides of the second trench 7 in the body region 10 .

In this embodiment, the region of the source region 11 is defined by a photolithography process, and N-type ions are implanted by using an ion implantation process. The implanted N-type ions may be arsenic or phosphorus. The injected dose can be 1.0E15-1.0E16 per square centimeter, and the energy can be 50-120KEV. Then carry out ion activation, the temperature of ion activation can be 800-1000 degrees, and the time of ion activation can be 20-60 minutes.

In this embodiment, FIG. 15 is a schematic structural diagram after forming source regions in regions on both sides of the second trench in the body region in the trench-type VDMOS manufacturing method provided in Embodiment 1 of the present invention. As shown in FIG. 15 , source regions 11 are formed in regions on both sides of the second trench 7 in the body region 10 .

Step 109c, depositing a dielectric layer 12 on the gate oxide layer 8 above the source region 11 .

In this embodiment, the dielectric layer 12 may be a silicon dioxide layer or a silicon dioxide layer doped with boron and phosphorus.

In this embodiment, FIG. 16 is a schematic structural diagram after depositing a dielectric layer on the gate oxide layer above the source region and removing the gate oxide layer in the trench VDMOS manufacturing method provided in Embodiment 1 of the present invention. As shown in FIG. 16, after depositing the dielectric layer 12 on the gate oxide layer 8 above the source region 11, the photolithography and etching process of the hole layer is performed. The specific photolithography and etching process of the hole layer is the prior art. No more details here.

Step 109d, depositing a metal layer of trench type VDMOS.

In this embodiment, the metal layer includes: a front metal layer 13 and a back metal layer 14 . Wherein, the front metal layer 13 can be an aluminum-silicon-copper alloy to form a source metal layer with a thickness of 2-4 microns, and the back metal layer 14 can be a titanium-nickel-silver composite layer to form a drain metal layer. Wherein, FIG. 17 is a schematic diagram of the structure after depositing the metal layer of the trench VDMOS in the trench VDMOS manufacturing method provided in Embodiment 1 of the present invention.

In the trench VDMOS manufacturing method provided in this embodiment, a hard mask layer is deposited on the N-type epitaxial layer; photolithography and etching are performed on the middle region of the hard mask layer to form a first trench window region; The lower area of the first trench window area is etched to form a first trench in the N-type epitaxial layer; on the upper surface of the hard mask layer, the first trench window area and the first trench grow P-type epitaxy ; The P-type epitaxy on the upper surface of the hard mask layer is removed by a chemical mechanical polishing process, and the P-type epitaxy in the hard mask layer and the window area of the first trench is used to form a P-type ion region in the first trench; Partial regions on both sides of the P-type ion region in the N-type epitaxial layer respectively form a second trench; a gate oxide layer is formed on the upper surface of the N-type epitaxial layer and the inner surface of the second trench; the gate oxide layer in the second trench Deposit a polysilicon layer on it; form the body region, source region, dielectric layer and metal layer of the trench VDMOS. The breakdown voltage of the trench type VDMOS is effectively improved, and at the same time, due to the use of a chemical mechanical polishing process to remove the P-type epitaxy on the upper surface of the hard mask layer, the P-type epitaxy in the hard mask layer and the first trench window area, and Forming a P-type ion region in the first trench, so that the P-type ion region no longer diffuses laterally, ensures that the threshold voltage of the trench-type VDMOS remains unchanged, and maintains the distance between the first trench and the second trench, The distance between the trenches for depositing the polysilicon layer is kept constant, thereby maintaining the cell density and ensuring the driving capability of the trench VDMOS.

Embodiment two

FIG. 18 is the first flow chart of Embodiment 2 of the trench-type VDMOS manufacturing method of the present invention. As shown in FIG. 18 , the trench-type VDMOS manufacturing method provided in this embodiment includes:

Step 201 , depositing a hard mask layer 3 on the N-type epitaxial layer 2 .

Step 202 , performing photolithography and etching on the middle region of the hard mask layer 3 to form the first trench window region 4 .

Step 203 , etching the lower side region of the first trench window region 4 to form a first trench 5 in the N-type epitaxial layer.

Step 204 , growing P-type epitaxy 6 on the upper surface of the hard mask layer 3 , in the first trench window region 4 and the first trench 5 .

Step 205, using a chemical mechanical polishing process to remove the P-type epitaxy 6 on the upper surface of the hard mask layer 3, the P-type epitaxy 6 in the hard mask layer 3 and the first trench window region 4, so that the first trench 5 A P-type ion region is formed.

Preferably, the doping ions of the P-type epitaxy 6 in the P-type ion region in this embodiment are boron ions, and the doping concentration of the P-type epitaxy is 1E19-1E20 atoms/cm3.

In this embodiment, steps 201 to 205 are the same as steps 101 to 105 in the present invention, and will not be repeated here.

Step 206 , forming second trenches 7 in parts of the N-type epitaxial layer 2 on both sides of the P-type ion region.

Further, step 206 in this embodiment may be divided into the following three steps for execution. FIG. 19 is the second flow chart of Embodiment 2 of the trench VDMOS manufacturing method of the present invention. As shown in FIG. 19, step 206 includes:

Step 206 a , depositing a hard mask layer 3 on the N-type epitaxial layer 2 .

In this embodiment, the process of step 206 a is the same as that of step 201 , which will not be repeated here.

In step 206b, photolithography and etching are carried out on partial regions on both sides of the P-type ion region in the hard mask layer 3 to form a second trench window region.

In this embodiment, photolithography and etching are used to etch away part of the hard mask layer 3 located on both sides of the P-type ion region in the hard mask layer 3 to form the second trench window region. The second trench 7 is a trench for depositing a polysilicon layer, and the window area of the second trench is a window area for the second trench formed after etching.

Optionally, the etching process in this embodiment may adopt a dry etching process.

In this embodiment, the second trench 7 is located directly below the window area of the second trench, and the side surfaces of the second trench 7 and the window area of the second trench are located on the same plane.

Step 206c, etching the lower side region of the window region of the second trench to form a second trench 7 in the N-type epitaxial layer 2 .

In this embodiment, a dry etching process may be used to etch the lower region of the window region of the second trench to form the second trench 7 in the N-type epitaxial layer 2 . Wherein, the cross-sectional shape of the second trench 7 is rectangular, and the depth of the second trench 7 is smaller than the thickness of the N-type epitaxial layer 2 .

Preferably, in this embodiment, the first groove 5 and the second groove 7 have the same depth.

In this embodiment, after the P-type ion region is formed, the P-type ion region can share the field strength at the bottom of the second trench 7, thereby increasing the breakdown voltage. The closer the bottom of the first trench 5 is to the bottom of the second trench 7 bottom, the more shared field intensity, when the depth of the first groove 5 and the second groove 7 are the same, that is, when the bottom of the first groove and the bottom of the second groove are at the same level, the second groove bottom The field strength is the weakest and the breakdown voltage reaches the highest.

Step 207 , rounding the bottom corner of the second groove 7 .

In this embodiment, since the bottom angle of the second trench 7 is a right angle and the radius of curvature is small, the breakdown voltage is low, so after the bottom corner of the second trench 7 is rounded, the second trench 7 The increased curvature of the bottom corner further increases the breakdown voltage of the trench VDMOS.

In this embodiment, after the bottom corner of the second trench 7 is rounded, the hard mask layer 3 is removed by a method in the prior art.

Step 208 , forming a gate oxide layer 8 on the upper surface of the N-type epitaxial layer 2 and the inner surface of the second trench 7 .

Step 209 , depositing a polysilicon layer 9 on the gate oxide layer 8 in the second trench 7 .

In this embodiment, steps 208 to 209 are the same as steps 107 to 108 in Embodiment 1 of the trench VDMOS manufacturing method of the present invention, and will not be repeated here.

In step 210, the polysilicon layer 9 is etched back.

In this embodiment, after the polysilicon layer 9 is etched back, the upper surface of the polysilicon layer 9 , the upper surface of the P-type ion region and the upper surface of the N-type epitaxial layer 2 are on the same plane.

Step 211 , forming the body region 10 , the source region 11 , the dielectric layer 12 and the metal layer of the trench VDMOS.

In this embodiment, step 211 is the same as step 109 in Embodiment 1 of the trench-type VDMOS manufacturing method of the present invention, and will not be repeated here.

In the trench-type VDMOS manufacturing method provided in this embodiment, the depth of the first trench is the same as that of the second trench, and the bottom corner of the second trench is rounded, which can further improve the impact of the trench-type VDMOS. wear voltage.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (7)

1. a groove-shaped VDMOS manufacture method, it is characterised in that including:

Described N-type epitaxy layer deposits hard mask layer；

Zone line in described hard mask layer is carried out photoetching, etching, forms the first trench openings district；

The underside area in described first trench openings district is performed etching, is formed in described N-type epitaxy layer First groove；

P is grown in described hard mask layer upper surface, described first trench openings district and described first groove Type extension；

Use CMP process to remove the p-type extension of described hard mask layer upper surface, described firmly cover P-type extension in film floor and described first trench openings district so that in described first groove formed p-type from Sub-district；

The second groove is formed respectively in the subregion of both sides, described N-type epitaxy layer ZhongPXing ion district；

Upper surface and described second grooved inner surface in described N-type epitaxy layer form gate oxide；

Deposit polycrystalline silicon layer on gate oxide in described second groove；

Form the body district of described groove-shaped VDMOS, source region, dielectric layer and metal level.

Method the most according to claim 1, it is characterised in that described in described N-type epitaxy layer The subregion of both sides, ZhongPXing ion district forms the second groove respectively and specifically includes:

Described N-type epitaxy layer deposits hard mask layer；

The subregion of the both sides, described p-type ion district in described hard mask layer is carried out photoetching, etching, Form the second trench openings district；

The underside area in described second trench openings district is performed etching, is formed in described N-type epitaxy layer Second groove.

Method the most according to claim 2, it is characterised in that described first groove and described the The degree of depth of two grooves is identical.

Method the most according to claim 3, it is characterised in that described in described N-type epitaxy layer After middle formation the second groove, also include:

The base angle of described second groove is carried out round and smooth process；

Remove described hard mask layer.

5. according to the method described in claim 3 or 4, it is characterised in that in described p-type ion district The dopant ion of p-type extension is boron ion, and the doping content of described p-type extension is 1E19-1E20 atom Number/cubic centimetre.

Method the most according to claim 5, it is characterised in that described in described second groove Gate oxide on after deposit polycrystalline silicon layer, also include:

Carry out back described polysilicon layer processing quarter, so that the upper surface of described polysilicon layer, described P The upper surface in type ion district is with the upper surface of described N-type epitaxy layer at grade.

Method the most according to claim 6, it is characterised in that the thickness of described polysilicon layer is 6000-12000 angstrom, the thickness of described gate oxide is 400-1000 angstrom.