CN106158643B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN106158643B CN106158643B CN201510163918.2A CN201510163918A CN106158643B CN 106158643 B CN106158643 B CN 106158643B CN 201510163918 A CN201510163918 A CN 201510163918A CN 106158643 B CN106158643 B CN 106158643B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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Abstract
一种晶体管的形成方法，包括：提供衬底；在所述衬底表面形成栅极结构；在所述栅极结构两侧的衬底内形成开口；在所述开口内形成应力层；在所述应力层表面形成覆盖层，所述覆盖层内掺杂有氧族元素离子；采用金属硅化工艺使所述覆盖层转化为电接触层，所述电接触层的材料为掺杂有氧族元素离子的金属硅化物。所形成的晶体管中，应力层表面的电阻降低，使所述晶体管的工作电流提高、性能稳定。
A method for forming a transistor, comprising: providing a substrate; forming a gate structure on the surface of the substrate; forming an opening in the substrate on both sides of the gate structure; forming a stress layer in the opening; A cover layer is formed on the surface of the stress layer, and the cover layer is doped with oxygen group element ions; the metal silicidation process is used to convert the cover layer into an electrical contact layer, and the material of the electrical contact layer is doped with oxygen group elements. Ionic metal silicides. In the formed transistor, the resistance of the surface of the stress layer is reduced, so that the operating current of the transistor is increased and the performance is stable.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of transistor.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is just towards higher component density and higher
The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor
The raising of the component density and integrated level of device, the grid size of transistor become more shorter than previous.However, the grid of transistor
Size, which shortens, can make transistor generate short-channel effect, and then generate leakage current, the final electric property for influencing semiconductor devices.
Currently, the prior art mainly improves performance of semiconductor device by improving carrier mobility.When the mobility of carrier mentions
The driving current of height, transistor improves, then the leakage current in transistor is reduced, and one for improving carrier mobility is critical to
Element is the stress improved in transistor channel region, therefore the stress for improving transistor channel region can greatly improve transistor
Performance.
A kind of method of prior art raising transistor channel region stress are as follows: form stress in the source region of transistor and drain region
Layer.Wherein, the stress layer material of PMOS transistor is SiGe (SiGe), due to SiGe and silicon lattice structure having the same, i.e.,
" diamond " structure, and at room temperature, the lattice constant of SiGe is greater than the lattice constant of silicon, therefore exists between silicon and SiGe
Lattice mismatch enables stressor layers to provide compression to channel region, to improve the carrier mobility of PMOS transistor channel region
Rate performance.Correspondingly, the stress layer material of NMOS transistor is silicon carbide (SiC), since at room temperature, the lattice of silicon carbide is normal
Number is less than the lattice constant of silicon, therefore there are lattice mismatches between silicon and silicon carbide, can provide tensile stress to channel region, thus
Improve the performance of NMOS transistor.
However, to be formed by the electrical connection properties between stressor layers and conductive structure bad for the prior art, reduce and partly lead
The Performance And Reliability of body device.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of transistor, is formed by transistor, stressor layers table
The resistance in face reduces, and improves the operating current of the transistor, performance is stablized.
To solve the above problems, the present invention provides a kind of forming method of transistor, comprising: provide substrate；In the lining
Bottom surface forms gate structure；Opening is formed in the substrate of the gate structure two sides；Stressor layers are formed in the opening；
Coating is formed in the stress layer surface, the coating is interior doped with oxygen group elements ion；Made using silication technique for metal
The coating is converted into electric contacting layer, and the material of the electric contacting layer is the metal silicide doped with oxygen group elements ion.
Optionally, the material of the stressor layers is silicon carbide；Doped with N-shaped ion in the stressor layers.
Optionally, the forming step of the stressor layers includes: side wall and bottom surface the formation seed layer in the opening；
The stress material layer for filling the full opening is formed in the seed layer surface.
Optionally, the formation process of the seed layer is chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation；The formation process of the stress material layer is epitaxial deposition process.
Optionally, the material of the coating is the silicon carbide for adulterating oxygen group elements ion.
Optionally, the formation process of the coating is epitaxial deposition process.
Optionally, the oxygen group elements ion adulterated in the coating is sulphion, plasma selenium or tellurium ion.
Optionally, the technique that oxygen group elements ion is adulterated in coating is doping process in situ or ion implantation technology.
Optionally, the oxygen group elements for oxygen group elements ion being adulterated in coating using doping process in situ, and being adulterated from
When son is sulphion, process gas includes one of hydrogen sulfide, sulfur dioxide, sulfur fluoride or a variety of.
Optionally, when the oxygen group elements ion adulterated in the coating is sulphion, the atom hundred of the sulphion
Dividing specific concentration is 0.1~5%.
Optionally, the coating with a thickness of 3 nanometers~50 nanometers.
Optionally, the silication technique for metal includes: to form metal on the substrate, coating and gate structure surface
Layer；The metallic atom in metal layer is spread into coating using the first annealing process, and coating is made to be converted into electric contacting layer；
After first annealing process, remaining metal layer is removed.
Optionally, the material of the metal layer is nickel or platinum.
Optionally, further includes: after removing remaining metal layer, carry out the second annealing process.
Optionally, the gate structure includes: the gate dielectric layer positioned at substrate surface, the electricity of the grid positioned at gate dielectric layer surface
Pole layer and the side wall positioned at gate electrode layer and gate dielectric layer two sides side wall and substrate surface.
Optionally, the material of the gate dielectric layer is silica；The material of the gate electrode layer is polysilicon.
Optionally, further includes: after forming the coating, dielectric layer is formed in the substrate and cover surface,
The dielectric layer exposes the top surface of the gate structure；The gate electrode layer is removed, forms grid in the dielectric layer
Pole opening；High-k dielectric layer is formed in the bottom surface of the gate openings；Metal gate is formed on the high-k dielectric layer surface.
Optionally, the forming step of the opening includes: to form mask layer in the substrate and gate structure surface, described
Mask layer exposes the section substrate surface of the gate structure two sides；Using the mask layer as exposure mask, the substrate is etched,
Opening is formed in the substrate.
Optionally, the etching technics for forming the opening includes dry etch process.
Optionally, further includes: form electric interconnection structure on the electric contacting layer surface.
Compared with prior art, technical solution of the present invention has the advantage that
In forming method of the invention, after stress layer surface forms coating, chalcogen is adulterated in the coating
Element ion；When it is subsequent so that coating is converted into electric contacting layer using silication technique for metal after, can make to be formed by electricity and connect
Contact layer material is the metal silicide doped with oxygen group elements ion.Due to finding after study, in metal silicide materials
Therefore the Schottky barrier that doping oxygen group elements ion can reduce metal silicide materials is formed by Xiao of electric contacting layer
Special base potential barrier reduces, then the resistance of the electric contacting layer reduces, and is formed by electricity so as to reduce the stressor layers with subsequent
Resistance between interconnection structure.Since stressor layers and the subsequent resistance being formed by between electric interconnection structure reduce, can be improved
Electric current between electric interconnection structure and stressor layers makes to be formed by crystal to improve the operating current for being formed by transistor
The performance of pipe is more stable, and reliability improves.
Further, the material of the stressor layers be silicon carbide, then be formed by covering layer material for doping oxygen group elements from
The silicon carbide of son；It is the metal carbon silication conjunction for adulterating oxygen group elements ion that the electric contacting layer material formed is converted by the coating
Object material, can further decrease the Schottky barrier of metal carbon-silicon compound material, reduce stressor layers and electric contacting layer with this
Between contact resistance, then resistance between the electric interconnection structure being subsequently formed and stressor layers reduces.
Further, the oxygen group elements ion adulterated in the coating is sulphion, and chalcogen member is adulterated in coating
The technique of plain ion is doping process in situ；The original position doping process can be during forming coating, by work
Sulphur source gas is added in skill gas, the sulphion adulterated in coating can be made to be more evenly distributed, and doping process is more simple；
The sulphion being then formed by electric contacting layer is more uniformly spread, and is formed by electric contacting layer for the energy of reduction contact resistance
Power is more stable.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of the schematic diagram of the section structure of the forming process of transistor of the embodiment of the present invention；
Fig. 4 to Figure 10 is the schematic diagram of the section structure of the forming process of the transistor of the embodiment of the present invention.
Specific embodiment
As stated in the background art, it is bad to be formed by the electrical connection properties between stressor layers and conductive structure for the prior art,
Reduce the Performance And Reliability of semiconductor devices.
It finds after study, since the material of stressor layers is semiconductor material, and the material of conductive structure is metal, described
There are Schottky barrier at the contact interface of stressor layers and conductive structure, cause carrier in the stressor layers and conductive structure
Transition difficulty at contact interface is larger, then the contact resistance between the stressor layers and conductive structure is larger.
In order to reduce the contact resistance between the stressor layers and conductive structure, a kind of method is formed in stress layer surface
Using metal silicide as the electric contacting layer of material, the metal silicide materials can reduce between conductive structure and stressor layers
Thus Schottky barrier reduces the contact resistance between stressor layers and conductive structure.
Fig. 1 to Fig. 3 is a kind of the schematic diagram of the section structure of the forming process of transistor of the embodiment of the present invention.
Referring to FIG. 1, providing substrate 100,100 surface of substrate has gate structure 101, the gate structure 101
There is opening 102 in the substrate 100 of two sides.
Referring to FIG. 2, forming stressor layers in 102 (as shown in Figure 1) of the opening using selective epitaxial depositing operation
103, the surface of the stressor layers 103 is higher than 100 surface of substrate.
Referring to FIG. 3, so that the part stressor layers 103 positioned at surface is converted into electric contacting layer 104 using silication technique for metal,
The material of the electric contacting layer 104 is metal silicide.
Wherein, when being formed by transistor is PMOS transistor, the material of the stressor layers 103 is SiGe (SiGe)；
When being formed by transistor is NMOS transistor, the material for being formed by stressor layers 103 is silicon carbide (SiC).The electricity connects
The forming step of contact layer 104 includes: in 103 forming metal layer on surface of stressor layers；Make the gold in metal layer using thermal anneal process
Belong to atom to spread into stressor layers, the part stressor layers 103 positioned at surface is made to be converted into metal silicide materials, forms electrical contact
Layer 104；After the thermal anneal process, remaining metal layer is removed.
The material of the metal layer is nickel (Ni) or cobalt (Co)；Wherein, especially using nickel as the material of metal layer when, can make
Electric contacting layer 104 is formed by with lower contact resistance.For PMOS transistor, the material of the stressor layers 103
For SiGe, the material for being formed by electric contacting layer 104 is the nickel-silicon compound for mixing germanium；It is described to answer for NMOS transistor
The material of power layer 103 is silicon carbide, and the material for being formed by electric contacting layer 104 is the nickel-silicon compound of carbon dope.
However, with the continuous diminution of semiconductor technology node, the size of the transistor of required formation is also accordingly reduced, is led
It causes the contact area between the stressor layers 103 and conductive structure smaller, causes connecing between stressor layers 103 and conductive structure
Electric shock resistance is larger.Even if forming electric contacting layer 104 between conductive structure and stressor layers 103, since the characteristic of material itself limits
System, it is limited to the ability for reducing contact resistance between the stressor layers 103 and conductive structure.By taking NMOS transistor as an example, when
When the material of the metal layer is nickel, it is formed by the nickel-silicon compound that 104 material of electric contacting layer is carbon dope, however, by institute
The Schottky barrier for stating the nickel-silicon compound of carbon dope is still higher, causes to be formed by NMOS transistor, stressor layers and conduction
Contact resistance between structure is still larger.Therefore, the forming process of the transistor is unable to satisfy the demand of technology development.
To solve the above-mentioned problems, the present invention provides a kind of forming method of transistor.Wherein, it is formed in stress layer surface
After coating, oxygen group elements ion is adulterated in the coating；Coating is converted using silication technique for metal when subsequent
After electric contacting layer, it can make to be formed by electric contacting layer material doped with the metal silicide of oxygen group elements ion.By
In finding after study, adulterating oxygen group elements ion in metal silicide materials can reduce the Xiao Te of metal silicide materials
Base potential barrier, therefore, the Schottky barrier for being formed by electric contacting layer reduce, then the resistance of the electric contacting layer reduces, so as to
Enough reduce the stressor layers and the subsequent resistance being formed by between electric interconnection structure.Since stressor layers are formed by electricity with subsequent
Resistance between interconnection structure reduces, and can be improved the electric current between electric interconnection structure and stressor layers, is formed by improve
The operating current of transistor keeps the performance for being formed by transistor more stable, and reliability improves.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 10 is the schematic diagram of the section structure of the forming process of the transistor of the embodiment of the present invention.
Referring to FIG. 4, providing substrate 200；Gate structure 201 is formed on 200 surface of substrate.
The substrate 200 be silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate or
Germanium on insulator (GOI) substrate.In the present embodiment, the substrate 200 is silicon substrate, subsequent at 201 liang of the gate structure
Stressor layers are formed in the substrate 200 of side, and the material of the stressor layers is SiGe or silicon carbide, can make the silicon substrate and answer
There are lattice mismatch between power layer, enable the application stress of substrate 200 for being formed by stressor layers to gate structure bottom, with this
Improve the carrier mobility of channel region.In the present embodiment, being formed by transistor is NMOS transistor, and what is be subsequently formed answers
Power layer material is silicon carbide.
The gate structure 201 is used to form transistor.The gate structure 201 includes: the grid on substrate 200
Layer and positioned at the grid layer sidewall surfaces side wall.In the present embodiment, the gate structure 201 further include: be located at institute
State the gate dielectric layer between grid layer and substrate 200.Wherein, the material of the grid layer is polysilicon or amorphous silicon, grid
Layer with a thickness of 500 angstroms~1500 angstroms；The material of the gate dielectric layer is silica.
In one embodiment, the gate structure 201 can be directly used for forming transistor, then the gate dielectric layer 210
Material can also be silicon nitride or silicon oxynitride.
In another embodiment, the gate structure 201 can be used as dummy gate structure, subsequent with high-K gate dielectric layer
The grid layer and gate dielectric layer are substituted with metal gate, then is capable of forming high-K metal gate structure (High K Metal Gate, letter
Claim HKMG) transistor, then the grid layer and gate dielectric layer are that the high-K gate dielectric layer being subsequently formed and metal gate take up space
Position.
In this embodiment, the gate dielectric layer can protect 200 surface of substrate to exempt from the subsequent removal grid layer
It is damaged, and the material of the gate dielectric layer is silica, the etching selection ratio between 200 surface of the gate dielectric layer and substrate
It is larger, it is smaller to the damage on 200 surface of substrate when removing the gate dielectric layer.
The formation process of the gate dielectric layer and grid layer includes: to form gate dielectric film on 200 surface of substrate；In the grid
Medium film surface forms gate electrode film；Patterned first mask layer (not shown), the figure are formed in the grid film surface
The first mask layer changed exposes part of grid pole film surface and covering needs to form the corresponding region and position of grid layer；With institute
Stating patterned first mask layer is exposure mask, etches the gate electrode film and gate dielectric film, until exposing 200 surface of substrate
Until, form grid layer and gate dielectric layer.Wherein, the formation process thermal oxidation technology of the gate dielectric film, chemical oxidation process,
Chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process；The formation process of the gate electrode film is chemistry
Gas-phase deposition or physical gas-phase deposition.
In the present embodiment, after forming the grid layer and gate dielectric layer, retain patterned first exposure mask
Layer, patterned first mask layer can protect the grid layer during being subsequently formed stressor layers and electric contacting layer
Top.
The technique for etching the gate electrode film is anisotropic dry etch process, etching gas Cl2、HBr、SF6In one
Kind is a variety of；The technique of the gate dielectric film is etched to combine for one or both of dry etch process, wet-etching technology,
Wherein, the etching liquid of the wet-etching technology includes hydrofluoric acid solution, and the gas of dry etching includes hydrofluoric acid gas.
Patterned first mask material is SiN, SiON, SiOCN, SiOBN, SiO2One of or a variety of groups
It closes, with a thickness of 50 angstroms~500 angstroms.The formation process of patterned first mask layer includes: in the grid film surface shape
At mask material film；Patterned layer is formed in the mask material film surface, the patterned layer covering needs to form grid layer
Corresponding region；Using the patterned layer as exposure mask, the mask material film is etched, until exposing grid film surface,
Form patterned first mask layer.
Wherein, the formation process of the mask material film is atom layer deposition process or chemical vapor deposition process.It is described
Patterned layer can be patterned photoresist layer, also can be the exposure mask formed using multiple graphics masking process, such as from
It is directed at double-pattern (Self-Aligned Double Patterning, abbreviation SADP) exposure mask.
In other embodiments, the gate structure 201 is used as dummy gate structure, and the gate structure 201 can wrap
The gate dielectric layer for not having silica between the grid layer and substrate is included, the material of the grid layer is polysilicon, subsequent to go
After the grid layer, high-K gate dielectric layer is formed in the position of the grid layer and positioned at high-K gate dielectric layer surface
Metal gate.
Distance of the side wall for defining the stressor layers being subsequently formed to grid layer.The material of the side wall includes oxidation
Silicon, silicon nitride, silicon oxynitride, the silicon oxynitride of carbon dope, boron-doping one of silicon oxynitride or multiple combinations；The side wall
With a thickness of 20 angstroms~200 angstroms；The formation process of the side wall includes: in substrate, the sidewall surfaces of grid layer and patterned
First exposure mask layer surface deposits side wall film；The side wall film is etched back to until exposing the patterned first mask layer bottom
Until 200 surface of surface and substrate, the side wall is formed.
In the present embodiment, since the top surface in grid layer remains patterned first mask layer, the figure
The first mask layer changed can protect the top surface of the grid layer in the technique for being etched back to side wall film.
Referring to FIG. 5, forming opening 202 in the substrate 200 of 201 two sides of gate structure.
In the present embodiment, the opening 202 is used to form stressor layers, doped p-type ion or N-type in the stressor layers
Ion can form source region and drain region in the substrate 200 of 201 two sides of gate structure.The depth of the opening 202 is 50 nanometers
~200 nanometers.
The forming step of the opening 202 includes: to form the second exposure mask in the substrate 200 and 201 surface of gate structure
Layer (not shown), second mask layer expose 200 surface of section substrate of 201 two sides of gate structure；With described
Two mask layers are exposure mask, etch the substrate 200, and opening 202 is formed in the substrate 200.
It is described in order to keep the structure snd size of second mask layer more accurate as the size of transistor constantly reduces
Second mask layer exposes the gate structure 201 and positioned at 200 surface of section substrate of 201 two sides of gate structure,
The area size that then second mask layer exposes is larger, the mask layer by technique limited smaller, simplify described the
The formation process of two mask layers.Since the top surface of the grid layer is covered with the first mask layer, it is being subsequently formed
During opening 202, the top surface of the grid layer is not damaged.
It in the present embodiment, is NMOS transistor due to being formed by transistor, and the carrier of NMOS transistor is electricity
The transfer ability of son, electronics is higher, and therefore, the side wall of the opening 202 can be mentioned perpendicular to 200 surface of substrate to channel region
For sufficiently large stress.
In the present embodiment, the etching technics for forming the opening 202 is anisotropic dry etch process.The lining
Bottom 200 be silicon substrate, the parameter of the anisotropic dry etch process include: etching gas include chlorine, hydrogen bromide or
The mixed gas of chlorine and hydrogen bromide, the flow of hydrogen bromide be 200 standard milliliters per minute~800 standard milliliters are per minute, chlorine
The flow of gas be 20 standard milliliters per minute~100 standard milliliters are per minute, the flow of inert gas is 50 every point of standard milliliters
Clock~1000 standard milliliters are per minute, and the pressure of etching cavity is 2 millitorrs~200 millitorrs, and etch period is 15 seconds~60 seconds.
In other embodiments, being formed by transistor is PMOS transistor, and the stress layer material being subsequently formed is SiGe.
Since the carrier of PMOS transistor is hole, and the mobility in hole is lower, in order to obtain the channel region of PMOS transistor
Bigger stress needs to keep the stressor layers smaller to the distance of grid layer, it is therefore desirable to make the side wall of the opening to described
200 sunken inside of substrate of grid layer bottom, the side wall for making the opening and 200 surface of substrate are in " Σ " shape；It opens described in the formation
Mouthful when, using anisotropic dry etch process formed side wall perpendicular to the groove on 200 surface of substrate after, using it is each to
Anisotropic wet-etching technology etches the side wall and bottom surface of the groove；Due to the anisotropic wet-etching technology
Etch rate in<111>crystal orientation is most slow, and the crystal orientation on 200 surface of the substrate is<100>or<110>, therefore can be made
The side wall of formed groove forms apex angle, and the apex angle is to 200 sunken inside of substrate；And the anisotropic wet etching work
The etching liquid of skill is alkaline solution, and the alkaline solution is potassium hydroxide (KOH), sodium hydroxide (NaOH), lithium hydroxide
(LiOH), ammonium hydroxide (NH4) or one of tetramethylammonium hydroxide (TMAH) or multiple combinations OH.
Referring to FIG. 6, forming stressor layers 203 in 202 (as shown in Figure 5) of the opening.
In the present embodiment, being formed by transistor is NMOS transistor, therefore the material of the stressor layers 203 is carbonization
Silicon, the stressor layers 203 can provide tensile stress to the substrate 200 of 201 bottom of gate structure, to improve electronics in channel region
Mobility.In the stressor layers 203, also doped with N-shaped ion, to be formed in the substrate 200 of 201 two sides of gate structure
Source region and drain region.In other embodiments, the transistor is PMOS transistor, and the material of the stressor layers is SiGe.
The forming step of the stressor layers 203 includes: the side wall and bottom surface formation seed layer in the opening 202；
The stress material layer of the full opening 202 of filling is formed in the seed layer surface.The formation process of the seed layer is chemistry
Gas-phase deposition, physical gas-phase deposition or atom layer deposition process；The seed layer is used for epitaxial growth stress material
Layer.In the present embodiment, the formation process of the seed layer is atom layer deposition process, and the atom layer deposition process being capable of shape
There is good gradient coating performance, energy at the seed layer of thinner thickness, and using the seed layer that atom layer deposition process is formed
Enough it is tightly covered on the side wall and bottom surface of opening 202.
The formation process of the stress material layer is epitaxial deposition process.In the present embodiment, the material of the stress material layer
Material is silicon carbide, and formation process is selective epitaxial depositing operation, comprising: temperature is 500 degrees Celsius~800 degrees Celsius, air pressure
For 1 support~100 supports, deposition gases include silicon source gas (SiH4Or SiH2Cl2) and carbon-source gas (CH4、CH3Cl or CH2Cl2),
The flow of the silicon source gas and carbon-source gas is 1 standard milliliters/minute~1000 standard milliliters/minute.In addition, the selection
The gas of property epitaxial deposition process further includes HCl and H2, the flow of the HCl is 1 standard milliliters/minute~1000 standards milli
Liter/min, H2Flow be 0.1 standard liter/min~50 standard liter/mins.
It in the present embodiment, can be with doping process in situ in stress in the selective epitaxial deposition process
N-shaped ion is adulterated in material layer, the N-shaped ion includes phosphonium ion or arsenic ion；The original position doping process can regulate and control source
Doped ions distribution and Doped ions concentration in area or drain region inhibit short ditch so as to avoid Doped ions from spreading
Channel effect.In other embodiments, can be after forming stressor layers 203, or after being subsequently formed coating, infused with ion
Enter technique and adulterates N-shaped ion in the stressor layers 203.
Referring to FIG. 7, forming coating 204 on 203 surface of stressor layers, the coating 204 is interior doped with chalcogen
Element ion.
The coating 204 is located at 202 surface of stressor layers, for being converted into metallic silicon in subsequent silication technique for metal
The electric contacting layer of compound material；Due in stressor layers 203 doped with p-type ion or N-shaped ion to form source region or drain region, it is described
Electric contacting layer positioned at 203 surface of stressor layers is answered for reducing the electric interconnection structure being subsequently formed in electric contacting layer surface with described
Resistance between power layer 203 improves the performance of transistor to increase the operating current of transistor.
The formation process of the coating 204 is selective epitaxial depositing operation.In the present embodiment, the coating
204 material is the silicon carbide for adulterating oxygen group elements (Group VIA element) ion；The oxygen group elements ion be sulphion, selenium from
Son or tellurium ion；The technique that oxygen group elements ion is adulterated in coating 204 is doping process in situ or ion implantation technology.
In the present embodiment, the material of the coating 204 includes silicon carbide, and the material of the stressor layers 203 is carbon
SiClx, therefore when forming the coating 204, it can be based on forming identical technique when stressor layers 203, and doping oxygen is added
The technique of race's element ion doping, makes to form the technique of coating 204 relatively simple.
After adulterating oxygen group elements ion in coating 204, the subsequent electrical contact being transformed by the coating 204
Layer material is the metal silicide materials for adulterating oxygen group elements ion；The metal silicide materials of the doping oxygen group elements ion
For the metal silicide materials undoped with oxygen group elements ion, there is lower Schottky barrier, then carrier exists
The difficulty of transition between stressor layers 203 and the electric contacting layer reduces, between stressor layers 203 and the electric interconnection structure being subsequently formed
Resistance reduce, to improve the operating current of transistor, adapted to the manufacturing technology of the semiconductor devices of more microsize
Demand.
In the present embodiment, oxygen group elements ion is adulterated in coating 204 using doping process in situ；It mixes the original position
General labourer's artistic skill enough makes the doping concentration distribution for the oxygen group elements ion being doped in coating 204 more uniform, is conducive to improve
The quality of the subsequent electric contacting layer being transformed by the coating 204.Moreover, can be in coating using doping process in situ
The higher oxygen group elements ion of doping concentration in 204, so that being more advantageous to reduces the electric contacting layer being subsequently formed and stressor layers 203
Between contact resistance.In the present embodiment, the atom percentage concentration of the sulphion adulterated in the coating 204 is 0.1
~5%.
In the present embodiment, since the technique of doping oxygen group elements ion is doping process in situ, in coating 204
Interior adulterated oxygen group elements ion is sulphion；The technique of doping sulphion includes: outside the selectivity for forming coating 204
Prolong in depositing operation, sulphur source gas is added, the sulphur source gas includes one of hydrogen sulfide, sulfur dioxide, sulfur fluoride or more
Kind combination, the flow of the sulphur source gas are 1 standard milliliters/minute~1000 standard milliliters/minute.
In other embodiments, the oxygen group elements ion adulterated in coating 204 is plasma selenium or tellurium ion, adulterates institute
The technique for stating plasma selenium or tellurium ion includes: in the initial covering for forming carbofrax material using selective epitaxial depositing operation
Layer；Plasma selenium or tellurium ion are adulterated in the initial overlay layer using ion implantation technology, form coating 204.
The coating 204 with a thickness of 3 nanometers~50 nanometers, and oxygen group elements ion in the coating 204
Even distribution；Since subsequent needs are converted into electric contacting layer with the coating 204, then the thickness of the coating 204 determines
The thickness for the electric contacting layer being subsequently formed；In order to guarantee in subsequent silication technique for metal, metallic atom can be spread simultaneously uniformly
It is distributed in coating 204, the thickness of the coating 204 is unsuitable blocked up；Moreover, in order to guarantee to be formed by coating 204
Electric contacting layer resistance is smaller, and the thickness of the coating 204 is also unsuitable too small.
After forming the coating 204, the coating 204 is set to be converted into electrical contact using silication technique for metal
Layer, the material of the electric contacting layer are the metal silicide doped with oxygen group elements ion.Below by the formation to electric contacting layer
Step is illustrated.
Referring to FIG. 8, in 201 forming metal layer on surface 205 of the substrate 200, coating 204 and gate structure.
In the present embodiment, after forming 202 (as shown in Figure 5) of the opening, retain second mask layer, then institute
Stating the second mask layer can be as the exposure mask of the silication technique for metal；Second mask layer exposes the gate structure
201 and 204 surface of the coating, since the surface of the grid layer has the first mask layer, the metallic silicon chemical industry
Skill will not form metal silicide materials layer in the grid layer surface.
The material of the metal layer 205 is nickel or platinum, and the formation process of the metal layer 205 is chemical vapor deposition work
Skill, physical gas-phase deposition or atom layer deposition process.The metal layer 205 is used in subsequent first annealing process,
Metallic atom is provided to the coating 204, coating 204 is enabled to be converted into the electric contacting layer of metal silicide materials.
In the present embodiment, the material of the metal layer 205 is nickel；In subsequent first annealing process, nickle atom to
Diffusion in the coating 204, is capable of forming the nisiloy carbon compound for mixing sulphur, when the material compared to metal layer 205 is cobalt, institute
Stating the nisiloy carbon compound for mixing sulphur has lower Schottky barrier, is conducive to make the electric contacting layer being subsequently formed with lower
Resistance.
Referring to FIG. 9, making the metallic atom in metal layer 205 to coating 204 (such as Fig. 8 institute using the first annealing process
Show) in diffusion, so that coating 204 is converted into electric contacting layer 206.
In first annealing process, the metallic atom in metal layer 205 is spread into coating 204, with coating
204 material combines, and becomes metal silicide materials, the coating 204 is made to be converted into electric contacting layer 206.
In the present embodiment, the material of the coating 204 is the silicon carbide for mixing sulphur, is formed by electric contacting layer 206 and is
Mix the carbon nickle silicide of sulphur；For the carbon nickel suicide material for not mixing sulphur, the electric contacting layer 206 has lower Schottky
Potential barrier, then the contact resistance between the electric contacting layer 206 and stressor layers 203 is smaller, is conducive to further decrease transistor
Operating current improves the performance of transistor.
First annealing process is rapid thermal annealing, spike thermal annealing or laser thermal anneal.When the first annealing process is
When short annealing, the temperature of the rapid thermal annealing is 200~500 DEG C, and the time is 10 seconds~120 seconds, and protective gas is nitrogen
Or inert gas；When the first annealing process is spike thermal annealing, temperature is 300~600 DEG C, and protective gas is nitrogen or inertia
Gas；When the first annealing process is laser thermal anneal, temperature is 500~900 DEG C, and the time is 0.1 millisecond~2 milliseconds, protection
Gas is nitrogen or inert gas.
Being formed by 206 material of electric contacting layer is metal silicide materials, and the annealing process can drive metal layer 205
Interior metallic atom enters in coating 204, so that part of covering layer 204 is converted into electric contacting layer 206, and formed electricity connects
The thickness of contact layer 206 increases with the extension of annealing time.
Referring to FIG. 10, removing remaining metal layer 205 (as shown in Figure 9) after first annealing process.
The technique for removing the metal layer 205 is dry etch process or wet-etching technology.In one embodiment, it removes
The technique of the metal layer 205 is wet-etching technology, and the Etch selectivity of the wet-etching technology is preferable, to electric contacting layer
206, the damage of substrate 200 and gate structure 201 is smaller.
In one embodiment, after removing metal layer 205, additionally it is possible to remove the second mask layer；Described second is removed to cover
The technique of film layer is dry etch process or wet-etching technology.
It in the present embodiment, further include carrying out the second annealing process after removing remaining metal layer 205.Described
Two annealing process are for making metallic atom more uniformly spreading in electric contacting layer 206.Second annealing process and first
Annealing process is identical or different.
It in one embodiment, further include forming electric interconnection structure on 206 surface of electric contacting layer.The electric interconnection structure
Formation process include: electric contacting layer 206, substrate 200 and 201 surface of gate structure formed dielectric layer (not indicating), it is described
The surface of dielectric layer is higher than or is flush to the top surface of the gate structure 201, and the surface of the dielectric layer is flat, and described
The material of dielectric layer is one of silica, silicon nitride, silicon oxynitride, low-K dielectric material or multiple combinations；Etched portions institute
Dielectric layer is stated, forms the through-hole for exposing 206 surface of electric contacting layer in the dielectric layer；Conduction material is filled in the through-hole
Material, forms the electric interconnection structure.After filling the conductive material, additionally it is possible to using CMP process completely or
Part removes the conductive material of dielectric layer surface.
Since the resistivity of the electric contacting layer 206 is lower, and the contact resistance between electric contacting layer and stressor layers 203 compared with
Low, then the contact resistance between the electric interconnection structure and stressor layers 203 is lower, so that in the channel region between source region and drain region
Electric current increase, the problems such as leakage current is advantageously reduced with this.
In one embodiment, the electric contacting layer can also be after the through-hole formed in the dielectric layer, described in formation
It is formed before electric contacting layer.I.e. after forming coating, dielectric layer, institute are formed on coating, substrate and gate structure surface
The surface for stating dielectric layer is higher than or is flush to the top surface of the gate structure, and has in the dielectric layer and expose covering
The through-hole of layer；The coating of the via bottoms is set to be converted into electric contacting layer using silication technique for metal.
In another embodiment, being formed by transistor is high-k/metal gate (High k Metal Gate, abbreviation HKMG)
Transistor, the technique for forming the transistor includes rear grid (Gate Last) technique.Specifically, in the substrate 200 and covering
After 204 surface of layer form dielectric layer, and the dielectric layer exposes the top surface of the gate structure 201, described in removal
Grid layer forms gate openings in the dielectric layer；High-k dielectric layer (material is formed in the bottom surface of the gate openings
Dielectric coefficient be greater than or equal to 4)；Metal gate is formed on the high-k dielectric layer surface.
To sum up, in the present embodiment, after stress layer surface forms coating, oxygen group elements are adulterated in the coating
Ion；After subsequent use silication technique for metal makes coating be converted into electric contacting layer, it can make to be formed by electric contacting layer
Material is the metal silicide doped with oxygen group elements ion.Due to finding after study, adulterated in metal silicide materials
Oxygen group elements ion can reduce the Schottky barrier of metal silicide materials, therefore, be formed by the Schottky of electric contacting layer
Potential barrier reduces, then the resistance of the electric contacting layer reduces, and is formed by electrical interconnection so as to reduce the stressor layers with subsequent
Resistance between structure.Since stressor layers and the subsequent resistance being formed by between electric interconnection structure reduce, can be improved electric mutual
Link the electric current between structure and stressor layers, to improve the operating current for being formed by transistor, makes to be formed by transistor
Performance is more stable, and reliability improves.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of transistor characterized by comprising
Substrate is provided；
Gate structure is formed in the substrate surface；
Opening is formed in the substrate of the gate structure two sides；
Stressor layers are formed in the opening；
Coating is formed in the stress layer surface, the coating is interior doped with oxygen group elements ion；
The coating is set to be converted into electric contacting layer using silication technique for metal, the material of the electric contacting layer is doped with chalcogen
The metal silicide of element ion；
The forming step of the stressor layers includes: side wall and bottom surface the formation seed layer in the opening；In the seed
Layer surface forms the stress material layer for filling the full opening.
2. the forming method of transistor as described in claim 1, which is characterized in that the material of the stressor layers is silicon carbide；
Doped with N-shaped ion in the stressor layers.
3. the forming method of transistor as described in claim 1, which is characterized in that the formation process of the seed layer is chemistry
Gas-phase deposition, physical gas-phase deposition or atom layer deposition process；The formation process of the stress material layer is extension
Depositing operation.
4. the forming method of transistor as described in claim 1, which is characterized in that the material of the coating is doping chalcogen
The silicon carbide of element ion.
5. the forming method of transistor as claimed in claim 4, which is characterized in that the formation process of the coating is extension
Depositing operation.
6. the forming method of transistor as described in claim 1, which is characterized in that the chalcogen member adulterated in the coating
Plain ion is sulphion, plasma selenium or tellurium ion.
7. the forming method of transistor as claimed in claim 6, which is characterized in that adulterate oxygen group elements ion in coating
Technique be doping process in situ or ion implantation technology.
8. the forming method of transistor as claimed in claim 7, which is characterized in that using doping process in situ in coating
Adulterate oxygen group elements ion, and adulterate oxygen group elements ion be sulphion when, process gas include hydrogen sulfide, sulfur dioxide,
One of sulfur fluoride is a variety of.
9. the forming method of transistor as claimed in claim 6, which is characterized in that when the chalcogen member adulterated in the coating
When plain ion is sulphion, the atom percentage concentration of the sulphion is 0.1~5%.
10. the forming method of transistor as described in claim 1, which is characterized in that the coating with a thickness of 3 nanometers~
50 nanometers.
11. the forming method of transistor as described in claim 1, which is characterized in that the silication technique for metal includes: in institute
State substrate, coating and gate structure forming metal layer on surface；Using the first annealing process make the metallic atom in metal layer to
Diffusion, makes coating be converted into electric contacting layer in coating；After first annealing process, remaining metal layer is removed.
12. the forming method of transistor as claimed in claim 11, which is characterized in that the material of the metal layer be nickel or
Platinum.
13. the forming method of transistor as claimed in claim 11, which is characterized in that further include: removing remaining metal
After layer, the second annealing process is carried out.
14. the forming method of transistor as described in claim 1, which is characterized in that the gate structure includes: positioned at substrate
The gate dielectric layer on surface, positioned at gate dielectric layer surface gate electrode layer and be located at gate electrode layer and gate dielectric layer two sides side wall
With the side wall of substrate surface.
15. the forming method of transistor as claimed in claim 14, which is characterized in that the material of the gate dielectric layer is oxidation
Silicon；The material of the gate electrode layer is polysilicon.
16. the forming method of transistor as claimed in claim 15, which is characterized in that further include: forming the coating
Later, dielectric layer is formed in the substrate and cover surface, the dielectric layer exposes the top surface of the gate structure；
The gate electrode layer is removed, forms gate openings in the dielectric layer；High k is formed in the bottom surface of the gate openings to be situated between
Matter layer；Metal gate is formed on the high-k dielectric layer surface.
17. the forming method of transistor as described in claim 1, which is characterized in that the forming step of the opening include:
The substrate and gate structure surface form mask layer, and the mask layer exposes the section substrate table of the gate structure two sides
Face；Using the mask layer as exposure mask, the substrate is etched, forms opening in the substrate.
18. the forming method of transistor as claimed in claim 17, which is characterized in that form the etching technics packet of the opening
Include dry etch process.
19. the forming method of transistor as described in claim 1, which is characterized in that further include: on the electric contacting layer surface
Form electric interconnection structure.
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| CN1508846A (en) * | 2002-12-19 | 2004-06-30 | ��ʽ���������Ƽ� | Semiconductor device and manufacturing method thereof |
| WO2015001863A1 (en) * | 2013-07-04 | 2015-01-08 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| CN105280492A (en) * | 2014-07-21 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| CN1508846A (en) * | 2002-12-19 | 2004-06-30 | ��ʽ���������Ƽ� | Semiconductor device and manufacturing method thereof |
| WO2015001863A1 (en) * | 2013-07-04 | 2015-01-08 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| CN105280492A (en) * | 2014-07-21 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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