CN106158594A - Photoetching method and technique for applying thereof - Google Patents
Photoetching method and technique for applying thereof Download PDFInfo
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- CN106158594A CN106158594A CN201510181033.5A CN201510181033A CN106158594A CN 106158594 A CN106158594 A CN 106158594A CN 201510181033 A CN201510181033 A CN 201510181033A CN 106158594 A CN106158594 A CN 106158594A
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- 238000000034 method Methods 0.000 title claims abstract description 95
- 238000001259 photo etching Methods 0.000 title claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 148
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 21
- 239000012790 adhesive layer Substances 0.000 claims description 14
- 238000002360 preparation method Methods 0.000 claims description 7
- 230000007547 defect Effects 0.000 abstract description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- 230000000717 retained effect Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
This application provides a kind of photoetching method and technique for applying thereof.This photoetching method includes: step S1, arranges main photoresist layer on the dielectric layer of wafer surface, and dielectric layer at least includes SiOXLayer, and SiOXOn the surface of the silicon substrate that layer is set directly at wafer；Step S2, is exposed main photoresist layer；Step S3, the marginal area of main photoresist layer after exposure arranges secondary photoresist layer；Step S4, develops to the main photoresist layer after exposure and secondary photoresist layer, forms photoresist mask layer；And step S5, under the protection of photoresist mask layer, dielectric layer is performed etching.This photoetching method makes the SiO directly contacted with silicon substrate of wafer edge region after etchingXLayer is remained, and then makes the structure sheaf of follow-up setting directly not contact with the substrate silicon of wafer, and then avoids in heat treatment process the generation of the scaling defects that bigger stress therebetween causes, and improves the yield of device.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of photoetching method, self-alignment silicide technology,
Contact hole processing technology and active area anti-carve technique.
Background technology
During semiconductor fabrication process, the SiO that Waffer edge directly contacts with silicon substrateXLayer is often etched away, and silicon substrate is straight
Connecing and expose, the surface of silicon exposed when this portion arranges Ti layer, TiN layer, Si3N4Layer or the silicide layer containing Ti etc. and silicon
Thermal coefficient of expansion serious unmatched structure sheaf time, in heat treatment process, exist bigger between silicon substrate and these structure sheafs
Stress, this stress makes these structure sheafs of Waffer edge become scaling defects source and falls into the inside of wafer, affects device
Performance, causes the yield of device to reduce.
In order to improve above-mentioned edge scaling defects in prior art, frequently with starting brush or meeting after the etching of key stratum completes
Increase bevel etched.Start brush the least to the improvement result of above-mentioned Waffer edge scaling defects.Bevel etched can improve one
The edge scaling defects divided, it is impossible to thoroughly improve edge scaling defects, and the bevel etched that the method increases needs special setting
Standby, this will increase process costs, increase the wafer manufacture cycle, additionally the increase of this processing step too increase Waffer edge etc. from
The risk of son damage.
As can be seen here, a kind of photoetching method that can be effectively improved Waffer edge scaling defects is needed badly.
Summary of the invention
The application aims to provide a kind of photoetching method, self-alignment silicide technology, contact hole processing technology and active area and anti-carves technique,
To solve the problem of Waffer edge scaling defects in prior art.
To achieve these goals, according to an aspect of the application, it is provided that a kind of photoetching method, this photoetching method includes:
Step S1, arranges main photoresist layer on the dielectric layer of wafer surface, and above-mentioned dielectric layer at least includes SiOXLayer, and above-mentioned SiOX
Layer is set directly in the surface of silicon of above-mentioned wafer；Step S2, is exposed above-mentioned main photoresist layer；Step S3,
The marginal area of the above-mentioned main photoresist layer after exposure arranges secondary photoresist layer；Step S4, to the above-mentioned main photoresist layer after exposure
Develop with above-mentioned secondary photoresist layer, form photoresist mask layer；And step S5, in the protection of above-mentioned photoresist mask layer
Under, above-mentioned dielectric layer is performed etching.
Further, above-mentioned marginal area be extend internally from wafer outer edge 1～3mm region.
Further, 0.5～1 times of the thickness that thickness is above-mentioned main photoresist layer of above-mentioned secondary photoresist.
Further, when when arranging above-mentioned secondary photoresist layer, the rotating speed of litho machine is for arranging above-mentioned main photoresist layer, above-mentioned litho machine turns
0.25～0.5 times of speed.
Further, above-mentioned litho machine arranges time is the time arranging above-mentioned main photoresist layer the 0.5～2 of above-mentioned secondary photoresist layer
Times.
According to further aspect of the application, it is provided that a kind of self-alignment silicide technology, this self-alignment silicide technology includes light
Quarter process, above-mentioned photoetching process use above-mentioned photoetching method implement.
Further, above-mentioned self-alignment silicide technology includes: step S10, implements above-mentioned photoetching process and forms groove on wafer；
Step S20, arranges metal level with in above-mentioned groove on the surface of above-mentioned wafer；And step S30, to having above-mentioned metal level
Wafer carry out heat treatment, form metal silicide.
According to further aspect of the application, it is provided that a kind of contact hole preparation technology, this contact hole preparation technology includes photoetching
Journey, this photoetching process uses above-mentioned photoetching method to implement.
Further, above-mentioned contact hole preparation technology includes: step S10 ', implement above-mentioned photoetching process on wafer, form groove；
Step S20 ', on above-mentioned dielectric layer, in above-mentioned groove, set gradually adhesive layer and metal level；And step S30 ', in removal
State the above-mentioned adhesive layer of more than dielectric layer surface and above-mentioned metal level, form contact hole.
According to further aspect of the application, it is provided that a kind of active area anti-carves technique, and this active area anti-carves technique and includes photoetching
Journey, this photoetching process uses above-mentioned photoetching method to implement.
The photoetching method of application the application, after being exposed above-mentioned main photoresist layer, again at the marginal area of main photoresist layer
Secondary photoresist layer is set, still retains in follow-up development, in the etching process of step S5 without the secondary photoresist layer of exposure
In, due to the existence of the secondary photoresist layer of wafer edge region so that the dielectric layer of wafer edge region is retained so that be situated between
The SiO directly contacted with silicon substrate in matter layerXLayer is remained, so make the structure sheaf of follow-up setting not with wafer
Substrate silicon directly contacts, and then avoids in heat treatment process the generation of the scaling defects that bigger stress therebetween causes, and carries
The high yield of device.
Accompanying drawing explanation
The Figure of description of the part constituting the application is used for providing further understanding of the present application, and the application's is schematic real
Execute example and illustrate for explaining the application, being not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the process flow diagram of the photoetching method in a kind of preferred implementation of the application；
Fig. 2 shows the wafer cross structural representation formed after arranging dielectric layer on wafer；
Fig. 3 shows the cross-sectional view of the wafer after arranging photoresist layer in the structure shown in Fig. 2；
Fig. 4 shows that the section that the structure shown in Fig. 3 is exposed the wafer after rear edge region arranges secondary photoresist layer is tied
Structure schematic diagram；
Fig. 5 shows the cross-sectional view of the wafer after developing the structure shown in Fig. 4；
Fig. 6 shows the cross-sectional view that the structure shown in Fig. 5 performs etching the wafer after forming groove；
Fig. 7 shows the cross-sectional view of the wafer formed after deposit adhesion layer in the structure shown in Fig. 6；
Fig. 8 shows the cross-sectional view of the wafer formed after depositing metal level in the structure shown in Fig. 7；And
Fig. 9 shows that the wafer cross structure forming contact hole after removing metal level beyond the groove shown in Fig. 8 and adhesive layer is shown
It is intended to.
Detailed description of the invention
It it is noted that described further below is all exemplary, it is intended to provide further instruction to the application.Unless otherwise finger
Bright, all technology used herein and scientific terminology have and are generally understood that with the application person of an ordinary skill in the technical field
Identical meanings.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to restricted root according to this Shen
Illustrative embodiments please.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to
Including plural form, additionally, it should be understood that, when using term " to comprise " in this manual and/or time " including ",
It indicates existing characteristics, step, operation, device, assembly and/or combinations thereof.
For the ease of describing, space relative terms here can be used, as " ... on ", " ... top ",
" at ... upper surface ", " above " etc., be used for describing such as a device shown in the figure or feature and other devices or
The spatial relation of feature.It should be appreciated that space relative terms is intended to comprise except the described in the drawings orientation of device
Outside different azimuth in use or operation.Such as, if the device in accompanying drawing is squeezed, then it is described as " at other devices
Part or structure above " or " other devices or structure on " device after will be positioned as " other devices or construct under
Side " or " under other devices or structure ".Thus, exemplary term " ... top " can include " ... on
Side " and " in ... lower section " two kinds of orientation.This device can also other different modes location (90-degree rotation or be in its other party
Position), and space used herein above is described relatively make respective explanations.
Now, the illustrative embodiments according to the application it is more fully described with reference to the accompanying drawings.But, these exemplary enforcements
Mode can be implemented by multiple different form, and should not be construed to be limited solely to embodiments set forth herein.Should
When being understood by, it is provided that these embodiments are so that disclosure herein is thorough and complete, and by these exemplary realities
The design executing mode is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer and region
Thickness, and make to be presented with like reference characters identical device, thus description of them will be omitted.
As background technology is introduced, the method removing Waffer edge scaling defects in prior art is more complicated, relatively costly,
And can not effectively, thoroughly improve the scaling defects of Waffer edge, in order to solve the problems referred to above, present applicant proposes a kind of photoetching
Method.
The application one preferred embodiment in, it is provided that a kind of photoetching method, as it is shown in figure 1, this photoetching method includes:
Step S1, arranges main photoresist layer on the dielectric layer of wafer surface, and this dielectric layer at least includes SiOXLayer, and SiOXLayer is straight
Connect on the surface of the silicon substrate being arranged on above-mentioned wafer；Step S2, is exposed above-mentioned main photoresist layer；Step S3, is exposing
The marginal area of the above-mentioned main photoresist layer after light arranges secondary photoresist layer；Step S4, to exposure after above-mentioned main photoresist layer and
Above-mentioned secondary photoresist layer develops, and forms photoresist mask layer；And S5, under the protection of above-mentioned photoresist mask layer, right
Above-mentioned dielectric layer performs etching.Dielectric layer in the application refer to next step technique before the combination of all layers in surface of silicon
Layer, only includes SiO sometimesXLayer, includes SiO sometimesXLayer, Si3N4Layer and SiOXThe combination layer of layer, for different technique systems
Journey, dielectric layer represents different combination layers, but no matter what kind of combination layer dielectric layer is, all comprises and directly contacts with silicon substrate
SiOXLayer.
In above-mentioned photoetching method, after being exposed main photoresist layer, the marginal area at main photoresist layer arranges secondary light again
Photoresist layer, still retains in follow-up development without the secondary photoresist layer of exposure, in the etching process of step S5, due to
The existence of the secondary photoresist layer of wafer edge region so that the dielectric layer of wafer edge region is retained, finally makes dielectric layer
In the SiO directly contacted with silicon substrateXLayer is remained, so make the structure sheaf of follow-up setting not with the substrate of wafer
Silicon directly contacts, it is to avoid the generation of the scaling defects that bigger stress therebetween causes in heat treatment process, improves device
Yield.
In order to be further ensured that the dielectric layer of Waffer edge large area is not etched, and do not affect the quarter of other Region Medium layers
Erosion, the preferred above-mentioned marginal area of the application be wafer outer edge extend internally 1～3mm region.
In order to avoid main photoresist layer is impacted by the setting up procedure of secondary photoresist layer, simultaneously in order to ensure secondary photoresist layer not by
Destroying, so that its dielectric layer that can shelter marginal area is not etched, the thickness of the preferably secondary photoresist layer of the application is
0.5～1 times of the thickness of main photoresist layer.
Another of the application preferred embodiment in, when arranging secondary photoresist layer, the rotating speed of litho machine is for arranging main photoresist layer
Time 0.25～0.5 times of litho machine rotating speed, such set-up mode make photoresist rotate dry during be retained in marginal zone
Territory, does not transfers to other region beyond marginal area, and those skilled in the art can be according to the thickness of secondary photoresist layer with brilliant
The factors such as the size of sheet determine the rotating speed of litho machine when arranging secondary photoresist layer.
In order to better control over the thickness of secondary photoresist layer, avoid it to flow in other regions, the preferred above-mentioned light of the application simultaneously
Quarter, machine arranged 0.5～2 times that time is the time arranging above-mentioned main photoresist layer of above-mentioned secondary photoresist layer.
The photoetching method of the application can apply in the most all of photoetching implementation process, so that the application light
Carving method solves problem Waffer edge defect easily occur pointedly, preferably the photoetching method of the application is applied to autoregistration
Silicide process, contact hole processing technology and active area anti-carve technique, illustrate respectively below for three kinds of techniques.
When the critical dimension reduction of device is to time below 1 μm, the series connection diffusion resistance of device and the contact resistance performance shadow to device
Ringing and highlight all the more, at this moment, self-alignment silicide technology arises at the historic moment, and this technique forms silicide on source, leakage and grid, passes through
Metal reacts with exposed silicon substrate and reaches autoregistration.This technique reduces device by covering the silicide of high conductivity in source and drain
Diffusion resistance and contact resistance.
When being applied in self-alignment silicide technology by the photoetching method of the application, this self-alignment silicide technology makes wafer limit
The SiO that edge directly contacts with silicon substrateXLayer is not etched away, in follow-up technique, and SiOXLayer can be etched away a part,
But still can retain a part, the metal level that this avoid follow-up setting directly contacts with silicon substrate so that heat treated
Cheng Zhong, will not cause therebetween stress excessive generation scaling defects owing to thermal coefficient of expansion does not mates.Avoid from right
Quasi-silicide process produces scaling defects, and then affects the performance of device and the yield of product.
Another of the application preferred embodiment in, the most above-mentioned self-alignment silicide technology includes: step S10, in enforcement
State photoetching process on wafer, form groove, in order to preferably form groove, this step is first use dry etching removal part
Exposed SiOXDielectric layer, forms shallow grooves, is then removed with secondary photoresist layer by main photoresist layer, and recycling wet etching goes
Except residue SiO in shallow groovesX, form groove, the simultaneously SiO of Waffer edgeXThe part of layer is removed, and remains most
SiOXLayer；Step S20, arranges metal level with in groove on the surface of above-mentioned wafer, it is generally preferable to metal level is nickel (Ni)
With cobalt (Co)；And step S30, the wafer with above-mentioned metal level is carried out heat treatment so that metal reacts with silicon substrate,
Form metal silicide.
When the photoetching method of the application is applied in contact hole processing technology, after above-mentioned main photoresist layer is exposed,
Marginal area at main photoresist layer arranges secondary photoresist layer again, without the secondary photoresist layer of exposure in follow-up development still
Retain, in etching process, due to the existence of the secondary photoresist layer of wafer edge region so that the dielectric layer of wafer edge region
Retained, and then made the SiO directly contacted with silicon substrate in dielectric layerXLayer is remained, so that follow-up at medium
The tack coat arranged on layer does not directly contact with the substrate silicon of wafer, and then avoids in heat treatment process, due to silicon substrate and Ti
The peeling that the thermal expansion coefficient difference of layer, TiN layer or the silicide layer containing Ti makes more greatly stress therebetween cause more greatly lacks
The generation fallen into, and then improve the yield of device.
In order to use simple efficient mode to prepare contact hole, the preferred above-mentioned contact hole preparation technology of the application includes: step S10 ',
Implement above-mentioned photoetching process on wafer, form groove；Step S20 ', adhesive layer and metal level are set on dielectric layer, in groove；
And step S30 ', remove the above-mentioned adhesive layer of more than above-mentioned dielectric layer surface and above-mentioned metal level, form contact hole.
Additionally, prior art fills SiO at STI (shallow-trench isolation)XAfter, need the surface of wafer is planarized, by
Different in active area effective area, different effective areas causes SiO on its surfaceXThe area of layer is different, so at chemical machinery
When grinding (Chemical Mechanical Polish is called for short CMP), the different SiO on active areaXThe grinding rate of layer is not
With, it is impossible to synchronize to reach to be ground to identical height, in order to avoid the generation of this phenomenon, it is ensured that can more uniformly difference be had
The SiO of area surfaceXLayer etches away, and anti-carves technique frequently with active area, the SiO being first etched with on area surfaceXLayer, the most again
Use CMP by the SiO of surfaces of active regionsXLayer grinds to be removed.But the SiO that in this technique, wafer edge region is filledXLayer
Also can be etched removal, follow-up through removing Si3N4, after the technique such as depositing polysilicon and etches polycrystalline silicon, wafer edge region
The SiO directly contacted with silicon substrateXLayer also can be removed, and causes silicon substrate exposed, the structure sheaf of follow-up setting such as Ti layer,
TiN layer, Si3N4Layer or the silicide layer containing Ti just directly contact with silicon substrate, in heat treatment process, due to the thermal expansion of the two
Coefficient does not mates, and makes stress therebetween relatively big, produces scaling defects.
Therefore, when the photoetching method of the application being applied to active area and anti-carving in technique, directly connecing with silicon substrate of Waffer edge
The SiO touchedXLayer will not be etched completely away, and then the structure sheaf avoiding follow-up setting directly contacts with silicon substrate, it is to avoid heat
Processing procedure produces scaling defects, improves performance and the yield of device.
In order to make those skilled in the art better understood when the photoetching method in the application, it is applied to tungsten contact hole with it below
Manufacture method as a example by, describe in detail the application technical scheme.
Thermal oxide is used to have deposit SiO on the active area wafer 100 with isolation area2Layer 200, forms the structure shown in Fig. 2；
Use conventional set-up mode at the SiO of the structure shown in Fig. 22Photoresist is set on the surface of layer 200, forms key light and carve
Glue-line 300, as it is shown on figure 3, the thickness of main photoresist layer 300 is about 0.3 μm, litho machine when forming main photoresist layer 300
Rotating speed be 2000r/min, the time is 20s.
Main photoresist layer 300 shown in Fig. 3 is exposed, the edge on the surface of main photoresist layer 300 the most after exposure
Arranging secondary photoresist layer 400 as shown in Figure 4 on region, rotating speed when arranging is 1000r/min, and the time is 15s, the pair of formation
The thickness of photoresist layer 400 is 0.2 μm.
Structure shown in Fig. 4 is developed, the photoresist through overexposure is removed, forms photoresist mask layer, such as Fig. 5 institute
Show.Use RIE dry etching to the SiO in Fig. 52Layer 200 performs etching, and forms the groove 201 shown in Fig. 6, has etched
Photoresist mask layer, during etching, the SiO of Waffer edge is removed after one-tenth2Layer is due to the secondary light being photo-etched in glue mask layer
The protection of photoresist layer and remain, and then make the SiO of marginal area in Fig. 62Layer 200 is not etched away, this example medium
Layer is exactly SiO2Layer.
Structure shown in Fig. 6 deposits TiN adhesive layer 500, forms the structure shown in Fig. 7.
To the TiN adhesive layer 500 shown in Fig. 7 away from above-mentioned SiO2Sputter tungsten metal level 600 on the surface of layer 200, form Fig. 8
Shown structure.Tungsten is full of groove 201 as shown in Figure 8.
Structure shown in Fig. 8 is carried out cmp, removes the adhesive layer 500 beyond groove and tungsten metal level 600, formed
Contact hole 202 shown in Fig. 9.
The method of above-mentioned formation contact hole, the marginal area after main photoresist layer 300 exposes arranges secondary photoresist layer 400 so that
During etching, SiO2Layer 200 is not etched away under the sheltering of secondary photoresist layer 400, and then makes marginal area
TiN adhesive layer 500 the most directly contacts with the silicon in substrate 100, it is to avoid in adhesive layer deposition process, TiN adhesive layer 500
And the bigger stress between substrate 100 makes the TiN adhesive layer 500 of marginal area peel off becomes scaling defects.
As can be seen from the above description, the embodiment that the application is above-mentioned achieves following technique effect:
In the photoetching method of the application, after being exposed above-mentioned main photoresist layer, the marginal area at main photoresist layer sets again
Put secondary photoresist layer, still retain in follow-up development without the secondary photoresist layer of exposure, in the etching process of step S5,
Existence due to the secondary photoresist layer of wafer edge region so that the dielectric layer of wafer edge region is retained, and then make to be situated between
The SiO directly contacted with silicon substrate in matter layerXLayer is remained so that the structure sheaf of follow-up setting not with the lining of wafer
End silicon directly contacts, and then avoids in heat treatment process, due to the generation of the scaling defects that bigger stress therebetween causes,
Improve the yield of device.
The foregoing is only the preferred implementation of the application, be not limited to the application, for those skilled in the art
For Yuan, the application can have various modifications and variations.All within spirit herein and principle, any amendment of being made,
Equivalent, improvement etc., within should be included in the protection domain of the application.
Claims (10)
1. a photoetching method, it is characterised in that described photoetching method includes:
Step S1, arranges main photoresist layer on the dielectric layer of wafer surface, and described dielectric layer at least includes SiOXLayer, and
Described SiOXOn the surface of the silicon substrate that layer is set directly at described wafer；
Step S2, is exposed described main photoresist layer；
Step S3, the marginal area of described main photoresist layer after exposure arranges secondary photoresist layer；
Step S4, develops to the described main photoresist layer after exposure and described secondary photoresist layer, forms photoresist mask
Layer；And
Step S5, under the protection of described photoresist mask layer, performs etching described dielectric layer.
Photoetching method the most according to claim 1, it is characterised in that described marginal area is for extend internally from wafer outer edge
The region of 1～3mm.
Photoetching method the most according to claim 1, it is characterised in that the thickness of described secondary photoresist is described main photoresist layer
0.5～1 times of thickness.
Photoetching method the most according to claim 1, it is characterised in that when arranging described secondary photoresist layer, the rotating speed of litho machine is for setting
Put during described main photoresist layer 0.25～0.5 times of described litho machine rotating speed.
Photoetching method the most according to claim 4, it is characterised in that described litho machine arranges the time of described secondary photoresist layer and is
0.5～2 times of time of described main photoresist layer is set.
6. a self-alignment silicide technology, including photoetching process, it is characterised in that described photoetching process uses Claims 1 to 5
According to any one of photoetching method implement.
Self-alignment silicide technology the most according to claim 6, it is characterised in that described self-alignment silicide technology includes:
Step S10, implements described photoetching process and forms groove on wafer；
Step S20, arranges metal level with in described groove on the surface of described wafer；And
Step S30, carries out heat treatment to the wafer with described metal level, forms metal silicide.
8. a contact hole preparation technology, including photoetching process, it is characterised in that described photoetching process uses in Claims 1 to 5 appoints
One described photoetching method is implemented.
Contact hole preparation technology the most according to claim 8, it is characterised in that described contact hole preparation technology includes:
Step S10 ', implement described photoetching process on wafer, form groove；
Step S20 ', on described dielectric layer, in described groove, set gradually adhesive layer and metal level；And
Step S30 ', remove the described adhesive layer of more than described dielectric layer surface and described metal level, form contact hole.
10. active area anti-carves a technique, including photoetching process, it is characterised in that described photoetching process uses Claims 1 to 5
According to any one of photoetching method implement.
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| CN201510181033.5A CN106158594A (en) | 2015-04-16 | 2015-04-16 | Photoetching method and technique for applying thereof |
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| CN108878353A (en) * | 2018-06-27 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | The preparation method of contact hole on a kind of wafer |
| CN110027123A (en) * | 2018-12-27 | 2019-07-19 | 李宗杰 | Quartz photolithography wafer and cutting technique |
| CN111199872A (en) * | 2020-01-09 | 2020-05-26 | 长江存储科技有限责任公司 | Forming method of wafer edge protection layer, three-dimensional memory and preparation method of three-dimensional memory |
| WO2021082337A1 (en) * | 2019-10-30 | 2021-05-06 | 武汉新芯集成电路制造有限公司 | Method for improving tip discharge defect and manufacturing method for semiconductor device |
| CN113223954A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for improving wafer burrs caused by groove etching |
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| WO2023272783A1 (en) * | 2021-07-02 | 2023-01-05 | 长鑫存储技术有限公司 | Preparation method for semiconductor device, and semiconductor device |
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| CN108646516A (en) * | 2017-08-28 | 2018-10-12 | 睿力集成电路有限公司 | Photoresist coating equipment |
| CN108878353A (en) * | 2018-06-27 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | The preparation method of contact hole on a kind of wafer |
| CN110027123A (en) * | 2018-12-27 | 2019-07-19 | 李宗杰 | Quartz photolithography wafer and cutting technique |
| CN110027123B (en) * | 2018-12-27 | 2021-03-16 | 李宗杰 | Quartz photoetching wafer and cutting technology |
| WO2021082337A1 (en) * | 2019-10-30 | 2021-05-06 | 武汉新芯集成电路制造有限公司 | Method for improving tip discharge defect and manufacturing method for semiconductor device |
| CN111199872B (en) * | 2020-01-09 | 2023-06-09 | 长江存储科技有限责任公司 | Forming method of wafer edge protection layer, three-dimensional memory and manufacturing method thereof |
| CN111199872A (en) * | 2020-01-09 | 2020-05-26 | 长江存储科技有限责任公司 | Forming method of wafer edge protection layer, three-dimensional memory and preparation method of three-dimensional memory |
| WO2022028113A1 (en) * | 2020-08-05 | 2022-02-10 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
| US12048139B2 (en) | 2020-08-05 | 2024-07-23 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure using first mask layer and first photoresist layer to selectively etch stack on complete die region |
| CN113223954A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for improving wafer burrs caused by groove etching |
| WO2023272783A1 (en) * | 2021-07-02 | 2023-01-05 | 长鑫存储技术有限公司 | Preparation method for semiconductor device, and semiconductor device |
| US12243743B2 (en) | 2021-07-02 | 2025-03-04 | Changxin Memory Technologies, Inc. | Method for preparing semiconductor device |
| CN117219502A (en) * | 2023-11-07 | 2023-12-12 | 天通控股股份有限公司 | Single-sided thinning method of bonding wafer |
| CN117219502B (en) * | 2023-11-07 | 2024-01-12 | 天通控股股份有限公司 | Single-sided thinning method of bonding wafer |
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