CN106157860A - Anti-noise narrow-frame display - Google Patents

Abstract

A noise-resistant narrow-frame display (20) comprises: a first drive circuit (22) having a first drive transistor (M22), the first drive transistor having a first area (B); a second drive circuit (13) controlling the conduction and cutoff of a plurality of pixel transistors (17) in a display area (16), the second drive circuit having a second drive transistor (M13), the second drive transistor having a second area (D), the second area being larger than the first area, the first drive circuit driving the second drive circuit; and a source drive circuit (14) coupled to the plurality of pixel transistors, outputting a plurality of display signals so that the display displays a picture. The beneficial effect of implementing the noise-resistant narrow-frame display of the present invention is that the display can meet the design requirements of a narrow frame and reduce the influence of noise on the display.

Description

Noise Resistant Narrow Bezel Display

technical field

The invention relates to the field of displays, more specifically, to a noise-resistant narrow-frame display.

Background technique

As the concept of system on glass (SOG, system on glass) has been proposed one after another, many products recently integrate the gate scanning driving circuit in the display driving circuit on the glass, which is a GOA (gate driver on array) circuit. The GOA circuit has many advantages. In addition to reducing the area of the display frame to achieve a narrow frame, it can also reduce the use of gate scanning driver ICs.

Please refer to FIG. 1 , which is a circuit diagram of a common display in the prior art. As shown in the figure, the display 10 includes a control circuit 11, a plurality of first driver circuits 12, a plurality of second driver circuits 13, a source driver circuit 14, a pixel load 15 (pixel loading), a display area 16, and a plurality of pixel transistors 17. The first driving circuit 12 includes a first driving transistor M12, the second driving circuit 13 includes a second driving transistor M13, and the area A1 of the first driving transistor M12 is the same as the area A1 of the second driving transistor M13.

Furthermore, since the currently designed GOA circuit 12 requires the control circuit 11 to provide basic signals, and the signal strength output by the control circuit 11 is relatively high, the signal strength received by the first-stage GOA circuit 12 in the GOA circuit string from the control circuit 11 It will be different from the signal strength received by the subsequent GOA circuit 13 . In this way, the characteristics of the scan signals output by each stage of the GOA circuit will be inconsistent. Therefore, the pixel load 15 is generally arranged around the display area 16, and then the pixel load 15 is used to couple with the first-stage GOA circuit 12, so that the characteristics of the scanning signal output by the first-stage GOA circuit are relatively consistent.

However, the above method will consume the bezel area A, which violates the requirements of the narrow bezel display. Therefore, the present invention proposes a narrow bezel display different from the general solution to overcome the above problems.

Contents of the invention

The technical problem to be solved by the present invention is that, for the prior art, the method of coupling the pixel load with the first-level GOA circuit to make the characteristics of the scanning signal output by the first-level GOA circuit more consistent will consume the defect of the frame area , providing a noise-resistant narrow bezel display.

The present invention solves the technical problem, and the adopted technical solution is to provide a noise-resistant narrow-frame display, which includes a first drive circuit, a first drive transistor, and a first drive transistor with a first area; a second drive circuit, Controlling the on and off of multiple pixel transistors in the display area, the second drive circuit has a second drive transistor, the second drive transistor has a second area, the second area is larger than the first area, and the first drive circuit drives the second drive circuit ; The source driving circuit is coupled with the pixel transistors and outputs a plurality of display signals so that the display can display a frame.

In the anti-noise narrow frame display of the present invention, the first area is 33%-66% of the second area.

In the anti-noise narrow frame display of the present invention, the first driving transistor has a first parasitic capacitance, the second driving transistor has a second parasitic capacitance, and the capacitance of the first parasitic capacitance is smaller than the capacitance of the second parasitic capacitance.

In the anti-noise narrow frame display of the present invention, the first driving circuit is a dummy gate driving circuit, and the second driving circuit is a gate driving circuit.

In the anti-noise narrow frame display of the present invention, it also includes: a control circuit, coupled to the first drive circuit, and outputs a start signal to the first drive circuit; wherein, the first drive circuit outputs a drive signal according to the start signal To the second driving circuit, the second driving circuit outputs a scanning signal according to the driving signal, so as to control the on and off of the pixel transistors through the scanning lines.

Further, in the anti-noise narrow frame display of the present invention, a third drive circuit is also included, the third drive circuit is connected to the second drive circuit and is located on the first side or the second side of the second drive circuit, when the second drive circuit When the circuit scans the display area in one direction, the first drive circuit and the third drive circuit are located on the first side of the second drive circuit; when the second drive circuit scans the display area bidirectionally, the first drive circuit is located on the first side of the second drive circuit. side, the third driving circuit is located on the second side of the second driving circuit, the first driving circuit and the third driving circuit are dummy gate driving circuits, and the second driving circuit is a gate driving circuit.

Implementing the anti-noise narrow-frame display of the present invention has the following beneficial effects: the characteristics of the scanning signal are more consistent without setting pixel loads on the periphery of the display area, which meets the needs of the narrow-frame display, and through the present invention The design of the gate drive circuit reduces the influence of noise on the display.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

Fig. 1 is a circuit diagram of a common display in the prior art;

Fig. 2 is the circuit diagram of the embodiment of the anti-noise narrow frame display of the present invention;

Fig. 3 is the circuit diagram of the embodiment of the gate drive circuit of the anti-noise narrow frame display of the present invention;

Fig. 4 is a schematic diagram of an embodiment of the anti-noise narrow-frame display of the present invention during unidirectional scanning;

FIG. 5 is a schematic diagram of an embodiment of the anti-noise narrow-frame display of the present invention during bidirectional scanning.

Symbol Description:

10 monitor 11 Control circuit 12 first drive circuit 13 Second drive circuit 14 Source drive circuit 15 pixel load 16 display area 17 pixel transistor 20 monitor twenty two first drive circuit twenty four third drive circuit 25 Fourth drive circuit 221 scanning unit 222 anti-noise unit 223 discharge circuit A border area A1 area

B first area C border area Cb capacitor Clk frequency signal D. second area DRI drive signal E. forward scan f reverse scan H1 first side H2 second side M12 first drive transistor M13 second drive crystal M22 first drive transistor OUT(n) output S1 scan signal Vddf forward signal Vddr reverse signal VST start signal VST1 first start signal VST2 second start signal

detailed description

In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation manners of the present invention will now be described in detail with reference to the accompanying drawings.

Please refer to FIG. 2 , which is a circuit diagram of an embodiment of the anti-noise narrow-frame display of the present invention. As shown in the figure, the display 20 includes a control circuit 11 , a plurality of first driving circuits 22 , a plurality of second driving circuits 13 , a source driving circuit 14 , a display area 16 , and a plurality of pixel transistors 17 . The control circuit 11 , the second driving circuit 13 and the source driving circuit 14 control the display area 16 to make the display area 16 display a frame, wherein the second driving circuit 13 is a gate driver. The first driving circuit 22 has a first driving transistor M22 having a first area B, and the second driving circuit 13 has a second driving transistor M13 having a second area D. The second area D is larger than the first area B.

Furthermore, the control circuit 11 is coupled to the first driving circuit 22, and outputs a start signal VST to the first driving circuit 22. After receiving the start signal VST from the control circuit 11, the first drive circuit 22 outputs the start signal VST according to the start signal VST. A driving signal DRI is sent to the second driving circuit 13 to drive the second driving circuit 13 . The second driving circuit 13 outputs scan signals to the plurality of pixel transistors 17 according to the driving signal DRI to control the plurality of pixel transistors 17 . In other words, the second driving circuit 13 controls the turn-on and turn-off of the plurality of pixel transistors 17 in the display area 16 via the scan lines to display images. The source driving circuit 14 is coupled to a plurality of pixel transistors 17 and outputs a plurality of display signals to the display area 16 to enable the display 20 to display images.

Please refer to FIG. 2 again. In order to meet the requirement of a narrow frame, the present invention does not set the pixel load 15 (FIG. 1) on the periphery of the display area 16, that is, the non-display area. The range of using the bezel area A is significantly reduced in common displays in the art. Moreover, the first driving circuit 22 of the present invention is not coupled to the display area 16, and does not control a plurality of pixel transistors 17, so the first driving circuit 22 is a dummy gate driver and does not output scanning Signal to display area 16. The first driving circuit 22 serves as a buffer circuit for the second driving circuit 13 , so the start signal VST output by the control circuit 11 is buffered by the first driving circuit 22 , and the characteristics of the scanning signal output by the second driving circuit 13 are relatively uniform.

Moreover, in order to reduce the noise generated by the first driving circuit 22 and affect the stability of the scanning signal, the present invention reduces the area of the first driving transistor M22 of the first driving circuit 22, and the first driving transistor M22 mainly serves as a charging and discharging function. , so the reduction of the area of the first driving transistor M22 will have a significant effect on noise reduction. Wherein, the area of the first driving transistor M22 is 33%˜66% of the area of the second driving transistor M13.

In addition, reducing the area of the first driving transistor M22 will have a significant effect on reducing noise, because when the area of the first driving transistor M22 is shrinking, the capacitance value of the first parasitic capacitor of the first driving transistor M22 will also decrease accordingly. . Similarly, the first driving transistor M22 has a first parasitic capacitance, and the second driving transistor M13 also has a second parasitic capacitance, and the capacitance of the first parasitic capacitance is smaller than the capacitance of the second parasitic capacitance. In this way, the present invention reduces the influence of the first parasitic capacitance on the scan signal.

Please refer to FIG. 3 , which is a circuit diagram of an embodiment of the gate driving circuit of the anti-noise narrow bezel display of the present invention. Firstly, following the above-mentioned present invention, the area of the first driving transistor M22 is reduced to reduce the influence of the first parasitic capacitance of the first driving transistor M22 on the output terminal OUT(n). Moreover, as shown in the third figure, the first drive circuit 22 can be designed with a scanning unit 221, an anti-noise unit 222, a discharge circuit 223 and a capacitor Cb, and the first drive circuit 22 of the present invention is used for a single Scanning or bi-directional scanning display 20, and improve the anti-noise effect.

In addition, during unidirectional scanning or bidirectional scanning, the first driving circuit 22 can further receive the forward signal Vddf, the first start signal VST1, the reverse signal Vddr, the second start signal VST2 and the frequency signal Clk, etc., the present invention The application of the first drive circuit 22 is not limited, and the technical idea of reducing the influence of noise by reducing the area of the first drive transistor M22 of the present invention can also be applied to other fields, such as: power supplies or controllers, etc., so this The embodiments of the invention are only described in the field of displays, and do not limit that the technical idea of the present invention can only be used in the field of displays.

Please refer to FIG. 4 , which is a schematic diagram of an embodiment of the anti-noise narrow bezel display of the present invention during unidirectional scanning. As shown in the figure, the display 20 further includes a third driving circuit 24 , and the third driving circuit 24 is also a dummy gate driving circuit like the first driving circuit 22 . When the display 20 is unidirectionally scanning E, the second driving circuit 13 unidirectionally scans the display area 16, the third driving circuit 24 and the first driving circuit 22 are all arranged on the first side H1 of the second driving circuit 13, and the third The driving circuit 24 and the first driving circuit 22 are connected to the second driving circuit 13 at the first side H1 to serve as a buffer circuit for the second driving circuit 13 . In addition, the third driving circuit 24 and the first driving circuit 22 can also be disposed on the second side H2 of the second driving circuit 13 , which can also achieve unidirectional scanning operation. Therefore, the above is only to illustrate the positions where the driving circuits 22 and 24 can be installed during unidirectional scanning, but not to limit the installation positions of the driving circuits 22 and 24 in the present invention.

Please refer to FIG. 5 , which is a schematic diagram of an embodiment of the anti-noise narrow bezel display when bidirectional scanning is invented. As shown in the figure, the display 20 also includes a fourth driving circuit 25, and the fourth driving circuit 25 and the third driving circuit 24 are both virtual gate driving circuits, but in this embodiment, the fourth driving circuit 25 is only used to replace the third driving circuit. Circuit 24 serves as an illustration of a bi-directional scanning embodiment. When the display 20 bidirectionally scans the E and F display areas 16, the first driver circuit 22 is arranged on the first side H1 of the second driver circuit 13, and the fourth driver circuit 25 is arranged on the second side H2 of the second driver circuit 13, so When the second driving circuit 13 bidirectionally scans E and F, the first driving circuit 22 and the fourth driving circuit 25 can be respectively used as buffer circuits of the second driving circuit 13 to reduce the influence of noise on the scanning signal.

To sum up, the present invention is an anti-noise narrow frame display, which includes a first driving circuit, a second driving circuit and a source driving circuit. The first driving circuit has a first driving transistor, and the first driving transistor has a first area. The second drive circuit controls the turn-on and cut-off of multiple pixel transistors in a display area, the second drive circuit has a second drive transistor, the second drive transistor has a second area, the second area is larger than the first area, and the first drive circuit Drive the second drive circuit. The source driving circuit is coupled to the pixel transistors and outputs a plurality of display signals to make the display display a frame.

Embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementations, and the above-mentioned specific implementations are only illustrative, rather than restrictive. Those of ordinary skill in the art will Under the enlightenment of the present invention, many forms can also be made without departing from the gist of the present invention and the protection scope of the claims, and these all belong to the protection of the present invention.

Claims (6)

1. an antimierophonic narrow border display, it is characterised in that comprise:

First drive circuit (22), has the first driving transistor (M22), and the first driving transistor has First area (B)；

Second drive circuit (13), the conducting of multiple pixel transistors (17) of control viewing area (16) With cut-off, the second drive circuit (13) has the second driving transistor (M13), the second driving transistor Having second area (D), second area (D) is more than the first area (B), the first drive circuit (22) Drive the second drive circuit (13)；

Source electrode drive circuit (14), couples with the plurality of pixel transistor (17), exports multiple display Signal, so that display (20) shows a picture.

2. narrow border display according to claim 1, it is characterised in that the first area (B) is The 33%～66% of second area (D).

3. narrow border display according to claim 1, it is characterised in that the first driving transistor (M22) having the first parasitic capacitance, the second driving transistor (M13) has the second parasitic capacitance, the The capacitance of one parasitic capacitance is less than the capacitance of the second parasitic capacitance.

4. narrow border display according to claim 1, it is characterised in that the first drive circuit (22) For empty gate driver circuit, the second drive circuit (13) is gate driver circuit.

5. narrow border display according to claim 1, it is characterised in that also comprise:

Control circuit (11), couples with the first drive circuit (22), and output initial signal (VST) is extremely First drive circuit (22)；

Wherein, the first drive circuit (22) is according to described initial signal (VST) output drive signal (DRI) To the second drive circuit (13), the second drive circuit (13) is swept according to described driving signal (DRI) output Retouch signal (S1), to be controlled conducting and the cut-off of the plurality of pixel transistor (17) by scan line.

6. narrow border display according to claim 1, it is characterised in that also comprise:

3rd drive circuit (24), the 3rd drive circuit (24) be connected with the second drive circuit (13) and It is positioned at the first side (H1) or the second side (H2) of the second drive circuit (13), when the second drive circuit (13) During simple scanning viewing area (16), the first drive circuit (22) and the 3rd drive circuit (24) are positioned at the First side (H1) of two drive circuits (13), when the second drive circuit (13) bilateral scanning viewing area (16) When, the first drive circuit (22) is positioned at first side (H1) of the second drive circuit (13), and the 3rd drives Circuit (24) is positioned at second side (H2) of the second drive circuit (13), the first drive circuit (22) with 3rd drive circuit (24) is empty gate driver circuit, and the second drive circuit (13) is gate driver circuit.