CN1061500C - Device for Uniformly Scaling and Resizing Digital Images - Google Patents

Abstract

An apparatus for uniformly scaling digital image sizes, an original digital image having N successive original image data and a destination digital image having M successive destination digital images. M is larger than N, the linear interpolation of the N-th and N + 1-th original image data generates a residual interpolation image data, when the quotient S is obtained by (M-N)/(N-1) and N is the minimum value of N +1 xS which is not less than sxN, the interpolation image data is inserted between the N-th and N + 1-th original image data. M < N, the address generator controls the memory unit to output the selected original image data. Subsequent original image data output by the memory unit is offset from only previous original image data output by the memory unit by a value V or V +1, V being a quotient of N/M.

Description

Device for Uniformly Scaling and Resizing Digital Images

The invention relates to an image processing device, in particular to a device capable of real-time, two-dimensional and uniform expansion and contraction of digital image processing size.

In the application of multimedia computers, it is very important to have the ability to integrate digital images. Before integrating a digital image (DIGITAL IMAGE) with another digital image, the digital image must be processed first, and the processing method is usually by adding The digital image size (hereinafter referred to as stretching (SCALING UP)), reducing the digital image size (hereinafter referred to as compression (SCALING DOWN)), cropping a selected portion of the digital image, translating a selected portion of the digital image to another area and so on to complete.

The stretching and compression of the above-mentioned digital image is accomplished by a specially designed computer. The digital image includes a plurality of scanning lines, and each scanning line also includes a plurality of pixel data (PIXEL DATA), and the stretching of the digital image is performed in each scanning line. Perform linear interpolation (LINEAR INTERPOLATION) between two scanning lines to obtain at least one interpolation scanning line between the two scanning lines, and perform linear interpolation between every two scanning pixels to obtain the interpolation At least one interpolated pixel data between two scanned pixels. The compression of the digital image is achieved by deleting part of the scan lines of the digital image and deleting part of the pixel data of each retained scan line.

For the stretching of digital images, it is quite slow to rely on computers to process the linear interpolation of raw image data. Therefore, various special hardware devices for stretching digital images have been developed.

Most of these dedicated hardware devices can only stretch digital images to a limited area. When stretching a digital image with N scanlines, the total number of scanlines to be inserted must be an integer multiple of N-1 to allow interpolation scanlines to be inserted between every two scanlines of the original scanline With the same number, the stretched image can still maintain uniformity. Similarly, when the stretched image has N' pixel data, the same is true.

Two-dimensional scaling of general digital images can be achieved by means of a special graphics processor that performs variable expansion and reduction of the image, or by using a dedicated hardware device capable of achieving the same result. The original image is first stored in a frame memory, the original image is then stretched in a first dimension, and the final one-dimensional stretched image is stored in the frame memory. The scaled image is then scaled in a second dimension, and the final 2D scaled image is stored in the frame memory before being provided to an output device, such as a computer monitor or printer. General scaling methods are not economical because of their considerable memory requirements, especially when large scaling ratios are used. In addition, general scaling methods use a large number of processing steps and thus have rather poor efficiency, since the one-dimensional warped image must be stored in the frame memory before it can be scaled in the second dimension, and because The 2D scaled image must be stored in the frame memory before it can be provided to the output device, therefore, general scaling methods are not suitable for use in live video applications.

The first object of the present invention is to provide a device capable of instantaneously and uniformly scaling digital images in two dimensions.

A second object of the present invention is to provide a low-cost and high-efficiency telescoping device suitable for use in live video applications.

The present invention provides a device capable of processing an original digital image to obtain a digital image for uniform scaling purpose, the device includes a frame memory for storing the original digital image, the original digital image has a number (N) A continuous original scan line and each original scan line several (N') continuous original pixel data, the device also includes a device for stretching the original digital image in the vertical direction to obtain a plurality (M) of continuous purpose scans A vertical stretching unit for a line, and a horizontal stretching unit for horizontally stretching a target scan line from the vertical stretching unit to obtain a number (M') of continuous target pixel data for each scan line.

When the numerical value (M) is greater than the numerical value (N), in order to make the vertical scaling unit scale the original digital image, the vertical scaling unit includes: a line memory connected to the frame memory to store data from the The (n+1) original scanning line of the frame memory; a line buffer, connected to the line memory, to store the (n) original scanning line; a first linear interpolator, connected to the line memory and the line buffer; and a vertical scaling controller connected to the frame memory, the line buffer and the first linear interpolator. The vertical scaling controller controls the storage of the original scan line in the line memory and the line buffer, and also controls the first linear interpolator to perform the (n)th and Linear interpolation of the (n+1)th original scan line to generate a residual interpolated scan line, when (M-N) is divided by (N-1) to get the quotient (S) and when (n) is a satisfying condition (n+1)×(S)≥(s)×(N), where (s) is located between 1 and (S), the residual interpolated scanlines are inserted between the (n)th and Between (n+1) original scan lines.

In order to make the vertical scaling unit scale the original digital image when the value (M) is smaller than the value (N), the vertical scaling controller includes:

A first address generator, connected to the frame memory, controls the frame memory to output the first one of the original scanning lines for storage in the line memory, for generating a first value (U) generating means, the value being a quotient obtained by dividing the value (N) by the value (M);

a first data register;

A first adder device, connected to the first generating device and the first data register, adds the value stored in the first data register to the value (U) to obtain a sum;

a first calculation means, connected to the first adder means, the first address generator and the first data register, for comparing the sum with the value (M) and causing the first address to be generated device to control the frame memory, and output the other one of the original scanning lines to be stored in the line memory, and the other one of the original scanning lines, when the sum is less than the value (M), is generated from the frame memory The output at the previous original scan line is offset by a value (V), and when the sum is at least equal to the value (M), the output at the previous original scan line by the frame memory is offset by a value ( V+1), the value (V) is equal to the quotient obtained by dividing (N) by (M). When the sum is at least equal to the value (M), the first calculation means stores the difference between the sum and the value (M) in the first data register, and when the sum is greater than the value (M) hour, the first computing device stores the sum in the first data register.

When the numerical value (M') is greater than the numerical value (N'), in order to make the horizontal stretching unit stretch the target scan line from the vertical stretching unit, the horizontal stretching unit includes:

A dot register, connected to the first linear interpolator, to store the (n'+1)th pixel data of one of the scan lines from the first linear interpolator;

a dot buffer, connected to the dot register, to store the (n')th pixel data of the one of the scan lines;

a second linear interpolator connected to the sticker register and the point buffer;

A horizontal scaling controller is connected to the row memory, the row buffer, the point buffer and the second linear interpolator.

The horizontal scaling controller controls the storage of the pixel data in the point register and the point buffer, and also controls the second linear interpolator to perform the (n')th from the point register and the point buffer and linear interpolation of the (n'+1)th pixel data to produce a residual interpolated pixel data, when (M'-N') is divided by (N'-1) to get the quotient (S') and when When (n') is a minimum value that satisfies the condition (n'+1)×(S')≥(s')×(N'), where (s') is located between 1 and (S'), the residual Interpolated pixel data is inserted between the (n')th and (n'+1)th original scan lines.

When the value (M') is smaller than the value (N'), in order to make the horizontal stretching unit stretch the target scan line from the vertical stretching unit, the horizontal stretching unit includes:

a second address generator, connected to the row memory, to control the row memory to output the first original pixel data of one of the scan lines for generating a value (U') second generating means, the The value is a quotient obtained by dividing the value (N') by the value (M');

a second data register;

A second adder means, connected to the second generating means and the second data register, adds the value (U') stored in the second data register to obtain a sum;

a second calculation means, connected to the second adder means, the second address generator and the second data register, to compare the sum with the value (M') and make the second address The generator is used to control the line memory to output another original pixel data of the aforementioned scan line. When the sum is less than the value (M'), the other original pixel data of the scan line is output from the line memory The previous original pixel data is offset by a value (V'), and when the sum is at least equal to the value (M'), it is offset by a value from the previous original pixel data output by the line memory (V'+1), the value (V') is equal to the quotient obtained by dividing (N') by (M'). In the second data register, the second calculation means stores the difference between the sum and the value (M') when the sum is at least equal to the value (M'), and when the sum is greater than the value (M') hours, the second calculating means stores the sum in the second data register.

The output of the second linear interpolator of the horizontal scaling unit can be provided directly to an output device.

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail:

Fig. 1 is a schematic circuit block diagram of the preferred embodiment of the telescoping device of the present invention.

Fig. 2 is a schematic circuit block diagram of the bilinear adder in the above preferred embodiment.

Fig. 3 is a schematic circuit block diagram of the vertical telescoping controller in the above-mentioned preferred embodiment.

Fig. 4 is a schematic circuit block diagram of the residual distributor of the above-mentioned vertical scaling controller.

FIG. 5 is a schematic circuit block diagram of the α-series generator of the above-mentioned vertical scaling controller.

FIG. 6 is a schematic circuit block diagram of the address generator of the vertical scaling controller.

Fig. 7 is a time sequence diagram of the vertical stretching operation of the vertical stretching unit of the above preferred embodiment when N=5 and ΔN=2.

FIG. 8 is a timing diagram of the vertical stretching operation of the vertical stretching unit when N=5 and ΔN=6.

FIG. 9 is a timing diagram of the vertical compression operation of the above-mentioned vertical stretching unit when N=5 and ΔN=2.

Fig. 10 is a timing diagram of the horizontal stretching operation of the horizontal stretching unit of the preferred embodiment when N'=5 and ΔN'=2.

Fig. 11 is a timing diagram of the horizontal compression operation of the above-mentioned horizontal stretching unit when N'=5 and ΔN'=2.

As shown in FIG. 1, the preferred embodiment of the device for uniformly stretching digital image size of the present invention includes a vertical stretching unit and a horizontal stretching unit. The vertical scaling unit can stretch or compress a digital image data in the vertical direction, and includes a line memory 3, a line buffer 4, a bilinear adder (BILINEAR ADDER) 5 and a vertical scaling controller 6; The horizontal scaling unit can stretch or compress a digital image data in the horizontal direction, and includes a point register 7 , a point buffer 8 , a bilinear adder 9 and a horizontal scaling controller 10 .

During use, a digital image processed by the device of the present invention is initially stored in a frame memory (FRAME MEMORY) 2, and this digital image can come from an image decoder or from digital image data sources such as an image capture system 1. The vertical scaling controller 6 controls the frame memory 2 to provide a selected scan line of the digital image to the line memory 3, and the vertical scaling controller 6 controls the line buffer 4 to store the previous line from the line memory 3. One scanning line, the bilinear adder 5 receives the scanning line data from the row memory 3 and the row buffer 4 and performs bilinear sexual interpolation.

The output of the bilinear adder 5 is received by the dot register 7 , and the horizontal scaling controller 10 controls the dot buffer 8 to store a pixel data from before the dot register 7 . The bilinear adder 9 receives pixel data from the point register 7 and the point buffer 8 , and performs bilinear interpolation according to a pair of weighting coefficients α, 1−α from the pan controller 10 .

What Fig. 2 shows is the circuit block diagram of this bilinear adder 5, from this row buffer 4 and the scanning line data corresponding to the nth scanning line of the digital image stored in this frame memory 2 through a register 501 and a The multiplier 502 is multiplied by the coefficient 1-α, and the scan line data from the line memory 3 and corresponding to the n+1th scan line of the digital image stored in the frame memory 2 passes through a register 503 and a multiplier 504 is multiplied by the coefficient α. When the coefficient α is a fraction (that is, α is neither equal to 1 nor equal to 0), the products obtained above are added by an adder 505 to obtain an interpolated scan line. The operation of the bilinear adder 5 will be described in detail below.

The structure of the bilinear adder 9 is similar to that of the bilinear adder 5 shown in FIG. 2 . However, in the bilinear adder 9, the pixel data from the dot buffer 8 corresponding to the n'th pixel data of the scan line data from the bilinear adder 5 is multiplied by the coefficient 1-α, and the pixel data from the dot register 7 corresponding to the n′+1th pixel data of the scan line data from the bilinear adder 5 is multiplied by the coefficient α. Therefore, the point register 7 is equivalent to the line memory 3 of the vertical scaling unit, and the point buffer 8 is equivalent to the line buffer 4 of the vertical scaling unit.

As shown in Figure 3, the vertical scaling controller 6 includes a programmable register group 30, a first calculation circuit 31, a second calculation circuit 32, a third calculation circuit 33, a selector 34, a residual Distributor 35 , an alpha serial generator 36 and an address generator 37 .

The register set 30 includes a first register 301, a second register 302 and a third register 303, the first register 301 is used to store the original scan line data N of the digital image in the frame memory 2, the first register 301 The second register 302 is used to store the amount ΔN of scanning lines to be inserted or deleted, and the third register 303 is used to store an INC/DEC flag 38. The above-mentioned INC/DEC flag 38 is used to indicate the Stretching or compression of digital image data is performed. The first calculation circuit 31, the second calculation circuit 32 and the third calculation circuit 33 respectively read the contents stored in the first register 301, the second register 302 and the third register 303, and the first calculation circuit 31 outputs ΔN The quotient T obtained by dividing by N−1, and the second calculation circuit 32 outputs the quotient S obtained by dividing ΔN by N−1. Therefore, when the digital image is being stretched, the quotient T is equivalent to the minimum number of interpolated scan lines inserted between every two adjacent scan lines of the digital image, and the quotient S is equivalent to a uniformly distributed The total number of residual interpolated scanlines between the original scanlines of this digital image. The third calculation circuit 33 outputs the quotient U of dividing N by N-[Delta]N, which corresponds to the total number of deleted residual scan lines when the digital image is compressed.

The selector 34 includes a first input terminal receiving the quotient U from the third calculation circuit 33 and a second input terminal receiving the quotient S from the second calculation circuit 32, and the selector 34 includes a control input terminal, the control input terminal receives the INC/DEC flag 38 from the third register 303, and the output terminal 42 of the selector 34 is connected to the residual distributor 35, and the residual distributor 35 also receives the INC/DEC flag 38 from the first calculation circuit The quotient T of 31 includes a control input terminal receiving the INC/DEC flag 38 from the third register 303 and a control output terminal 39 connected to the alpha serial generator 36 and the address generator 37. The residual distributor 35 determines when to perform a residual interpolation step during stretching of the digital image and when to delete a residual scan line during compression of the digital image. The α serial generator 36 receives the quotient T from the first calculation circuit 31 and the INC/DEC flag 38 from the third register 30c, and generates coefficients α, 1-α and the A storage command signal of the row buffer 4 (as shown in FIG. 1 ). The address generator 37 also receives the 1VC/DEC flag 38 from the third register 303 and provides line address data to the frame memory 2 .

As shown in Figure 4, the residual distributor 35 includes a calculation circuit 40, a double-input selector 41, an intermediate data register 56, a double-input adder 43, a calculation circuit 44, a double-input selector 45 . A clock modulation circuit 46 and a selector 47 .

The calculation circuit 40 outputs the difference between N and ΔN. The selector 41 has a first input terminal receiving the output of the calculation circuit 40, a second input terminal receiving the value N from the first register 301, and a control unit receiving the INC/DEC flag 38 from the third register 303. input. The intermediate data register 56 receives the output 42 of the selector 34 (as shown in FIG. 3 ) and has an output connected to an input of the two-input adder 43 . The other input end of this adder 43 then receives the output end 42 of this selector 34, the output end of this adder 43 and the output end of this selector 41 serve as the input end of a computing circuit 44, and this computing circuit 44 is The output of the adder 43 subtracts the output of the selector 41, and when the output of the adder 43 is greater than or equal to the output of the selector 41, the calculation circuit 44 generates an enable signal at a control output terminal 39 thereof. The dual-input selector 45 includes a first input terminal receiving the adder 43, a second input terminal receiving the output difference between the adder 43 and the selector 41 from the calculation circuit 44, and a connection with the calculation circuit 44. The control input 39 of the circuit 44 is connected to a control input and an output connected to the intermediate data register 56 .

The clock modulation circuit 46 receives the original input line clock and modulates the original input line clock according to the signal of the control output terminal 39 and the quotient T from the first calculation circuit 31 . The raw input line clock can represent the scan line clock, enabling the vertical scan run to be outputted as raw image data for display on an output device such as a printer or computer monitor. When the control output terminal 39 is in a high logic state, the clock modulation circuit 46 outputs a divided by T+2 clock, and the divided by T+2 clock has a time delay of T+2 times the original input line clock, And when the control output terminal 39 is in the low logic bit state, the clock modulation circuit 46 outputs a clock divided by T+1, and the clock divided by T+1 has a time T+1 times that of the original input line clock Delay. In addition, the output terminal of the clock modulation circuit 46 and the original input line clock are connected to the input terminal of the selector 47, and the INC/DEC flag 38 from the third register 30C is used as the control of the selector 47 enter. The intermediate data register 56 includes a load terminal LD for receiving the clock signal mClock1 output from the selector 47 .

As shown in FIG. 5 , the α-series generator 36 includes a coefficient generator 363 , a selector 364 and a subtractor circuit 365 . The coefficient generator 363 is connected to the control output terminal 39 of the calculation circuit 44 and receives the original input line clock and the quotient T from the first calculation circuit 31 . When the control output terminal 39 is in a high logic bit state, the coefficient generator 363 generates successive alpha coefficients 1, 1/(T+2), 2/(T+2), ..., (T+1)/(T+2). When the control output terminal 39 is in a low logic bit state, the coefficient generator 363 generates successive alpha coefficients 1, 1/(T+1), 2/(T+1), ..., T/(T+1). The selector 364 includes a first input terminal fixed to 1, a second input terminal receiving the output of the coefficient generator 363, and a control input terminal receiving the INC/DEC flag 38, and the output coefficient α is used as the One input of the subtractor circuit 365 and the other input terminal of the subtractor circuit 365 are fixed at 1. One output terminal of the subtracter circuit 365 outputs the coefficient 1−α, and the other output terminal outputs the storage instruction signal of the row buffer 4 (as shown in FIG. 1 ). And when the coefficient 1-α. The other output end outputs the storage instruction signal of the row buffer 4 (as shown in FIG. 1 ). And when the coefficient 1−α is equal to 0 (ie α=1), the subtracter circuit 365 generates the storage instruction signal.

As shown in Figure 6, this address generator 37 comprises a calculation circuit 371, an adder 372, a selector 373, an adder 374, an address register 375, a latch circuit 376, a clock modulation circuit 377 and A selector 378.

The calculation circuit 371 outputs the quotient V obtained by dividing N by N-ΔN, which is equivalent to the difference between the two selected scanning lines of the digital image in the frame memory 2 when the digital image data is compressed. , the quotient V and the control output 39 are used as the input of the adder 372, and the output of the adder 372 is used as an input of the selector 373, and the other input of the selector 373 is used is fixed at 1, and the INC/DEC flag 38 is used as a control input terminal of the selector 373 . A difference generated by the selector 373 is delivered to the adder 374 . The output end of this adder 374 is connected to this address register 375, and the output end of this address register 375 is connected to this adder 374 again, and this address register 375 has an initial input end Start, in order to set this frame memory 2 The address of the first scan line, and the address register 375 further has a load terminal LD for controlling the update of the next address.

The latch circuit 376 samples and holds the control output terminal 39 according to the original input line clock. The quotient T of circuit 31 modulates the original input line clock. When the output of the latch circuit 376 is in a high logic state, the clock modulation circuit 377 outputs a time delay divided by T+2 times. When the output of the latch circuit 376 is in a low logic state, the clock modulation Circuit 377 outputs a divide-by-T+1 clock with a time delay of T+1 times the original input line clock. The selector 378 receives the original input line clock and the output of the clock modulating circuit 377, and selects a clock output mClock2 through the INC/DEC flag 38, and the clock output mClock2 is selected by the load terminal LD of the address register 375 take over.

The structure of the horizontal telescopic controller 10 is similar to that of the vertical telescopic controller 6 shown in FIGS. 3-6 . Insignificant differences between the two controllers 6, 10 exist. For example, in the horizontal scaling controller 10, the first register of the programmable register set is used to store the N' pixel data of the digital image of each original scanning line in the frame memory 2, and the first register The second register is used to store ΔN' pixel data to be interpolated or deleted for each scan line. The third register stores an INC/DEC flag indicating whether stretching or compression of digital images in a horizontal direction is to be performed. The first calculation circuit generates a quotient T' corresponding to the minimum number of interpolated pixel data to be inserted between every two pixel data of the scan line data from the bilinear adder 5. When the digital image is stretched, the second computing circuit generates a quotient S corresponding to the total number of residual interpolated pixel data to be evenly distributed between the pixel data of the scan line data from the bilinear adder 5 '. The third calculation circuit generates a quotient U' corresponding to the total number of residual pixel data to be deleted from the scan line data from the bilinear adder 5 when the digital image is compressed. Instead of a store command signal, the alpha serial generator of the pan controller 10 generates a latch command signal to the dot buffer 8 . The clock input to the address generator, the alpha-serial generator and the residual distributor is a raw pixel clock. The raw pixel clock may be a display dot clock such that the panning operation can be output on the raw image data for display on the output device. The address output of the address register of the horizontal scaling controller 10 is a point address used to control the row memory 3 and the row buffer 4 . Thus, during stretching in the horizontal direction, all pixel data between the nth and n+1th original scan lines and the interpolated scan line, if any, simply passes through the bilinear adder. When compressing in the vertical and horizontal directions, only one selected pixel data of one selected original scanning line passes through the bilinear adder 5 .

Therefore, this embodiment can be used to simultaneously perform expansion or compression in the vertical direction and expansion or compression in the horizontal direction. Run as described below:

A． To facilitate the description of the vertical stretch operation of the preferred embodiment, a raw digital image with five raw scan lines and five pixel data per scan line is stretched to obtain a seven-entry scan line with five pixel data per scan line. An example of a digital image for the purpose of pixel data.

As shown in Figure 3, the programmable register set 30 of the vertical scaling controller 6 is initially set to store the number "5" in the first register 301, store the number "2" in the second register 302 and A logic "1" is stored in the third register 303; the number "5" is equivalent to the original scanning line number N of the original image data in the frame memory 2, and the number "2" is equivalent to the inserted scanning line A total of ΔN, the logic 1 in the third register 303 indicates that stretching of the digital image data in the vertical direction is to be performed. Then, the programmable planning register group of this horizontal scaling controller 10 is programmed, to indicate that there are five pixel data in each original scan line, no pixel data to be interpolated in each original scan line, and the original number Stretching of the image in the horizontal direction is to be performed. The first calculation circuit 31 outputs a quotient T obtained by dividing ΔN by N−1, and since ΔN is smaller than N−1, the quotient T is equal to 0. The second calculation circuit 32 outputs a quotient S obtained by dividing ΔN by N−1, which is equal to 2 in this example. The third computing circuit 33 is irrelevant because during stretching operation, the selector 34 provides the output of the second computing circuit 32 to the residual distributor 35, the first, second and the output of the third calculation circuit is 0 because no horizontal stretching or compression operation is to be performed.

As shown in Figures 1, 3, and 7, the address register 375 of the address generator 37 initially sets the line address of the first original scanning line stored in the original scanning line of the frame memory 2, and controls the frame memory 2 to provide The first original scan line of this original scan line is sent to this line memory 3, simultaneously, this quotient S is stored in this intermediate data register 56, then this adder 43 compares this quotient S and the content of this intermediate data register 56 again Add, because the output of the adder 43 is 4 and less than N (N equals to 5), so the control output terminal 39 of the calculation circuit 44 is in a low logic bit state, and the selector 45 provides the output of the adder 43 to the The intermediate data register 56 and the clock input mClock1 providing the intermediate data register 56 is a clock divided by T+1, which is exactly the same as the original input line clock because the quotient T is equal to 0.

Because the control output 39 is at a low logic state and because the quotient T is equal to 0, the coefficient generator 363 provides the digital "1" to the selector 364 because the INC/DEC flag 38 is at logic "1", The selector 364 selects the output of the coefficient generator 363 as the weighting coefficient α, because the coefficient α is equal to 1, so the coefficient 1-α is equal to 0, and generates the storage command signal to facilitate the control of the row buffer 4 to store The first original scan line of the original scan line from the line memory 3, the output of the bilinear adder 5 at this stage is the first original scan line of the original scan line.

The selector 373 provides a difference equal to 1 to the adder 374. Therefore, when the next line clock mClock2 arrives, the adder 374 will increase the output of the address register 375 by one unit, thereby controlling the frame memory 2 , providing the second scan line of the original scan line to the line memory 3 .

When the next line clock mClock1 arrives, the intermediate data register 56 stores the previous output (equal to 4) of the adder 43. At this time, the output of the adder 43 (equal to 6) is greater than N (equal to 5), making the calculation The control output terminal 39 of the circuit 44 is in a high logic state, and the selector 45 provides the difference between the output of the adder 43 and the output of the selector 41 to the intermediate data register, and the clock input mClock1 is equal to dividing by T+2 clock with twice the delay time of the original input line clock.

The control output 39 is at a high logic state, and the coefficient generator 363 generates two consecutive outputs 1 and 1/2 during a clock mClock (ie, two consecutive original input line clocks). During the clock period of the first original input line, because the coefficient α is equal to 1, the bilinear adder 5 outputs the second original scan line of the original scan line, and stores the second original scan line in the row In the buffer 4, during the second original input line clock, the content of the address register 375 is increased by one unit when the next clock is input to mClock2, at this moment, the output of the coefficient generator 363 is equal to 1/2, and the coefficient α is equal to 1/2, the coefficient 1-α is equal to 1/2, so no recommendation signal is generated. Therefore, the second original scan line of the original scan line remains in the row buffer 4, and the output of the bilinear adder 5 at this stage is the second original scan line and the third original scan line of the original scan line. Bilinear interpolation of scanlines.

The content of the intermediate data register 56 is updated to 1 when the next clock input mClock1 arrives, that is, the difference between the adder 43 and the number N. The output of the adder 43 is less than N, so that the control output 39 is in a low logic state, the selector 45 provides the output of the adder 43 to the intermediate data register 56, and the clock input mClock1 of the intermediate data register 56 is divided by the T+1 clock, and the coefficient α from the α-serial generator 36 is equal to 1. The output of the bilinear adder 5 is the third original scan line of the original scan lines, and because the coefficient α is equal to 1, the third original scan line of the original scan line is stored in the line buffer 4 .

The subsequent operation of the vertical scaling unit is similar to the above until the fifth original scan line is output by the bilinear adder 5 .

FIG. 7 is an operation timing diagram of the above preferred embodiment, where N=5 and ΔN=2.

As mentioned above, the vertical scaling controller 6 controls the bilinear adder 5 to perform bilinear interpolation of the nth and n+1th scanning lines of the original scanning line, wherein the nth scanning line line is stored in the row buffer 4, and the n+1th scanning line is stored in the row memory 3, so that when ΔN is divided by N-1 to obtain a quotient S and when (n+1)× Under the condition of (S)≥(s)×(N), when n is the minimum, create a residual interpolation scan line inserted between the nth and n+1 original scan lines of the original scan line, where s ranges from 1 to S.

As shown in FIG. 1, since no horizontal scaling operation is to be performed, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to sequentially provide the pixel data stored therein to the bilinear addition device 5. The raw plus interpolated pixel data from the bilinear adder 5 is received by the point register 7 which in turn provides the raw and interpolated pixel data to the bilinear adder 9 . At this time, the coefficient α is always equal to 1, and the output of the point buffer 8 is ignored by the bilinear adder 9 . The output of the bilinear adder 9 is equal to the output of the bilinear adder 5 and can be directly provided to the output device (not shown).

In this example, the quotient T obtained by dividing ΔN by N-1 is 0. If the quotient T is not equal to 0, that is, 1N is greater than or equal to N-1, the vertical scaling controller 6 also controls the bilinear adder 5 to execute the nth and n+1th original scanning lines of the original scanning line. Bilinear interpolation of scan lines to create T additional consecutive interpolated scan lines inserted between the nth and n+1th original scan lines. Figure 8 is a timing diagram of the sampling vertical stretch operation performed by the preferred embodiment when N=5 and ΔN=6. In this example, the quotient is equal to 1, and the quotient is equal to 2. It is obvious that, except for the two residual interpolated scan lines, there is a Additional interpolated scanlines.

B． In the following example, a raw digital image with five original scan lines and five pixel data per scan line is compressed to obtain a three-entry scan line with five pixel data per scan line digital image.

As shown in Figure 3, the programmed register set 30 is set to store the value "5" in the first register 301, store the value "2" in the second register 302 and store the value "2" in the third register 303. A logic "0". The value “5” corresponds to the number N of original scan lines of the original image data in the frame memory 2 , the value “2” corresponds to the total number of deleted scan lines ΔN, the logic in the third register 303 . Then instructs the digital image data to perform a compression operation. The programmable programming register set of the horizontal scaling controller 10 is then programmed to indicate that there are five pixel data in each original scan line, that no pixel data is to be interpolated in each original scan line, and that the original digital image is Horizontal stretching is to be performed.

During compression operation, the outputs of the first and second computing circuits 31, 32 are uncorrelated, and the third computing circuit 33 outputs the quotient U obtained by dividing N by N-ΔN, where N-ΔN is retained The number of the original scan lines, in this embodiment, the quotient U is equal to 2. The selector 34 provides the output of the third calculation circuit 33 to the residual distributor 35 .

As shown in Figures 1, 3, 6, and 9, the address register 375 of the address generator 37 first sets the line address of the first original scanning line stored in the frame memory 2, and in a Control the frame memory 2 to provide the first original scan line of the original scan line to the line memory 3 during the start line clock period, and at the same time, the quotient U is stored in the intermediate data register 56, and then the adder 43 will The quotient is added to the content of the intermediate data register 56, and the calculation circuit 44 subtracts the value N-ΔN from the selector 41 from the output of the adder 43, because the output of the adder 43' is at this time is equal to 4 and greater than N-[Delta]N (equal to 3), so the control output 39 of the calculation circuit 44 is in a high logic state. The selector 45 provides the difference between the output of the adder 43 and the output of the selector 41 to the intermediate data register 56 , and the raw line clock is supplied to the intermediate data register 56 via the selector 47 .

As shown in Figures 3 and 5, because a logic "0" is stored in the third register 303, the selector 364 maintains the coefficient α as 1, and the coefficient 1-α is therefore equal to 0, so the store command signal is always generated so that the line buffer 4 can continuously store an original scan line from the line memory 3 , and the output of the bilinear adder 5 is always the output of the line memory 3 .

As shown in Figure 6, the calculation circuit 371 outputs the quotient V obtained by dividing N by N-ΔN. In this example, the quotient V is equal to 1, and the adder 372 generates the quotient V and the control output terminal The sum number of the instant logic state of 39, the logic state at this moment is high logic state, and this selector 373 selects the output (equaling 2) of this adder 372, and provides identical output to this adder 374, therefore, this address The output of register 375 is incremented by two units when the next clock input mClock2 arrives, thereby controlling the frame memory 2 to provide the third original scan line of the original scan lines to the row memory 3 .

As shown in Figure 4, until the arrival of the next line clock, the intermediate data register 56 stores the previous difference "1" calculated by the calculation circuit 44, at this time, the output of the adder 43 (equal to 3) is equal to the The output of the selector 41 , the control output 39 of the calculation circuit 44 is at a high logic state, and the selector 45 provides the difference between the output of the adder 43 and the output of the selector 41 to the intermediate data register 56 .

As shown in Figure 6, the adder 372 again produces the sum of the quotient V and the immediate logic state of the control output 39; the output of the adder 372 (equal to 2) is provided via the selector 373 to the adder 374, therefore, the output of the address register 375 will be increased by two units when the next clock input mClock2 arrives, thereby controlling the frame memory 2 to provide the fifth original scan line of the original scan line to The line memory 3. Figure 9 is a timing diagram for the vertical compression operation of this preferred embodiment, ie N=5 and ΔN=2. For this example, the operation of the horizontal scaling unit is the same as described above, so it will not be repeated.

As mentioned above, the address generator 37 of the vertical scaling controller 6 controls the frame memory 2 to output only the selected scan lines in the original scan lines. And in this frame memory 2, this original scanning line that is not output is discarded in fact, and, when the output of the adder 43 of this residue distributor 35 is less than this difference number N-ΔN, by this frame memory 2 The difference between the output original scan line and the original scan line output by the frame memory 2 is V, when the output of the adder 43 is at least equal to the difference N-ΔN, the original output by the frame memory 2 The difference between the scan line and the original scan line output by the frame memory 2 is V+1.

C． In the horizontal stretching operation description of the following embodiment, the original digital image with five original scan lines and five pixel data per scan line is stretched, and a scan line with five entries and seven pixel data per scan line can be obtained .

The programmable register set 30 of the vertical stretch controller 6 is initially programmed to indicate that there are five original scan lines in the frame memory 2 and that stretching of the original digital image in the vertical direction is performed. The programmable register set of the pan controller 10 is then programmed by storing a value of "5" in the first register, a value of "2" in the second register, and a logic "1" in the third register. The value "5" corresponds to the number N' of pixel data in each original scanning line in the frame memory 2. The value "2" corresponds to the total amount ΔN' of pixel data to be interpolated per scanning line. A logic "1" in the third register indicates that horizontal stretching of the raw digital data is to be performed.

The output of the first, second and third computing circuits 31, 32, 33 of the vertical stretching controller 6 is 0, since no vertical stretching or compression operation is to be performed. The first calculation circuit of the horizontal scaling controller 10 outputs a quotient T' obtained by dividing ΔN' by N'-1. The second computing circuit of the horizontal scaling controller 10 outputs a quotient S' obtained by dividing ΔN' by N'-1. In this embodiment, the quotient S' is equal to 2. The output of the third computing circuit of the panning controller 10 is irrelevant because the output of the second computing circuit is provided to the residual distributor during panning operation.

Since there is no vertical scaling operation to be performed, the vertical scaling controller 6 controls the frame memory 2 to sequentially provide the original scan lines to the row memory 3 . The horizontal scaling controller 10 controls the row memory 3 and the row buffer 4 to sequentially provide the pixel data stored therein to the bilinear adder 5 . At this time, the coefficient α from the vertical scaling controller 6 is always equal to 1, and the output of the line buffer 4 is ignored by the bilinear adder 5 . The output of the bilinear adder 5 is equal to the output of the line memory 3 .

As mentioned above, the stretching operation of the horizontal scaling unit is substantially similar to that of the vertical scaling unit, but unlike the vertical scaling controller 6, the horizontal scaling controller 10 controls the bilinear adder 9 to perform the The bilinear interpolation of the n'th raw pixel data stored in the dot buffer 8 and the n'+1 raw pixel data stored in the dot register 7 can generate a value when ΔN' is divided by Get a remainder S' with N'-1, when n' is the minimum value that satisfies the condition (n'+1)×(s')≥(s')×(N'), where (s') ranges from 1 to (S'), are residual interpolated pixel data inserted between the n'th and n'+1th original pixel data. Therefore, for N', ΔN' and S' equal to 5, 2 and 2 respectively, the residual interpolated pixel data is to be interpolated between the second and third raw pixel data of a scan line and between the fourth and third Between five raw pixel data.

The horizontal scaling controller 10 initially sets the point address of the first pixel data of the scan line data stored in the line memory 3 and controls the line memory 3 to provide the first pixel data to the bilinear addition device 5, which can be received by the dot register 7 during the initial pixel clock. The coefficient α from the pan controller 10 is equal to 1, and the latch command signal can control the dot buffer 8 to store the first raw pixel data from the dot register 7 therein. The output of the bilinear adder 9 at this stage is the first raw pixel data, and can be directly provided to the output device (not shown).

At this time, the horizontal scaling controller 10 controls the line memory 3 to provide the second original pixel data to the bilinear adder 5 for the dot register 7 to receive. The horizontal scaling controller 10 continuously generates two alpha coefficients 1 and 1/2 within two consecutive original pixel clocks. In the first raw pixel clock, the bilinear adder 9 outputs the second raw pixel data, and, at the same time, the latter is stored in the dot buffer 8, because the coefficient α is equal to 1. During the second raw pixel clock, the line memory 3 provides the third raw pixel data to the bilinear adder 5 for the dot register 7 to receive. The coefficient α is now equal to 1/2, and the second raw pixel data is still in the dot buffer 8 . At this stage, the output of the bilinear adder 9 is the bilinear interpolation of the second and third raw pixel data.

During the next raw pixel clock, the coefficient α from the horizontal scaling controller 10 returns to 1, and the output of the bilinear adder 9 is simultaneously stored in the third raw pixel in the dot buffer 8 data.

Subsequent operations of the horizontal scaling unit are similar to the foregoing, until the fifth original pixel data of a scan line is output by the bilinear adder 9 .

Fig. 10 is a timing diagram of the horizontal stretching operation of the preferred embodiment, that is, N'=5 and ΔN'=2.

In this example, the quotient T' obtained by dividing ΔN' by N'-1 is zero. If the quotient T' is not 0, then ΔN' is greater than or equal to N'-1, the horizontal scaler 10 controls the bilinear adder 9 to perform the n'th and n'th+ The bilinear interpolation of 1 raw pixel data can generate an additional amount T' of consecutively interpolated pixel data interpolated between the n'th and n'+1th raw pixel data.

D． An original digital image with five original scan lines and five pixel data per scan line is compressed to obtain a destination digital image with five items of scan lines and three pixel data per scan line.

The programmable register set 30 of the vertical scaling controller 6 is initially programmed to indicate that there are five original scan lines in the frame memory 2, that no scan lines are to be interpolated, and that the vertical stretch of the original digital image is to be executed. The programmable register set of the pan controller 10 is programmed by storing a value of "5" in the first register, a value of "2" in the second register, and a logic "0" in the third register. The value "5" is the number N' of pixel data corresponding to each original scanning line of the digital image in the frame memory 2. The value "2" corresponds to the total amount ΔN' of pixel data to be deleted per scanning line. A logic "0" in the third register may indicate that compression of the raw digital data in the horizontal direction is to be performed.

The output of the first, second and third calculation circuits 31, 32, 33 of the vertical scaling controller 6 is 0, because no vertical stretching or compression operation is to be performed, therefore, the vertical scaling controller 6 controls the frame memory 2. Sequentially provide the original scan lines to the line memory 3. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to provide the selected pixel data stored therein to the bilinear adder 5 . In this embodiment, the coefficient α from the vertical scaling controller 6 is always equal to 1, and the output of the line buffer 4 is ignored by the bilinear adder 5 . The output of the bilinear adder 5 is equal to the output of the line memory 3 .

The compression operation of the horizontal scaling unit is substantially similar to the compression operation of the vertical scaling unit, however, in the horizontal scaling unit, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to only output selected The original pixel data of the original pixel data to be output by the line memory 3 and the line buffer 4, when the output of the adder of the residual distributor of the horizontal scaling controller 10 is less than the difference (N'-ΔN'), The output from the line memory 3 and the line buffer 4 is only offset by a value V' in the previous original pixel data, while in other states, the output from the line memory 3 and the line buffer 4 is only in the The previous original pixel data is offset by a value V'+1, and the value V' is the quotient obtained by dividing N' by N'-ΔN'.

The outputs of the first and second computing circuits of the panning controller 10 are irrelevant during the panning operation. The third calculation circuit outputs the quotient U' obtained by dividing N' by N'-ΔN', and N'-ΔN' is the number of original pixel data to be kept for each scanning line. In this embodiment, the quotient U ' is equal to 2 and is the residual distributor provided to the pan controller 10 .

The horizontal scaling controller 10 initially sets the dot address of the first pixel data of a scan line data stored in the line memory 3, and controls the line memory 3 to provide the first pixel data during the initial pixel clock period. Pixel data to the bilinear adder 5, since a logic "0" is stored in the third register of the pan controller 10, the coefficient α from the pan controller 10 is kept at 1, therefore, The dot buffer 8 is used to continuously store the pixel data from the dot register 7 , and the output of the bilinear adder 9 is always the output of the dot register 7 .

At this time, the output of the adder of the residual distributor of the horizontal scaling controller 10 is larger than the difference (N'-ΔN'), thereby resulting in an offset value (V'+1) or 2 results. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to provide the third pixel data of the scan line data stored therein to the bilinear adder 5 for the dot register 7 to receive.

On arrival of the next pixel clock, the output of the adder of the residual distributor of the horizontal scale controller 10 is equal to the difference (N'-ΔN'), thereby resulting in an offset value (V'+1) or a result of 2 . The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to provide the fifth pixel data of the scan line data stored therein to the bilinear adder 5 for the dot register 7 to receive .

Fig. 11 is a timing chart of the horizontal compression operation of this embodiment, that is, N'=5 and ΔN'=2.

To sum up, the device of the present invention is a dedicated hardware device that allows real-time two-dimensional expansion and contraction of the digital image size. Because it requires less memory and uses fewer processing steps, it is quite cheap and has a high As a result of efficiency, the output of the vertical scaling unit does not need to be stored under an intermediate frame buffer and is provided directly to the horizontal scaling unit, and because the output of the horizontal scaling unit does not need to be stored under an output frame buffer, it is Provided directly to an output device, so the present invention is very suitable for live video applications.

Claims (5)

1. A device for uniformly stretching the size of a digital image, the device comprising a frame memory (2) for storing an original digital image therein, the original digital image having a plurality (N) of continuous original scan lines and each original scan line Line multiple (N') continuous original pixel data, the device also includes a vertical scaling unit for stretching the original digital image in the vertical direction to obtain multiple (M) continuous scanning lines, and a horizontal stretching unit for The direction stretches the scan line from the vertical stretch unit to obtain a horizontal stretch unit with more (M') continuous pixel data per scan line. The value (M) is greater than the value (N), and the value (M') Greater than this value (N'), characterized by: The vertical telescoping unit includes: A line memory (3), connected to the frame memory (2), stores the (n+1) original scan lines from the frame memory (2) in it; A line buffer (4), connected to the line memory (3), stores the (n)th original scan line therein; a first linear interpolator (5), connected to the row memory (3) and the row buffer (4); a vertical scaling controller (6), connected to the frame memory (2), the line buffer (4) and the first linear interpolator (5); The vertical scaling controller (6) controls the storage of the original scan line in the row memory (3) and the row buffer (4), and the vertical scaling controller also controls the first linear interpolator to perform Linear interpolation of the (n) and (n+1) original scan lines of the line memory (3) and the line buffer (4) to produce a residual interpolated scan line, when (M-N) is divided by ( N-1) to get the quotient (S) and when (n) is a minimum value that satisfies the condition (n+1)×(S)≥(s)×(N), where (s) is from 1 to ( S), the residual interpolation scan line is inserted between the (n) and (n+1) original scan lines; The horizontal flex unit includes: A dot register (7), connected to the first linear interpolator (5) to store the (n'+1)th pixel data of one of the scan lines from the first linear interpolator (5) in it; A dot buffer (8) is connected to the dot register (7) to store (n') pixel data in the scan line; A second linear interpolator (9), connected to the point register (7) and the point buffer (8); A horizontal scaling controller (10), connected to the line memory (3), the line buffer (4), the point buffer (8) and the second linear interpolator (9); The horizontal scaling controller controls the storage of the pixel data in the point register (7) and the point buffer (8), and the horizontal scaling controller (10) also controls the second linear interpolator (9) to perform Linear interpolation of the (n')th and (n'+1)th pixel data from the point register (7) and the point buffer (8) to produce a residual interpolated pixel data, when (M' -N') divided by (N'-1) to get the quotient (S') and when (n') is a satisfying condition (n'+1)×(S')≥(s')×(N') , where (s') is from 1 to (S'), the residual interpolated pixel data is inserted between the (n')th and (n'+1)th original scan lines; The output of the second linear interpolator (9) can be provided directly to an output device. 2. The device for uniformly stretching digital image size as claimed in claim 1, characterized in that: The vertical scaling controller (6) can further control the first linear interpolator (5) to perform linear interpolation of the (n)th and (n+1)th original scan lines, generating an additional number (T) The continuous interpolation scan lines, when (M-N) is greater than (N-1), the continuous interpolation scan lines are inserted between the (n) and (n+1) original scan lines, The value (T) is equal to the quotient obtained by dividing (M-N) by (N-1). 3. The device for uniformly stretching digital image size as claimed in claim 2, characterized in that: The first linear interpolator (5) is a bilinear adder. 4. The device for uniformly stretching digital image size as claimed in claim 1, characterized in that: The horizontal scaling controller (10) can further control the second linear interpolator (9) to perform the (n')th and Linear interpolation of (n'+1) pixel data to generate an additional number (T') of continuous interpolated pixel data, when (M'-N') is greater than (N'-1), the Continuous interpolation pixel data is inserted between the (n')th and (n'+1)th pixel data, the value (T') is divided by (M'-N') by (N'- 1) The resulting quotients are equal. 5. The device for uniformly stretching digital image size as claimed in claim 4, characterized in that: The second linear interpolator (9) is a bilinear adder.

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