CN106128353B - A kind of line-scanning drive circuit and its driving method that TFT is integrated - Google Patents

Abstract

The invention discloses a TFT-integrated row scanning driving circuit and a driving method thereof. The row scanning driving circuit includes at least one row scanning driving circuit unit, and each row scanning driving circuit unit circuit includes six TFTs and a capacitor. The line scan drive circuit is controlled by two clock signals, and the initialization module uses the first pulse signal CK1 to cooperate with the bootstrap node Q to control, which simplifies the line scan drive circuit and reduces the output noise voltage caused by clock feedthrough. The charge sharing structure is adopted in the high-level maintenance module, which can realize multi-channel pulse signal control, and use pulse signals with different duty ratios as control signals to reduce circuit power consumption.

Description

A TFT integrated line scan driving circuit and its driving method

technical field

The invention relates to the field of electronic circuits, in particular to a TFT integrated line scan driving circuit and a driving method thereof.

Background technique

At present, amorphous silicon TFT (a-Si TFT) and polysilicon TFT (Poly-Si TFT) are the most important mass production technologies in the flat panel display field. Although a-Si TFT has the advantages of large area uniformity and low process cost, it is suitable for applications with lower resolution and larger display area. However, due to the low carrier mobility and poor electrical stability, a-Si TFTs are not suitable for integrated circuit design. On the other hand, polysilicon TFT has high carrier mobility and good electrical stability, which is not only widely used in high-resolution high-quality mobile phone displays, but also suitable for use on glass substrates. integrated circuits. When the polysilicon TFT row driver circuit and the pixel array are integrated on the same substrate, it can not only reduce the peripheral driver IC and its connecting lines, make the frame of the TFT display panel narrower, but also simplify the display module process and improve the yield.

In the traditional LTPS TFT line scan drive circuit design, more clock signals need to be used to control and drive. However, due to the excessive number of clock signals, the performance of the line scan driving circuit of the LTPS TFT is not good. This is mainly because: 1) The multi-channel and multi-phase clock signals require complex control timing, which puts forward more difficult requirements for timing control ICs and level shift ICs, which is easy to bring about a substantial increase in the price of driver ICs; 2 ) In the layout design of the line scan drive circuit, in order to ensure a small on-resistance of the clock trace and avoid affecting the function of the scan circuit due to too large RC delay, the width of the clock trace is generally counted as 100um. Therefore, when the number of clock signals is too large, the area occupied by the line scanning circuit is too large, which is not conducive to the narrow frame design of the display panel. Therefore, how to simplify the complexity of the integrated line scan driving circuit and achieve better circuit performance with fewer signals has always been an urgent problem to be solved in the field of flat panel display.

SUMMARY OF THE INVENTION

Aiming at the problems in the prior art that the row scan driving circuit needs too much timing control and the structure is complex, the present invention provides a TFT integrated row scan driving circuit with a simple structure and a driving method thereof.

A TFT-integrated line scan drive circuit, comprising a line scan drive circuit unit;

The row scan driving circuit unit includes an initialization module 10 , a driving module 30 , an input module 20 , a high level maintaining module 40 and a charge sharing module 50 ;

The initialization module 10 is connected to the first pulse signal terminal and the bootstrap node Q, and transmits the signal on the ground terminal GND to the output terminal of the line scan drive circuit unit to initialize the line scan drive circuit;

The driving module 30 is connected to the first pulse signal terminal, and transmits the effective level of the first pulse signal to the output terminal of the line scan driving circuit unit;

The input module 20 and the drive module are coupled to the bootstrap node Q, and control the switching state of the switch in the input module in response to the level of the start pulse;

The high-level maintaining module 40 is used for maintaining the line-scanning signal output terminal of the driving module at a high level after the line-scanning driving circuit unit outputs the line-scanning signal;

The charge sharing module 50 is coupled between the bootstrap node Q and the output terminal of the row scan driver circuit unit, and is used for adaptively adjusting the potential of the bootstrap node Q in response to the state of the output terminal of the row scan driver circuit unit;

The line scan drive circuit initialization module 10 is connected to the input module 20, the first signal IN is transmitted to the drive module 30 through the input module (10), and the drive module 30 responds to the first signal IN and transmits the first pulse signal to the line scan circuit output terminal; the high-level maintenance module 40 is connected to the charge sharing module 50, and respectively transmits the signal on the ground terminal GND to the output terminal of the line scan driving circuit unit and transmits the output terminal signal to the bootstrap node Q; the charge sharing One end of the module 50 is connected to the bootstrap node Q, and the other end is connected to the output end of the line scan driving circuit unit;

The TFT is a low temperature polysilicon TFT.

The arrival time of the valid level of the first signal IN is earlier than the arrival time of the valid level of the first pulse signal CK1, and the valid levels of the first signal IN and the first pulse signal CK1 do not overlap.

The initialization module 10 includes a fourth transistor T4 and a sixth transistor T6;

After the control electrode of the fourth transistor T4 is coupled to the first electrode, it is connected to the first pulse signal terminal CK1; the second electrode of the fourth transistor T4 is coupled to the first electrode of the sixth transistor T6 to form the first node P;

The second electrode of the sixth transistor T6 is coupled to the ground terminal GND; the control electrode of the sixth transistor T6 is coupled to the bootstrap node Q.

The driving module 30 includes a first transistor T1 and a first capacitor C1;

The control electrode of the first transistor T1 is coupled to the bootstrap node Q; the first electrode of the first transistor T1 is connected to the first pulse signal terminal CK1; the second electrode of the first transistor T1 is coupled to the output node F;

Both ends of the first capacitor C1 are coupled between the control electrode and the second electrode of the first transistor T1.

The input module 20 includes a third transistor T3;

The second electrode of the third transistor T3 is coupled to the bootstrap node Q; the control electrode of the third transistor T3 is coupled to the first electrode for inputting the first signal N.

The high-level maintaining module 40 includes a fifth transistor T5;

The control electrode of the fifth transistor T5 is coupled to the second electrode of the fourth transistor T4; the first electrode of the fifth transistor T5 is coupled to the output node F; the second electrode of the fifth transistor T5 is coupled to the ground terminal GND.

The charge sharing module 50 includes a second transistor T2;

The control electrode of the second transistor T2 is coupled to the first pulse signal terminal; the first electrode of the second transistor T2 is coupled to the bootstrap node Q; the second electrode of the second transistor T2 is coupled to the output node F for the row scan driving circuit unit output.

The initialization module (10) includes a fourth transistor T4 and a sixth transistor T6; the charge sharing module (50) includes a second transistor T2;

The control electrode of the second transistor T2, the control electrode and the first electrode of the fourth transistor T4 are all connected to the second pulse signal terminal;

The second pole of the fourth transistor T4 is coupled to the first pole of the sixth transistor T6 to form a first node P;

The second electrode of the sixth transistor T6 is coupled to the ground terminal GND; the control electrode of the sixth transistor T6 is coupled to the bootstrap node Q.

including at least two cascaded row scan drive circuit units;

The signal output terminal of the front-stage row scanning driving circuit unit is connected to the first signal terminal IN of the rear-stage row scanning driving circuit unit.

The initialization module (10) includes a second capacitor C2, a fourth transistor T4 and a sixth transistor T6;

Both ends of the second capacitor C2 are connected between the control electrode of the sixth transistor and the bootstrap node Q, and the control electrode of the fourth transistor T4 is connected to one end of the second capacitor C2;

The first pole of the fourth transistor T4 is coupled to the first pulse CK1, and the second pole of the fourth transistor T4 is coupled to the first pole of the sixth transistor T6 to form a first node P;

The second pole of the sixth transistor T6 is coupled to the ground terminal GND.

The first pole of all transistors is the source or drain, the second pole is the drain or source, and the control pole is the gate, that is, when the first pole is the source, the second pole is the drain; when the first pole is the drain, the second pole extremely source;

A method for driving a TFT-integrated line scan driving circuit, using the above-mentioned TFT-integrated line scan driving circuit, inputting a first signal from an input module, inputting a pulse signal from a driving module, and inputting a GND signal at a ground terminal GND of an initialization module;

When the row scan driving circuit is cascaded with multi-level row scan driver circuit units, the first pulse signal of the odd-numbered row scan driver circuit is provided by the first clock signal CK1, and the first pulse signal of the even-numbered row scan driver circuit is provided by the second clock signal CK2 provides;

When there is a second pulse signal terminal in the row scan drive circuit unit, the second pulse signal of the odd-numbered row scan drive circuit is provided by the second clock signal CK2, and the second pulse signal of the even-numbered row scan drive circuit is provided by the first clock CK1;

Wherein, the timings of the second clock signal CK2 and the first clock signal CK1 are opposite.

When there is a second pulse signal terminal in the line scan drive circuit unit, and the entire line scan drive unit adopts multiple pulse control signals, the first pulse signal of the first stage is CK1, the second pulse signal is CK2, and the first pulse signal of the second stage is CK2. One pulse signal is CK2, the second pulse signal is CK3, the first pulse signal of the third stage is CK3, the second pulse signal is CK4, and so on, and the cycle is performed according to the number of pulse channels.

beneficial effect

The present invention provides a TFT-integrated row scanning driving circuit and a driving method thereof. The row scanning driving circuit includes at least one row scanning driving circuit unit, and each row scanning driving circuit unit circuit includes 6 TFTs and 1 capacitor. Compared with the traditional line scan drive circuit which is composed of multiple TFTs and capacitors, this design simplifies the complexity of the line scan drive circuit. The circuit of the invention is controlled by 2 channels of clock signals. In the design of the initialization module, the first pulse signal CK1 is used to cooperate with the bootstrap node Q to control, and no special control signal is set, which solves the problem of cumbersome control sequence of the traditional line scan driving circuit, reduces the circuit output noise due to clock signal coupling. At the same time, a high-level maintenance module is specially designed, in which a charge sharing structure is adopted to solve the influence of the control clock feedthrough effect on the gate and source voltages of the driving TFT, thereby maintaining the line scan signal output by the circuit. high-level voltage. In addition, the state switching signal of the control terminal of the high-level maintenance module and the control signal of the output module are multiplexed, which further simplifies the circuit structure and facilitates the realization of the narrow-frame active TFT panel. The driving method can realize multi-channel pulse signal control, and using pulse signals with different duty ratios as control signals can reduce the dynamic power consumption of the circuit.

Description of drawings

Figure 1 is a structural diagram of a low temperature polysilicon TFT;

FIG. 2 is a structural diagram of a first row scan driving circuit unit disclosed in Embodiment 1 of the present application;

FIG. 3 is a structural diagram of a second row scan driving circuit unit disclosed in Embodiment 1 of the present application;

FIG. 4 is a structural diagram of a third row scan driving circuit unit disclosed in Embodiment 1 of the present application;

FIG. 5 is a working timing diagram of the first row scan driving circuit unit disclosed in Embodiment 1 of the present application;

Fig. 6 is the simulation working timing chart of the row scanning drive circuit unit corresponding to Fig. 5;

Fig. 7 is a kind of simulation working timing chart of the row scanning drive circuit unit corresponding to Fig. 4;

FIG. 8 is a structural block diagram of a row scan driving circuit unit disclosed in Embodiment 2 of the present application;

FIG. 9 is a schematic structural diagram of a row scan driving circuit disclosed in Embodiment 2 of the present application;

Fig. 10 is a kind of working timing diagram of the row scanning driving circuit corresponding to Fig. 9;

FIG. 11 is an analog operation timing diagram of the row scan driving circuit corresponding to FIG. 10 .

Detailed ways

In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the accompanying drawings and the following various specific embodiments of the present invention, wherein the same symbols in the accompanying drawings represent the same or similar components.

Specific embodiments of various aspects of the present invention will be described in further detail below with reference to the accompanying drawings.

First, some terms are explained:

The transistors in the present invention may be field effect transistors or bipolar transistors.

When the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor pole.

When the transistor is a bipolar transistor, its control electrode refers to the base electrode of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the bipolar transistor. Emitter or collector; the transistor in a display is usually a type of field effect transistor: a thin film transistor (TFT).

The present application is described in detail below by taking the transistor as a field effect transistor as an example. In other embodiments, the transistor may also be a bipolar transistor.

Referring to FIG. 1 , it is a structural diagram of a low temperature polysilicon TFT. The polysilicon TFT adopts a self-aligned top-gate structure design, so that the gate can be made of Al material with low resistivity as the electrode, which greatly reduces the cost and improves the lithography technology. The production process of polysilicon is mainly divided into: (1) sputtering a metal layer on the glass substrate to form the source and drain, and photolithography to form the source and drain (2) PECVD (plasma enhanced chemical vapor deposition) deposition of the base film and non-metallic A crystalline silicon film, and through a low-temperature laser annealing method, the amorphous silicon film is crystallized into a polysilicon film, and boron is doped by ion implantation to form a doped region (3) PECVD deposition insulating layer, the insulating layer material is generally SiO ₂ (4) sputtering a layer of metal film, photolithography etching to form gate, and depositing an insulating layer (5) photolithography to form contact holes, sputtering pixel electrode transparent conductive film ITO, photolithography etching to form pixel electrodes.

LTPS TFT has high carrier mobility and stable electrical properties, and is suitable for circuit design with high response speed, high reliability, and low power consumption. Compared with the N-type LTPS TFT manufacturing process, the P-type LTPS TFT manufacturing process is simpler. This is because when the doped region is formed, the P-type structure needs boron ion implantation, and the ion energy only needs 10KeV, while the N-type structure needs the P ion energy to reach 70KeV. Secondly, the heat resistance and stability of P-type LTPS TFT are better than that of N-type LTPS TFT. Therefore, when designing a circuit based on LTPS TFT, a TFT with a P-type structure is generally selected.

In this implementation, the effective level is low level, because the devices selected in the circuit design of the present invention are all P-type TFTs. In other alternative embodiments, the active level may also be determined to be a high level according to the selected transistor. For example, when the circuit function is realized based on N-type TFT, the effective level can be selected as a high level. The signal overlap mentioned in the present invention means that the two signals are in the active level state at least at the same time. Therefore, the non-overlapping is the time when the two signals are not in the active level state together.

Embodiment 1;

Referring to FIG. 2 , a structural diagram of a row scan driving circuit unit disclosed in this embodiment includes: an initialization module 10 , an input module 20 , a driving module 30 , a high-level maintenance module 40 and a charge sharing module 50 ;

Wherein, the initialization module 10 is connected to the first pulse signal terminal and the bootstrap node Q, and is used for transmitting GND to the output terminal of the row scan driving circuit unit by switching the switch state to initialize the circuit.

In a specific embodiment, the initialization module 10 includes a fourth transistor and a sixth transistor; the control electrode (eg gate) of the fourth transistor is coupled to the first electrode (eg drain) for inputting the first pulse signal CK1; The second electrode (eg source) of the fourth transistor is coupled to the first electrode (eg drain) of the sixth transistor to form a first node (P); the second electrode (eg source) of the sixth transistor is coupled to the high level terminal ; the control electrode (eg gate) of the sixth transistor is coupled to the bootstrap node Q. In other embodiments, the initialization module may also be implemented in other ways, or add or reduce components. For example, as shown in FIG. 3 , the initialization module not only includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, but also includes a second capacitor C2.

The input module 20 is coupled with the driving module 30 to form a bootstrap node Q, and the bootstrap node Q controls the switch state in response to the level of the first signal IN, and is used for inputting the first signal IN from the first signal input terminal to connect the bootstrap node Q is coupled to a low level to provide a driving voltage; in a specific example, the input module 20 includes a third transistor T3 for inputting the first signal, and the control electrode (eg gate) of the third transistor T3 is coupled to the first signal The second electrode (eg, the source electrode) of the third transistor T3 is coupled to the control electrode (eg, the gate electrode) of the first transistor T1 to form the bootstrap node Q.

The driving module 30 is configured to transmit the active level _VL of the first pulse signal CK1 to the line scanning output terminal of the line scanning driving circuit by switching the switch states, thereby outputting the line scanning signal OUT[n]. In a specific embodiment, the driving module 30 may include a first transistor T1 for coupling to the output terminal of the row scan driving circuit unit and a first capacitor C1 for storing the charge of the driving control terminal Q. For example, the control electrode (eg gate) of the first transistor T1 is coupled to the bootstrap node Q, the first electrode (eg drain) is used to input the first pulse signal CK1, and the second electrode (eg source) is used for row scanning driving The output terminal of the circuit unit; the first capacitor C1 is respectively coupled between the control electrode (eg gate) and the second electrode (eg source) of the first transistor T1.

The high level maintaining module 40 is used for maintaining the switch state switched by the control terminal through its high level, and maintains the row scan signal output terminal of the driving module at a high level after the row scan driving circuit unit outputs the row scan signal. In a specific embodiment, the high level maintaining module 40 includes a fifth transistor T5. The control electrode (eg gate) of the fifth transistor T5 is coupled to the first node P; the first electrode (eg drain) of the fifth transistor T5 is coupled to the output node F; the second electrode (eg source) of the fifth transistor T5 ) is coupled to a constant voltage source GND.

The charge sharing module (50) includes a second transistor T2; the control electrode of the second transistor T2 is coupled to the first pulse signal terminal; the first electrode of the second transistor T2 is coupled to the bootstrap node Q; the second electrode of the second transistor T2 It is coupled to the output node F, and is used for the output of the row scan driving circuit unit; it is used for adaptively adjusting the potential of the bootstrap node Q in response to the state of the output terminal of the row scan driving circuit unit.

In this embodiment, the effective level of the first signal IN arrives earlier than the arrival time of the effective level of the first pulse signal CK1, and the effective level of the first signal IN does not overlap with the effective level of the first pulse signal CK1 .

Please refer to FIG. 5 , which is a working timing diagram of the row scan driving circuit unit disclosed in the first embodiment of the present application. The working process of the line scan driving circuit unit shown in FIG. 2 , FIG. 3 and FIG. 4 will be described in detail below with reference to FIG. 5 . First take Figure 2 as an example:

Initialization stage (P1): the first signal IN is at a high level, and the third transistor T3 is turned off. When the first pulse signal CK1 is at a low level, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. The bootstrap node Q and the output OUT1 are connected together through the second transistor T2 and both are charged to GND through the fifth transistor T5. When the first pulse signal CK1 is at a high level, the fifth transistor T5 is still kept on, and the bootstrap node Q and the output OUT1 are kept at a high level.

Input stage (P2): the first pulse signal CK1 is at a high level, and the second transistor T2 and the fourth transistor T4 are turned off. The first signal IN is at a low level, the third transistor T3 is turned on, the bootstrap node Q is pulled to a low level, and then the first transistor T1 and the sixth transistor T6 are turned on. At this time, the sixth transistor T6 is turned on and the fifth transistor T5 is turned off, and at the same time, the first transistor T1 is turned on, causing the high level of the first pulse signal CK1 to be transmitted to the output terminal of the row scan driving circuit unit.

Bootstrap stage (P3): the first signal IN is at a high level, and the third transistor T3 is turned off. Since the bootstrap node Q remains low, the first transistor T1 and the sixth transistor T6 remain turned on. When the first pulse signal CK1 becomes a low level, the bootstrap node Q is pulled to (V _L -V _{TH_T3} )+(V _L -V _H ) due to the bootstrap effect of the first capacitor. The output OUT1 is quickly pulled to V _L . At the same time, the second transistor T2 is turned off because the output OUT1 is the source of the second transistor and is quickly pulled to _VL . The gate-source voltage of the second transistor T2 is 0V, which is much greater than the threshold voltage of the second transistor T2. When the first pulse signal becomes a high level, the second transistor T2 and the fourth transistor T4 are turned off. Since the first transistor T1 and the sixth transistor T6 are still turned on, the fifth transistor T5 is still turned off, and the first pulse signal CK1 is transmitted to the output terminal of the row scan driving circuit unit through the first transistor T1. At this time, due to the bootstrap effect of the first capacitor C1, the bootstrap node Q is pulled up to V _L -V _{TH_T3} .

Charge sharing stage (P4): the first pulse signal CK1 is at a low level, and the second transistor T2 and the fourth transistor T4 are turned on. The opening of the fourth transistor T4 results in the opening of the fifth transistor T5, through which GND is passed to the output terminal OUT1. Since the bootstrap node Q and the output OUT1 are connected together through the second transistor T2, the voltage of the bootstrap node is determined by the shared charge of the first capacitor C1 and the load capacitor C. At this time, the _total charge stored on the capacitor is: Qtotal=C ₁ ×(V _L -V _{TH_T3} ), and the charge shared by the load capacitor C is: Since the load capacitance is much larger than the first capacitor C1, the charge stored on the first capacitor almost flows to the load capacitor C, and there is almost no charge stored on the first capacitor C1, so that the bootstrap node Q is pulled to a high level.

High level hold stage (P5): the first signal IN is at a high level, and the third transistor T3 is turned off. When the first pulse signal CK1 is at a low level, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. The bootstrap node Q is connected to the output terminal OUT1 and remains at a high level.

When the first pulse signal CK1 is at a high level, the second transistor T2 and the fourth transistor T4 are turned off, and the fifth transistor T5 is still turned on. The bootstrap node Q is connected to the output terminal OUT1 and remains at a high level.

After that, regardless of whether the first pulse signal is at a high level or a low level, the fifth transistor T5 remains in an open state, and the output OUT1 is also at a high voltage until the first signal IN is re-inputted at a low level in the next frame.

It should be noted that, in the high-level sustaining stage, the voltages of the gate and source of the first transistor T1 are easily affected by the clock feedthrough effect, and their voltages will float following the change of the first pulse signal CK1. For the row driving circuit, besides the row scanning signal, the output of the row scanning driving circuit should be in a high-level maintenance state most of the time. The floating of the voltage of the gate and source of the first transistor T1 may be transmitted in the line scan driving circuit chain, resulting in a large-amplitude noise voltage appearing in the line scan signal output by the line scan driving circuit in the high-level sustaining part , and this noise voltage may accumulate pole by pole, which will eventually lead to the logic disorder of the output of the row scan drive circuit, resulting in false turn-on. In order to suppress the influence of the clock feed-through effect, a high-level maintenance module is introduced into the integrated circuit. When the high-level maintenance control terminal of the high-level maintenance control terminal obtains an effective level, the fifth transistor T5 and the second transistor T2 are turned on, respectively The bootstrap node Q and the row signal output terminal are coupled to the high-level terminal, and are maintained at the high-level voltage V _H , thereby maintaining the high-level voltage of the row scan signal output by the row scan driving circuit.

In another specific embodiment, please refer to FIG. 3 , the initialization module may include a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a second capacitor C2 . The control electrode (eg gate) of the fourth transistor T4 and the control electrode (eg gate) of the sixth transistor T6 may be coupled together and to the bootstrap node Q through the second capacitor C2. The advantages of this embodiment are:

(1) The control electrode (eg gate) of the fourth transistor T4 is coupled to the bootstrap node Q through the second capacitor C2, which improves the driving capability of the fourth transistor T4 and reduces the dynamic power consumption of the circuit. This is because the gate voltage of the fourth transistor T4 is modulated by the bootstrap node Q, and in the pull-down phase, the gate voltage of the fourth transistor T4 can be pulled down to (V _L -V _{TH_T3} )+(V _L -V _H ) , thereby improving the driving capability of the fourth transistor. Secondly, in the high-level sustaining stage, the fourth transistor T4 is turned off, and its gate-source and gate-drain parasitic capacitances no longer generate dynamic power consumption.

(2) The fourth transistor T4 works in the linear region, which improves the response speed of the circuit. This is because the fourth transistor T4 no longer adopts the gate-source shorting method, and the fourth transistor T4 can be quickly turned on when the bootstrap node Q is at a low level, thereby improving the response speed of the circuit.

In another specific embodiment, please refer to FIG. 4 , the initialization module may include a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a second pulse signal CK2 . The control stage (eg gate) of the fourth transistor T4 and the control stage (eg gate) of the second transistor T2 may be coupled to the second pulse signal CK2, and the first stage (eg drain) of the fourth transistor T4 is coupled to the control level. The control stage (eg gate) of the sixth transistor T6 is coupled to the bootstrap node Q. In this way, three pulse signal control circuits with a duty ratio of 1/3, four pulse control circuits with a duty ratio of 1/4, etc., and four overlapping pulse signals with a duty ratio of 1/2 can be controlled. circuit. Taking the three-way pulse signal control circuit with a duty ratio of 1/3 as an example, when using three-way clock pulse control with a duty ratio of 1/3, the first pulse signal terminal of the first stage outputs CK1, and the second pulse input CK2 is input to the terminal; the first pulse signal terminal of the second stage outputs CK2, and the second pulse input terminal inputs CK3; the first pulse signal terminal of the third stage outputs CK3, and the second pulse input terminal inputs CK1;

Next, taking the three-way pulse signal control circuit with a duty ratio of 1/3 as an example, in the high level holding stage, the second pulse signal CK2 is at a low level, the second transistor T2 is turned on, and the first pulse signal CK1 is at a high level. The level charges the bootstrap node Q through the second transistor T2, so that the sixth transistor T6 is turned off. At this time, the fourth transistor T4 is turned on, the first node P becomes a low level, and then the fifth transistor T5 is continuously turned on, so that the output OUT[n] will always be kept at a high level in the high-level holding stage. The advantages of this embodiment are:

(1) Using pulse signals with different duty ratios as control signals can reduce the dynamic power consumption of the circuit. This is because using pulse signals with different duty ratios as the control signal can reduce the frequency of the pulse signal in the circuit, thereby reducing the dynamic power consumption generated by the parasitic capacitance connected to the pulse signal when the pulse clock jumps.

(2) The overlapping output OUT[n] can also be realized by controlling the input pulse signal.

FIG. 6 is the simulation result of the row scan driving circuit unit shown in FIG. 2 , from top to bottom, the first pulse signal CK1, the first input signal IN, the output voltage of the bootstrap node Q, the output voltage of the first node P, and the output signal OUT [1]. Moreover, a load resistor with a resistance value of 2000 and a capacitance value of 300pF is connected to the output end of the line scan signal OUT[1]. FIG. 6 shows that the row scan driving circuit disclosed in this embodiment can normally output row scan signals.

FIG. 7 is a simulation result of the line scan driving circuit unit shown in FIG. 4 , in which three-way pulse signals with a duty ratio of 1/3 are used for control. The simulation result diagram from top to bottom is the first pulse signal CK1, the second pulse signal CK2, the first input signal IN, the output voltage of the bootstrap node Q, the output voltage of the first node P, and the output signal OUT[1]. And a load resistor with a resistance value of 2000 and a capacitance value of 300pF is connected to the output end of the line scan signal OUT[1]. FIG. 7 shows that the row scan driving circuit disclosed in the present embodiment with the structure shown in FIG. 4 can output row scan signals normally.

To sum up, the advantages of the row scan driving circuit unit circuit of the present invention are:

(1) The circuit structure is simple, and the unit circuit only uses 6 P-TFTs, 1 capacitor and 1 clock signal. It is beneficial to the realization of the narrow border active TFT panel.

(2) Compared with the traditional circuit that uses two large drive tubes to achieve the pull-up and pull-down functions, this unit circuit uses one large drive tube to achieve the above functions, which saves the circuit area and the power consumption caused by the parasitic capacitance of the large drive tube.

Embodiment 2:

By cascading the above row scan drive circuit units, the present application discloses a row scan drive circuit. Please refer to FIG. 8 , which is a structural block diagram of a row scanning driving circuit disclosed in Embodiment 2 of the present application. Each level of row scanning driving circuit unit needs to have three input signals: a first input signal IN, a first pulse signal CK1 or a second pulse signal CK1 Pulse signal CK2, high-level input GND is represented by V _H in the figure, and one output signal OUT[n].

It can be seen from the single-stage line scan driving circuit in FIG. 6 that the effective level of the output signal of the line scan driving circuit unit is generated by the low level output of the first pulse signal CK1, so the output signal can be determined by adjusting the first pulse signal CK1.

Please refer to FIG. 9 , which is a schematic structural diagram of a row scan driving circuit disclosed in Embodiment 2 of the present application, wherein OUT[n] is the output signal of the n-th row scan driver circuit unit, n=1, 2, 3, 4... ….

The line scan driving circuit includes:

A plurality of cascaded row scan drive circuit units.

Please refer to FIG. 10 , which is a timing control diagram of a row scan driving circuit disclosed in Embodiment 2 of the present application.

The two clock lines (CK1, CK2) are used to transmit the required clock signals to the row scan driving circuit units of all levels.

CK1 and CK2 provide two clock signals with a duty cycle of 50%. The first pulse signal of the odd-numbered row scanning driving circuit is provided by the clock signal line CK1, and the first pulse signal of the even-numbered row scanning driving circuit is provided by the clock line CK2.

Specifically, the first signal IN of the scan driving circuit unit in this row leads the output signal of the scan driving circuit unit in the row. For the m-th row scan driver circuit, its first signal IN input node is connected to the signal output terminal of the m-1 th row scan driver circuit unit; its output signal OUT[m] is connected to the m+1-th row scan driver The first signal input node of the circuit unit.

Fig. 11 is the simulation result of the line scan driving circuit shown in Fig. 9, in which OUT[1]~OUT[4] are the line scan signals of the first row to the fourth row, and the line scan signal output end of each row is connected to The resistance value is 2000 load resistor and the capacitance value is 300pF load capacitor. FIG. 11 shows that the logic of the row scan driving circuit disclosed in this embodiment is correct, and the row scan signal can be outputted well.

To sum up, the row scan driving circuit disclosed in this application has the following advantages:

(1) The unit circuit structure of the row scanning driving circuit is simple, and only 6 TFTs and 1 capacitor are required for a single stage.

(2) The state switching signal of the control terminal of the high-level maintenance module and the control signal of the driving module are multiplexed, so the overall circuit structure is simple, which is beneficial to the realization of the narrow-frame active TFT panel.

(3) Compared with the active TFT panel that does not integrate the row scan driver circuit (n-level row scan driver circuit unit, used as the row scan driver circuit) on the TFT panel, nearly n external pins are saved. Therefore, the line scan driving circuit disclosed in this embodiment is extremely advantageous for forming a display panel with a narrow frame.

The present invention is described above by using specific examples, just to help those of ordinary skill in the art to understand well. Various deductions, modifications and substitutions may also be made to the specific embodiments of the present invention without departing from the spirit and scope of the present invention. These changes and substitutions will fall within the scope defined by the claims of the present invention.

Claims (6)

1. a kind of TFT integrated line-scanning drive circuit, which is characterized in that including a line-scanning drive circuit unit；

The line-scanning drive circuit unit includes initialization module (10), drive module (30), input module (20), high level Maintenance module (40) and charge sharing module (50)；

The initialization module (10) is connected with the first pulse signal end and bootstrapping node Q, and the signal on ground terminal GND is transmitted To the output end of line-scanning drive circuit unit, line-scanning drive circuit is initialized；

The drive module (30) is connected with the first pulse signal end, and the significant level of the first pulse signal is transmitted to capable scanning The output end of drive circuit unit；

The input module (20) and drive module are coupled in bootstrapping node Q, respond the level control input module of initial pulse The switching state of middle switch；

The high level maintenance module (40) is used for after line-scanning drive circuit unit exports line scan signals, by drive module Line scan signals output end maintain high level；

The charge sharing module (50) is coupled between bootstrapping node Q and the output end of line-scanning drive circuit unit, is used for Adjust the current potential of bootstrapping node Q with responding the state self-adaption of line-scanning drive circuit unit output end；

The line-scanning drive circuit initialization module (10) is connected with input module (20), and the first signal IN passes through input module (10) it is transmitted to drive module (30), after drive module (30) responds the first signal IN, the first pulse signal is transmitted to row and is swept Scanning circuit output end；High level maintenance module (40) is connected with charge sharing module (50), respectively passes signal on ground terminal GND It is sent to the output end of line-scanning drive circuit unit and output end signal is transmitted to bootstrapping node Q；The charge sharing module (50) one end is connected with bootstrapping node Q, and the other end is connected with the output end of line-scanning drive circuit unit；

The TFT is low temperature polycrystalline silicon TFT；

The charge sharing module (50) includes second transistor T2；

The control electrode of second transistor T2 is coupled to the first pulse signal end；The first pole of second transistor T2 is coupled to bootstrapping section Point Q；The second pole of second transistor T2 is coupled to output node F, exports for line-scanning drive circuit unit；

The initialization module (10) includes the second capacitor C2, the 4th transistor T4 and the 6th transistor T6；

The both ends of the second capacitor C2 are connected between the control electrode of the 6th transistor and bootstrapping node Q, and the 4th transistor The control electrode of T4 is connected with one end of the second capacitor C2, and the control electrode of the control electrode of the 4th transistor T4 and the 6th transistor T6 It is connected；

The first pole of the 4th transistor T4 is coupled to the first pulse CK1, and the second pole is coupled to the of the 6th transistor T6 One pole forms first node P；

The second pole of the 6th transistor T6 is coupled to ground terminal GND.

2. line-scanning drive circuit according to claim 1, which is characterized in that the drive module (30) includes first brilliant Body pipe T1 and first capacitor C1；

The control electrode of the first transistor T1 is coupled to bootstrapping node Q；The first pole of the first transistor T1 and the first pulse signal end CK1 is connected；The second pole of the first transistor T1 is coupled to output node F；

The both ends of first capacitor C1 are coupled between the control electrode of the first transistor T1 and the second pole.

3. line-scanning drive circuit according to claim 2, which is characterized in that the input module (20) includes third crystalline substance Body pipe T3；

The second pole of third transistor T3 is coupled to bootstrapping node Q；The control electrode of third transistor T3 is coupled with the first pole, is used for The input of first signal N.

4. line-scanning drive circuit according to claim 3, which is characterized in that the high level maintenance module (40) includes 5th transistor T5；

The control electrode of 5th transistor T5 is coupled to the second pole of the 4th transistor T4；The first pole of 5th transistor T5 is coupled to Output node F；The second pole of 5th transistor T5 is coupled to ground terminal GND.

5. line-scanning drive circuit according to claim 1-4, which is characterized in that including including at least two grades The line-scanning drive circuit unit of connection；

The signal output end of prime line-scanning drive circuit unit and the first signal end IN of rear class line-scanning drive circuit unit It is connected.

6. a kind of driving method of line-scanning drive circuit, which is characterized in that swept using the described in any item rows of claim 1-5 Driving circuit is retouched, the first signal is inputted from input module, from drive module input pulse signal, in the ground terminal of initialization module GND inputs GND signal；

When line-scanning drive circuit is that multistage line-scanning drive circuit is unit cascaded, the first of odd level line-scanning drive circuit Pulse signal is provided by the first clock signal CK1, and the first pulse signal of even level line-scanning drive circuit is by second clock CK2 It provides；

Wherein, second clock signal CK2 is opposite with the timing of the first clock signal CK1.