CN106125430A - The preparation method of array base palte, display floater and array base palte - Google Patents

Abstract

The invention discloses an array substrate, comprising: a substrate; a gate formed on the substrate; a gate insulating layer formed on a side of the substrate facing the gate, and the gate insulating layer covers the gate; an active layer formed on the On the side of the gate insulating layer away from the gate, the active layer is made of a metal oxide material and is arranged facing the gate; the source and drain spaced apart from each other are formed on the side of the gate insulating layer away from the gate, The source and the drain are respectively connected to both ends of the active layer; a passivation layer is formed on the side of the source away from the gate insulating layer, and the passivation layer covers the source, the drain and the active layer; and a light-shielding layer , formed on the side of the passivation layer away from the active layer, and the vertical projection of the light shielding layer on the gate insulating layer covers the active layer. The yield rate of the array substrate of the present invention is high. The invention also discloses a method for preparing a display panel and an array substrate.

Description

Array substrate, display panel and method for preparing array substrate

technical field

The present invention relates to the technical field of display panels, in particular to an array substrate, a display panel and a method for preparing the array substrate.

Background technique

With the development of display technology, liquid crystal displays (Liquid Crystal Display, LCD) and other flat display devices are widely used in mobile phones, televisions, personal Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream of display devices.

Most of the liquid crystal display devices currently on the market are backlight liquid crystal displays, which include a liquid crystal display panel and a back light module. The working principle of the liquid crystal display panel is to place liquid crystal molecules between two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The direction of the liquid crystal molecules is controlled by electrifying or not, and the light of the backlight module Refracted out to produce a picture.

Usually, a liquid crystal display panel consists of a color filter (Color Filter, CF) substrate, a thin film transistor (Thin Film Transistor, TFT) array substrate, a liquid crystal (Liquid Crystal, LC) and a sealant frame (Sealant) sandwiched between the color filter substrate and the array substrate. )composition. Among them, the performance of the thin film transistors of the array substrate directly affects the display quality of the liquid crystal display panel.

With the development of large size and high PPI (Pixels Per Inch, the number of pixels per inch) and high refresh rate products, thin film transistors using oxide semiconductors have been widely valued and applied due to their high mobility. However, since the oxide semiconductor is easily affected by light, the electrical properties of the thin film transistor are unstable, and the product yield of the array substrate is low.

Contents of the invention

The technical problem to be solved by the present invention is to provide an array substrate with high yield.

In addition, a display panel using the array substrate is also provided.

In addition, a method for preparing the array substrate is also provided.

In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:

In one aspect, an array substrate is provided, comprising:

Substrate;

a gate formed on the substrate;

a gate insulating layer formed on a side of the substrate facing the gate, the gate insulating layer covering the gate;

an active layer formed on a side of the gate insulating layer away from the gate, the active layer is made of a metal oxide material and is disposed facing the gate;

A source and a drain spaced apart from each other are formed on a side of the gate insulating layer away from the gate, and the source and the drain are respectively connected to two ends of the active layer;

a passivation layer formed on a side of the source electrode away from the gate insulating layer, the passivation layer covering the source electrode, the drain electrode and the active layer; and

A light-shielding layer is formed on a side of the passivation layer away from the active layer, and a vertical projection of the light-shielding layer on the gate insulating layer covers the active layer.

Wherein, the light-shielding layer is made of black resin material.

Wherein, the active layer adopts indium gallium zinc oxide.

Wherein, the passivation layer has a through hole for exposing part of the source;

The array substrate further includes a pixel electrode formed on a side of the passivation layer away from the source, and the pixel electrode is connected to the source through the through hole.

In another aspect, a display panel is also provided, including the array substrate as described in any one of the above items.

In another aspect, a method for preparing an array substrate is also provided, including:

sequentially forming gates on the substrate;

forming a gate insulating layer on a side of the substrate facing the gate, the gate insulating layer covering the gate;

An active layer is formed on a side of the gate insulating layer away from the gate, the active layer is made of a metal oxide material and is disposed facing the gate;

A source and a drain spaced apart from each other are formed on a side of the gate insulating layer away from the gate, and the source and the drain are respectively connected to two ends of the active layer;

forming a passivation layer on a side of the source electrode away from the gate insulating layer, the passivation layer simultaneously covering the source electrode, the drain electrode and the active layer; and

A light-shielding layer is formed on a side of the passivation layer away from the active layer, and a vertical projection of the light-shielding layer on the gate insulating layer covers the active layer.

Wherein, the same photomask is used to form the active layer and the light shielding layer.

Wherein, the light-shielding layer is made of black resin material.

Wherein, the active layer adopts indium gallium zinc oxide.

Wherein, the preparation method of the array substrate also includes:

forming a through hole on the passivation layer to expose part of the source;

A pixel electrode is formed on a side of the passivation layer away from the source, and the pixel electrode is connected to the source through the through hole.

Compared with the prior art, the present invention has the following beneficial effects:

The array substrate of the present invention is provided with the light-shielding layer, so it can prevent light from entering the active layer of the thin film transistor, so that the thin film transistor has good electrical stability, and the performance of the array substrate is good , High yield.

Description of drawings

In order to illustrate the technical solution of the present invention more clearly, the accompanying drawings used in the implementation will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some implementations of the present invention. As far as technical personnel are concerned, other drawings can also be obtained like these drawings without paying creative work.

1 to 8 are structural schematic diagrams of various steps in a method for manufacturing an array substrate according to an embodiment of the present invention.

FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the implementation manners in the present invention, all other implementation manners obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Please refer to FIG. 8 , an embodiment of the present invention provides an array substrate 10 , including a substrate 1 , a gate 2 , a gate insulating layer 3 , an active layer 4 , a source 5 and a drain 6 spaced from each other, and a passivation layer 7 And the light-shielding layer 8. Wherein, the gate 2 is formed on the substrate 1 . The gate insulating layer 3 is formed on a side of the substrate 1 facing the gate 2 and covers the gate 2 . The active layer 4 is formed on a side of the gate insulating layer 3 away from the gate 2 , the active layer 4 is made of a metal oxide material and is disposed facing the gate 2 . The source 5 and the drain 6 are formed on a side of the gate insulating layer 3 away from the gate 2 , and are respectively connected to two ends of the active layer 4 . The passivation layer 7 is formed on the side of the source 5 away from the gate insulating layer 3, and the passivation layer 7 simultaneously covers the source 5, the drain 6 and the active Layer 4. The light shielding layer 8 is formed on a side of the passivation layer 7 away from the active layer 4 , and the vertical projection of the light shielding layer 8 on the gate insulating layer 3 covers the active layer 4 .

The array substrate 10 in this embodiment, since it is provided with the light-shielding layer 8, can effectively prevent light from entering the active layer 4 of the thin film transistor, so that the thin film transistor has good electrical stability, The array substrate 10 has good performance and high yield.

Wherein, the material of the gate 2 may be one or more stacked combinations of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The gate 2 can also play a light-shielding function to prevent light from entering the active layer 4 of the thin film transistor, so that the thin film transistor has good electrical stability and improves the stability of the array substrate 10. yield.

Further, as an optional implementation manner, the light-shielding layer 8 is made of black resin material, which has low cost and mature technology.

Preferably, the active layer 4 uses indium gallium zinc oxide, so that the threshold voltage of the thin film transistor does not drift, the carrier solubility is high, and it can be charged quickly, thereby improving the yield and charging rate of the thin film transistor .

Further, please refer to FIG. 7 and FIG. 8 together. As an optional implementation manner, the passivation layer 7 has a through hole 70 , and the through hole 70 is used to expose part of the source electrode 5 . The array substrate 10 further includes a pixel electrode 9 formed on the passivation layer 7 and connected to the source 5 through the through hole 70 .

Please refer to FIG. 8 and FIG. 9 together. The embodiment of the present invention also provides a display panel 100. The display panel 100 includes an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and The liquid crystal layer 30 between the film substrates 20, the array substrate 10 adopts the array substrate 10 described in any one of the above implementation modes. Since the array substrate 10 has high yield and performance, the display quality of the display panel 100 is good.

Please refer to FIG. 1 to FIG. 6 together. The embodiment of the present invention also provides a method for preparing an array substrate, including:

Step1: Form gate 2 sequentially on substrate 1, as shown in Figure 1;

Step2: Form a gate insulating layer 3 on the side of the substrate 1 facing the gate 2, the gate insulating layer 3 covers the gate 2, as shown in FIG. 2 ;

Step3: Form an active layer 4 on the side of the gate insulating layer 3 away from the gate 2, the active layer 4 is made of a metal oxide material and is arranged facing the gate 2, as shown in Figure 3 shown;

Step4: Form a source 5 and a drain 6 spaced from each other on the side of the gate insulating layer 3 away from the gate 2, and the source 5 and the drain 6 are respectively connected to the active Both ends of the layer 4, the gate 2, the active layer 4, the source 5 and the drain 6 jointly form a thin film transistor, as shown in FIG. 4 ;

Step5: Form a passivation layer 7 on the side of the source 5 away from the gate insulating layer 3, and the passivation layer 7 simultaneously covers the source 5, the drain 6 and the active Layer 4, as shown in Figure 5;

Step6: forming a light-shielding layer 8 on the side of the passivation layer 7 away from the active layer 4 , the vertical projection of the light-shielding layer 8 on the gate insulating layer 3 covers the active layer 4 , As shown in Figure 6.

The array substrate 10 formed by the preparation method of the array substrate described in this embodiment mode can prevent light from entering the active layer 4 of the thin film transistor because the light shielding layer 8 is provided, so that the thin film transistor has With good electrical stability, the performance of the array substrate 10 is good and the yield rate is high, so the product yield rate of the manufacturing method of the array substrate is high.

Wherein, the material of the gate 2 may be one or more stacked combinations of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The gate 2 can also play a light-shielding function to prevent light from entering the active layer 4 of the thin film transistor, so that the thin film transistor has good electrical stability and improves the preparation of the array substrate. The product yield of the method.

Further, as an optional implementation, the active layer 4 and the light-shielding layer 8 may be formed using the same photomask, so as to reduce the number of photomasks required in the manufacturing process and reduce production costs.

It can be understood that since the position and shape of the light-shielding layer 8 are set completely corresponding to the active layer 4 , the same mask can be used to form the active layer 4 and the light-shielding layer 8 . At the same time, it should be noted that in the manufacturing process of the light-shielding layer 8, the photomask can be properly matched with the process debugging (for example, adjusting the distance between the photomask and the film layer where the light-shielding layer 8 is located during exposure), so that the light-shielding layer The area of the light-shielding layer 8 is slightly larger than that of the active layer 4 so as to completely cover the active layer 4 and effectively prevent light from entering the active layer 4 .

Further, as an optional implementation manner, the light-shielding layer 8 is made of black resin material, which has low cost and mature technology.

Preferably, the active layer 4 uses indium gallium zinc oxide, so that the threshold voltage of the thin film transistor does not drift, the carrier solubility is high, and it can be charged quickly, thereby improving the yield and charging rate of the thin film transistor .

Further, please refer to FIG. 7 and FIG. 8, as an optional implementation manner, the preparation method of the array substrate further includes:

Step7: forming a via hole 70 on the passivation layer 7 to expose part of the source electrode 5, as shown in FIG. 7 ;

Step8: Form a pixel electrode 9 on the side of the passivation layer 7 away from the source electrode 5 , and the pixel electrode 9 is connected to the source electrode 5 through the through hole 70 , as shown in FIG. 8 .

The embodiments of the present invention have been described in detail above, and specific examples have been used to illustrate the principles and embodiments of the present invention. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present invention; meanwhile, for Those skilled in the art will have changes in the specific implementation and scope of application according to the idea of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

1. an array base palte, it is characterised in that including:

Substrate；

Grid, is formed on the substrate；

Gate insulator, is formed at the side towards described grid of described substrate, and described gate insulator covers described grid；

Active layer, is formed at the side away from described grid of described gate insulator, and described active layer uses metal-oxide Material and just described grid being arranged；

The source electrode being spaced and drain electrode, be formed at the side away from described grid of described gate insulator, described source electrode and Described drain electrode is respectively connecting to the two ends of described active layer；

Passivation layer, is formed at the side away from described gate insulator of described source electrode, and described passivation layer covers described source electrode, institute State drain electrode and described active layer；And

Light shield layer, is formed at the side away from described active layer of described passivation layer, and described light shield layer is at described gate insulator On upright projection cover described active layer.

2. array base palte as claimed in claim 1, it is characterised in that described light shield layer uses black resin material.

3. array base palte as claimed in claim 1 or 2, it is characterised in that described active layer uses indium gallium zinc oxide.

4. array base palte as claimed in claim 1, it is characterised in that described passivation layer has through hole, in order to expose part Described source electrode；

Described array base palte also include pixel electrode, described pixel electrode be formed at described passivation layer away from the one of described source electrode Side, described pixel electrode is connected to described source electrode by described through hole.

5. a display floater, it is characterised in that include the array base palte as described in any one of Claims 1 to 4.

6. the preparation method of an array base palte, it is characterised in that including:

Substrate sequentially forms grid；

Forming gate insulator in the side towards described grid of described substrate, described gate insulator covers described grid；

Be formed with active layer in the side away from described grid of described gate insulator, described active layer uses metal-oxide material Expect and just described grid arranged；

The source electrode and drain electrode, described source electrode and institute being spaced is formed in the side away from described grid of described gate insulator State drain electrode and be respectively connecting to the two ends of described active layer；

Forming passivation layer in the side away from described gate insulator of described source electrode, described passivation layer covers described source simultaneously Pole, described drain electrode and described active layer；And

Forming light shield layer in the side away from described active layer of described passivation layer, described light shield layer is on described gate insulator Upright projection cover described active layer.

7. the preparation method of array base palte as claimed in claim 6, it is characterised in that use identical light shield formed described in have Active layer and described light shield layer.

The preparation method of array base palte the most as claimed in claims 6 or 7, it is characterised in that described light shield layer uses black tree Fat material.

The preparation method of array base palte the most as claimed in claims 6 or 7, it is characterised in that described active layer uses indium gallium zinc Oxide.

10. the preparation method of array base palte as claimed in claim 6, it is characterised in that also include:

Described passivation layer forms through hole, in order to expose the described source electrode of part；

Forming pixel electrode in the side away from described source electrode of described passivation layer, described pixel electrode is connected by described through hole To described source electrode.