CN106100633A - A kind of crystal oscillator drive circuit - Google Patents

Abstract

The embodiment of the invention discloses a kind of crystal oscillator drive circuit, described circuit includes: bias current generation unit, resistance unit and electric current can configure amplifier unit；Wherein, bias current generation unit, can configure amplifier unit with described resistance unit and described electric current respectively and be connected, providing operating current for can configure amplifier unit to described resistance unit and electric current；Resistance unit, can configure amplifier unit with described electric current and is connected, and sets up DC point for can configure amplifier unit to described electric current；Electric current can configure amplifier unit, it is connected with input and the outfan of crystal oscillator respectively, for operating current being amplified under the control of DC point, to drive crystal oscillator starting of oscillation, achieve the power consumption reducing drive circuit, reduce the area shared by drive circuit, and improve the purpose of the scope of application of drive circuit.

Description

Crystal oscillator drive circuit

Technical Field

The embodiment of the invention relates to a circuit technology, in particular to a crystal oscillator driving circuit.

Background

With the increasing development of science and technology, electronic products are continuously updated, but the implementation of each electronic product cannot be separated from a digital circuit, the digital circuit cannot be separated from an oscillator, and the oscillator generates accurate clock pulses so as to control the digital circuit to work sequentially. Crystal oscillators are widely used in integrated systems on chip, and are usually used to provide an accurate clock source for a real-time clock module. With the popularization of the internet of things and portable mobile devices powered by batteries, the batteries are required to be capable of effectively supplying power for years or even longer, which puts a strict limit on the power consumption of a crystal oscillator driving circuit in a chip and generally requires that the working current of the crystal oscillator driving circuit is controlled below 1 muA.

A conventional driving circuit of a crystal oscillator in the prior art as shown in fig. 1 comprises an inverting amplifier INV and a feedback resistor RF. The whole crystal oscillator circuit also comprises an off-chip quartz crystal and matching capacitors C1 and C2. Wherein, inverter INV and feedback resistance RF form the drive circuit, compensate the inherent loss of the quartz crystal, maintain the oscillation of the system, for this reason, inverter INV must offer minimum transconductance

${\mathrm{gm}}_{crit}=4R_m{\mathrm{\ω}}^2{(\frac{C_1{C}_2}{C_1+C_2}+C_0)}^2$

Wherein R is_mIs the equivalent series resistance of the crystal oscillator, omega is the resonance frequency of the crystal oscillator, C₀The capacitors C1 and C2 are capacitance values of off-chip matching capacitors, and the transconductance of the inverting amplifier is generally required to be at least 5 times the minimum transconductance in circuit design, so as to ensure that the crystal oscillator can start oscillation under various process, voltage and temperature changes. In the inverting amplifier INV, both NMOS and PMOS transistors work in saturation region, and the relationship between transconductance and working current is:

$gm=\frac{2I_D}{V_{gs}-V_{th}}$

wherein, V_gsIs the gate-source voltage of the transistor, V_thIs the threshold voltage of the transistor, I_DIs the drain current.

However, the disadvantage of this circuit configuration is that the overdrive voltage of the transistor is relatively large and increases with increasing supply voltage. Resulting in low current utilization efficiency thereof and variation of the inverter current with variation of the power supply voltage, resulting in variation of the oscillation characteristics of the circuit with variation of the power supply voltage. In order to ensure the starting oscillation, a large margin must be left in the circuit design, and the power consumption consumed by the circuit is large. For example, at a voltage of 3.3V, the current consumed by such a circuit when driving a 32.768kHz crystal oscillator is typically about 6-7 μ A. On the other hand, the feedback resistor RF provides a dc operating point for the inverter INV at the start stage of oscillation starting, and the resistance value is generally required to be greater than 10M Ω, which occupies a large area in a chip and increases the chip cost.

Disclosure of Invention

The invention provides a crystal oscillator driving circuit, which is used for reducing the power consumption of the driving circuit, reducing the occupied area of the driving circuit and improving the application range of the driving circuit.

The embodiment of the invention provides a crystal oscillator driving circuit, which comprises:

the bias current generating unit, the resistance unit and the current configurable amplifier unit; wherein,

the bias current generating unit is respectively connected with the resistance unit and the current configurable amplifier unit and is used for providing working current for the resistance unit and the current configurable amplifier unit;

the resistance unit is connected with the current configurable amplifier unit and used for establishing a direct-current working point for the current configurable amplifier unit;

and the current configurable amplifier unit is respectively connected with the input end and the output end of the crystal oscillator and is used for amplifying the working current under the control of a direct current working point so as to drive the crystal oscillator to start oscillation.

Preferably, the circuit further comprises: and the signal amplifying and shaping unit is connected with the current configurable amplifier unit and is used for amplifying and shaping the signal at the input end of the crystal oscillator and outputting a start oscillation mark signal of the crystal oscillator.

Further, the circuit further comprises: and the starting unit is respectively connected with the bias current generating unit and the signal amplifying and shaping unit and is used for controlling the starting of the bias current generating unit under the control of the starting vibration mark signal.

Preferably, the bias current generating unit specifically includes:

a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor, wherein:

the grid electrodes of the first PMOS transistor and the second PMOS transistor are connected, the source electrode of the first PMOS transistor is connected with the power supply to form a current mirror, and the drain electrode of the first PMOS transistor is connected with the first end of the first resistor and the grid electrode of the first NMOS transistor; the drain electrode of the second PMOS transistor is connected with the grid electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor; the grid electrode of the second NMOS transistor is connected with the drain electrode of the first NMOS transistor and the second end of the first resistor, and the source electrode of the second NMOS transistor and the source electrode of the first NMOS transistor are both grounded.

Preferably, the resistance unit specifically includes:

a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor composed of three NMOS transistors connected in series, wherein,

the grid electrode of the third PMOS transistor is connected with the grid electrode of the second PMOS transistor, the source electrode of the third PMOS transistor is connected with the power supply, and the drain electrode of the third PMOS transistor is connected with the grid electrode of the fifth NMOS transistor and the drain electrode and the grid electrode of the fourth NMOS transistor; the source electrode of the fourth NMOS transistor is connected with the drain electrode and the grid electrode of the third NMOS transistor; the source of the third NMOS transistor is grounded.

Preferably, the current-configurable amplifier unit specifically includes:

a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor, wherein,

the source electrode of the fourth PMOS transistor is connected with the power supply, the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor and the grid electrode of the fifth PMOS transistor, and the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the sixth NMOS transistor, the drain electrode of the fifth NMOS transistor and the output end of the crystal oscillator; the grid electrode of the sixth NMOS transistor is connected with the source electrode of the fifth NMOS transistor and the input end of the crystal oscillator, and the source electrode is grounded; the source electrode of the eighth PMOS transistor is connected with the power supply, the grid electrode of the eighth PMOS transistor is connected with the current control signal, and the drain electrode of the eighth PMOS transistor is connected with the source electrode of the fifth PMOS transistor; the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the seventh NMOS transistor and the output end of the crystal oscillator; the source electrode of the seventh NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, and the grid electrode of the seventh NMOS transistor is connected with the grid electrode of the sixth NMOS transistor; the source electrode of the tenth NMOS transistor is grounded, and the grid electrode of the tenth NMOS transistor is connected with a current control signal; the source electrode of the ninth PMOS transistor is connected with a power supply, the grid electrode of the ninth PMOS transistor is connected with a current control signal, and the drain electrode of the ninth PMOS transistor is connected with the source electrode of the sixth PMOS transistor; the grid electrode of the sixth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor, and the drain electrode of the sixth PMOS transistor is connected with the drain electrode of the eighth NMOS transistor and the output end of the crystal oscillator; the grid electrode of the eighth NMOS transistor is connected with the grid electrode of the seventh NMOS transistor, and the source electrode of the eighth NMOS transistor is connected with the drain electrode of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor is connected with a current control signal, and the source is grounded.

Preferably, the signal amplifying and shaping unit specifically includes:

the transistor comprises a seventh PMOS transistor, a ninth NMOS transistor, a Schmidt trigger and a counter, wherein the source electrode of the seventh PMOS transistor is connected with a power supply, the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the sixth PMOS transistor, and the drain electrode of the seventh PMOS transistor is connected with the input end of the Schmidt trigger and the drain electrode of the ninth NMOS transistor; the grid electrode of the ninth NMOS transistor is connected with the grid electrode of the eighth NMOS transistor, and the source electrode of the ninth NMOS transistor is grounded; the output end of the Schmitt trigger is connected with the input end of the counter, and the output end of the counter outputs a start-oscillation marking signal.

Preferably, the starting unit specifically includes:

a tenth PMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor, wherein the tenth PMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor are formed by three PMOS transistors connected in series,

the source electrode of the tenth PMOS transistor is connected with the power supply, the grid electrode of the tenth PMOS transistor is connected with the output end of the counter, and the drain electrode of the tenth PMOS transistor is connected with the grid electrode of the thirteenth NMOS transistor and the drain electrode of the twelfth NMOS transistor; the drain electrode of the thirteenth NMOS transistor is connected with the grid electrode of the first PMOS transistor, and the source electrode of the thirteenth NMOS transistor is grounded; the source of the twelfth NMOS transistor is grounded, and the grid of the twelfth NMOS transistor is connected with the grid of the first NMOS transistor.

The crystal oscillator driving circuit provided by the embodiment of the invention comprises: the bias current generating unit, the resistance unit and the current configurable amplifier unit; the bias current generating unit is respectively connected with the resistance unit and the current configurable amplifier unit and is used for providing working current for the resistance unit and the current configurable amplifier unit; the resistance unit is connected with the current configurable amplifier unit and used for establishing a direct-current working point for the current configurable amplifier unit; the current configurable amplifier unit is respectively connected with the input end and the output end of the crystal oscillator and used for amplifying working current under the control of a direct current working point so as to drive the crystal oscillator to start oscillation.

Drawings

FIG. 1 is a schematic diagram of a driving circuit of a crystal oscillator in the prior art;

fig. 2 is a schematic diagram of a driving circuit of a crystal oscillator according to an embodiment of the invention;

fig. 3 is a schematic diagram of a driving circuit of a crystal oscillator according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a driving circuit of a crystal oscillator according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Example one

Fig. 2 is a schematic structural diagram of a driving circuit of a crystal oscillator according to an embodiment of the present invention, which is suitable for providing an accurate clock for a digital circuit. As shown in fig. 2, the structure of the driving circuit of the crystal oscillator provided in this embodiment includes: a bias current generating unit 210, a resistance unit 220, and a current configurable amplifier unit 230; wherein,

a bias current generating unit 210 connected to the resistance unit 220 and the current configurable amplifier unit 230, respectively, for providing the resistance unit 220 and the current configurable amplifier unit 230 with operating currents;

the resistor unit 220 is connected to the current configurable amplifier unit 230, and is configured to establish a dc operating point for the current configurable amplifier unit 230; preferably, the resistor unit 220 may be formed of a MOS transistor, because the MOS transistor occupies a smaller area than a general resistor device, and the area occupied by the entire driving circuit can be saved.

And the current configurable amplifier unit 230 is respectively connected with the input end XIN and the output end XOUT of the crystal oscillator, and is used for amplifying the working current under the control of a direct-current working point so as to drive the crystal oscillator to start oscillation.

According to the technical scheme of the embodiment, the bias current generating unit is used for providing working current for the resistance unit and the current configurable amplifier unit; establishing a direct current working point for the current configurable amplifier unit through a resistance unit; the current configurable amplifier unit amplifies the working current under the control of the direct current working point to drive the crystal oscillator to start oscillation, so that the power consumption of the driving circuit is reduced.

Example two

Fig. 3 is a schematic structural diagram of a driving circuit of a crystal oscillator according to a second embodiment of the present invention, on the basis of the second embodiment, a signal amplifying and shaping unit 240 and a starting unit 250 are added in the present embodiment, and specifically, as shown in fig. 3, the driving circuit includes:

a bias current generating unit 210, a resistance unit 220, a current configurable amplifier unit 230, a signal amplifying and shaping unit 240 and a starting unit 250; wherein,

a bias current generating unit 210 connected to the resistance unit 220 and the current configurable amplifier unit 230, respectively, for providing the resistance unit 220 and the current configurable amplifier unit 230 with operating currents;

the resistor unit 220 is connected to the current configurable amplifier unit 230, and is configured to establish a dc operating point for the current configurable amplifier unit 230;

the current configurable amplifier unit 230 is respectively connected with the input end XIN and the output end XOUT of the crystal oscillator, and is used for amplifying the working current under the control of a direct-current working point so as to drive the crystal oscillator to start oscillation;

a signal amplifying and shaping unit 240, connected to the current configurable amplifier unit 230, for amplifying and shaping the signal at the input end XIN of the crystal oscillator, and outputting a crystal oscillator oscillation start flag signal OSC-READY;

and a start unit 250 respectively connected to the bias current generating unit 210 and the signal amplifying and shaping unit 240, and configured to control start of the bias current generating unit 210 under control of the oscillation start flag signal OSC-READY.

Preferably, as an implementation manner of the driving circuit, referring to fig. 4, the starting unit 250 specifically includes:

a tenth PMOS transistor P10, a twelfth NMOS transistor N12, and a thirteenth NMOS transistor N13, which are composed of three PMOS transistors connected in series, wherein,

a source electrode of the tenth PMOS transistor P10 is connected to the power supply VDD, a gate electrode thereof is connected to the output terminal of the COUNTER, and a drain electrode thereof is connected to a gate electrode of the thirteenth NMOS transistor N13 and a drain electrode of the twelfth NMOS transistor N12; the drain electrode of the thirteenth NMOS transistor N13 is connected with the gate electrode of the first PMOS transistor P1, and the source electrode is grounded; the source of the twelfth NMOS transistor N12 is grounded, and the gate is connected to the gate of the first NMOS transistor N1.

Exemplarily, the bias current generating unit 210 may specifically include:

a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a first resistor R, wherein:

the grid electrodes of the first PMOS transistor P1 and the second PMOS transistor P2 are connected, the source electrodes are connected with a power supply VDD to form a current mirror, and the drain electrode of the first PMOS transistor P1 is connected with the first end of the first resistor R and the grid electrode of the first NMOS transistor N1; the drain of the second PMOS transistor P2 is connected to the gate of the second PMOS transistor P2 and the drain of the second NMOS transistor N2; the gate of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1 and the second terminal of the first resistor R, and the source of the second NMOS transistor N2 and the source of the first NMOS transistor N1 are both grounded.

Illustratively, the resistance unit 220 may specifically include:

a third PMOS transistor P3, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5 composed of three NMOS transistors connected in series, wherein,

the gate of the third PMOS transistor P3 is connected to the gate of the second PMOS transistor P2, the source is connected to the power supply, and the drain is connected to the gate of the fifth NMOS transistor N5 and the drain and gate of the fourth NMOS transistor N4; the source of the fourth NMOS transistor N4 is connected to the drain and gate of the third NMOS transistor N3; the source of the third NMOS transistor N3 is grounded.

Exemplarily, the current configurable amplifier unit 230 may specifically include:

a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11, wherein,

the source electrode of the fourth PMOS transistor P4 is connected with a power supply, the grid electrode of the fourth PMOS transistor P4 is connected with the grid electrode of the third PMOS transistor P3 and the grid electrode of the fifth PMOS transistor P5, and the drain electrode of the fourth PMOS transistor P3578 is connected with the drain electrode of the sixth NMOS transistor N6, the drain electrode of the fifth NMOS transistor N5 and the output end XOUT of the crystal oscillator; the grid electrode of the sixth NMOS transistor N6 is connected with the source electrode of the fifth NMOS transistor N5 and the input end XIN of the crystal oscillator, and the source electrode is grounded; the source electrode of the eighth PMOS transistor P8 is connected with a power supply VDD, the grid electrode of the eighth PMOS transistor P8 is connected with a current control signal, and the drain electrode of the eighth PMOS transistor P3578 is connected with the source electrode of the fifth PMOS transistor P5; the drain electrode of the fifth PMOS transistor P5 is connected with the drain electrode of the seventh NMOS transistor N7 and the output end XOUT of the crystal oscillator; the source of the seventh NMOS transistor P7 is connected to the drain of the tenth NMOS transistor N10, and the gate is connected to the gate of the sixth NMOS transistor N6; the source of the tenth NMOS transistor N10 is grounded, and the gate is connected to a current control signal; the source electrode of the ninth PMOS transistor P9 is connected with a power supply VDD, the grid electrode of the ninth PMOS transistor P9 is connected with a current control signal, and the drain electrode of the ninth PMOS transistor P9 is connected with the source electrode of the sixth PMOS transistor P6; the gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5, and the drain is connected to the drain of the eighth NMOS transistor N8 and the output XOUT of the crystal oscillator; the gate of the eighth NMOS transistor N8 is connected to the gate of the seventh NMOS transistor N7, and the source is connected to the drain of the eleventh NMOS transistor N11; the gate of the eleventh NMOS transistor N11 is connected to the current control signal, and the source is grounded.

Illustratively, the signal amplifying and shaping unit 240 may specifically include:

a seventh PMOS transistor P7, a ninth NMOS transistor N9, a schmitt trigger T, and a COUNTER, wherein the seventh PMOS transistor P7 has a source connected to the power supply, a gate connected to the gate of the sixth PMOS transistor P6, and a drain connected to the input terminal of the schmitt trigger T and the drain of the ninth NMOS transistor N9; the gate of the ninth NMOS transistor N9 is connected to the gate of the eighth NMOS transistor N8, and the source is grounded; the output terminal of the schmitt trigger T is connected to the input terminal of the COUNTER, and the output terminal of the COUNTER outputs the oscillation start flag signal OSC-READY.

It should be noted that, since the bias current generating unit 210 has a degenerate operating point where the current is zero, in order to enable the driving circuit to operate normally at any time, the driving circuit further needs to include the starting unit 250 to help the bias current generating unit 210 establish a correct dc operating point. The operation process of the starting unit 250 is as follows: when the circuit is not activated, the gate voltage of the first NMOS transistor N1 is zero, the currents of the first PMOS transistor P1 and the second PMOS transistor P2 are zero, and the crystal oscillator oscillation start flag signal OSC-READY is low, so that the twelfth NMOS transistor N12 is turned off, the tenth PMOS transistor P10 is turned on, the gate node of the thirteenth NMOS transistor N13 is charged, the gate voltage of the thirteenth NMOS transistor N13 is raised, the thirteenth NMOS transistor N13 is turned on, the gate voltage of the second PMOS transistor P2 is lowered by the on-current, so that the second PMOS transistor P2 and the first PMOS transistor P1 are gradually turned on, and the gate voltage of the first NMOS transistor N1 is raised. After the circuit is started and stabilized, the gate voltage of the first NMOS transistor N1 makes the twelfth NMOS transistor N12 turn on, and since the tenth PMOS transistor P10 adopts a wider transistor with a lower turn-on capability than the twelfth NMOS transistor N12, the gate voltage of the thirteenth NMOS transistor N13 drops to near zero, and the thirteenth NMOS transistor N13 turns off. At this time, the twelfth NMOS transistor N12 and the tenth PMOS transistor P10 in the start unit 250 are both turned on, and this branch will consume a part of the current, but after the crystal oscillator starts oscillation stably, the oscillation start flag signal OSC-READY is set to high level, and the tenth PMOS transistor P10 is turned off, so that the start unit 250 does not consume the current after the crystal oscillator operates stably, thereby further reducing the power consumption of the entire driving circuit.

In the bias current generating unit 210, the first PMOS transistor P1 and the second PMOS transistor P2 are mirror current mirrors, assuming that the ratio of the width to length ratios of the second NMOS transistor N2 and the first NMOS transistor N1 isWhere K denotes a ratio of a width to a length of the second NMOS transistor N2 to a width to a length of the first NMOS transistor N1, and W, L denotes a channel width and a channel length of the transistors, respectively, the bias current generated by the bias current generating unit 210 is:

$I_B=\frac{2}{{\mathrm{\μ}}_n{C}_{ox}{\left(\frac{W}{L}\right)}_{N1}}\frac{1}{R^2}(1-\frac{1}{\sqrt{K}})$

wherein, I_BIndicating bias currents, W, L respectivelyDenotes a channel width and length of the first NMOS transistor N1, K denotes a ratio of a width to length ratio of the second NMOS transistor N2 to the first NMOS transistor N1, R denotes a resistance value of the first resistor R, μ_nDenotes the carrier mobility of the NMOS transistor, C_oxRepresenting the gate capacitance of the transistor per unit area. As can be seen, the bias current I_BThe size of the circuit is irrelevant to the power supply voltage VDD, so that the working current of the circuit does not change greatly along with the change of the power supply voltage VDD, correspondingly, a large margin is not reserved in the circuit design, and the power consumption of the circuit is further reduced.

The current configurable amplifier unit 230 includes a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8, which function as current sources, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6, and a tenth NMOS transistor N10, an eleventh NMOS transistor N11, an eighth PMOS transistor P8, and a ninth PMOS transistor P9, which function as switches. The gate of the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the eighth PMOS transistor P8, and the ninth PMOS transistor P9 is connected to the current control signal, which can be implemented by a programming procedure according to design requirements.

In the whole driving circuit, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the first PMOS transistor P1 and the second PMOS transistor P2 form a mirror current source to provide bias current for each unit. The fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 form a configurable current mirror to provide current for the amplifier. The current of the current configurable amplifier unit is adjusted by controlling the on and off of the tenth NMOS transistor N10, the eleventh NMOS transistor N11 and the eighth PMOS transistor P8, the ninth PMOS transistor P9. When the characteristics of the crystal oscillator are different, the sizes of the used off-chip matching capacitors are different, and the temperature and the process are changed, the required transconductance of the amplifier is also changed, so that the power consumption can be flexibly configured under various different conditions by using the current configurable amplifier unit, and the extremely low power consumption characteristic is achieved. Typically, the fifth PMOS crystal is used when the lowest power configuration is usedThe branch of the transistor P5 and the sixth PMOS transistor P6 is turned off, the current is zero, the sixth NMOS transistor N6 serves as an amplifier to drive the crystal oscillator, the sixth NMOS transistor N6 can be biased in the subthreshold region by designing the proper transistor size, and the relationship between the transconductance and the working current of the amplifier circuit isWherein n is a process-related parameter, typically 1-2, and I_DThe working current is k, the boltzmann constant is, T is absolute temperature, q is electronic charge, and kT/q is approximately equal to 26mV at normal temperature. Compared with the traditional transistor inverter amplifying circuit, the transistor amplifying circuit which works in the subthreshold region has higher current efficiency (can provide larger transconductance under a certain current) under a certain current by the bias, so that the low power consumption characteristic can be realized. The fifth NMOS transistor N5 operates in a linear region to form a resistor to establish a dc operating point for the sixth NMOS transistor N6, and the third NMOS transistor N3 and the fourth NMOS transistor N4 form a diode-connected transistor to provide a bias voltage for the fifth NMOS transistor N5. The third NMOS transistor N3 and the sixth NMOS transistor N6 are designed to be matched to have the same gate voltage, assuming that the ratio of the width-to-length ratio of the fourth NMOS transistor N4 to the fifth NMOS transistor N5 isThe on-resistance of the fifth NMOS transistor N5 isWherein W, L denotes the channel width and length of the NMOS transistor, respectively, K_rRepresents the ratio of the width to length, μ, of the fourth NMOS transistor N4 to the fifth NMOS transistor N5_nDenotes the carrier mobility of the NMOS transistor, C_oxRepresents the gate capacitance of the transistor per unit area, I_p3Represents the operating current of the third PMOS transistor P3; by adjusting the relevant parameters, an appropriate resistance value can be obtained. Typically, for a 32.768kHz crystal oscillator, feedback is generally required in order not to affect the circuit start-up characteristicsThe resistor RF is larger than 10M omega, and the area occupied by the feedback resistor can be greatly reduced by using the transistor resistor design, so that the area of the whole drive circuit is reduced.

When the driving circuit works stably, the input end XIN and the input end XOUT of the crystal oscillator generate sinusoidal oscillation signals, but the amplitudes are small. In the signal amplifying and shaping unit 240, the ninth NMOS transistor N9 amplifies the signal at the input XIN of the crystal oscillator, and obtains the final square wave output signal OSC-OUT through the schmitt trigger T shaping, and then outputs the crystal oscillator oscillation start flag signal OSC-READY through the COUNTER setting.

According to the technical scheme of the embodiment, the bias current generating unit is used for providing working current for the resistance unit and the current configurable amplifier unit; establishing a direct current working point for the current configurable amplifier unit through a resistance unit; the current configurable amplifier unit amplifies the working current under the control of the direct current working point to drive the crystal oscillator to start oscillation, so that the power consumption of the driving circuit is reduced.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (8)

1. A crystal oscillator drive circuit, comprising: the bias current generating unit, the resistance unit and the current configurable amplifier unit; wherein,

the bias current generating unit is respectively connected with the resistance unit and the current configurable amplifier unit and is used for providing working current for the resistance unit and the current configurable amplifier unit;

the resistance unit is connected with the current configurable amplifier unit and used for establishing a direct-current working point for the current configurable amplifier unit;

and the current configurable amplifier unit is respectively connected with the input end and the output end of the crystal oscillator and is used for amplifying the working current under the control of a direct current working point so as to drive the crystal oscillator to start oscillation.

2. The circuit of claim 1, further comprising: and the signal amplifying and shaping unit is connected with the current configurable amplifier unit and is used for amplifying and shaping the signal at the input end of the crystal oscillator and outputting a start oscillation mark signal of the crystal oscillator.

3. The circuit of claim 2, further comprising: and the starting unit is respectively connected with the bias current generating unit and the signal amplifying and shaping unit and is used for controlling the starting of the bias current generating unit under the control of the starting vibration mark signal.

4. The circuit according to claim 3, wherein the bias current generating unit specifically comprises:

a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor, wherein:

the grid electrodes of the first PMOS transistor and the second PMOS transistor are connected, the source electrode of the first PMOS transistor is connected with the power supply to form a current mirror, and the drain electrode of the first PMOS transistor is connected with the first end of the first resistor and the grid electrode of the first NMOS transistor; the drain electrode of the second PMOS transistor is connected with the grid electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor; the grid electrode of the second NMOS transistor is connected with the drain electrode of the first NMOS transistor and the second end of the first resistor, and the source electrode of the second NMOS transistor and the source electrode of the first NMOS transistor are both grounded.

5. The circuit according to claim 4, wherein the resistance unit comprises in particular:

a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor composed of three NMOS transistors connected in series, wherein,

the grid electrode of the third PMOS transistor is connected with the grid electrode of the second PMOS transistor, the source electrode of the third PMOS transistor is connected with the power supply, and the drain electrode of the third PMOS transistor is connected with the grid electrode of the fifth NMOS transistor and the drain electrode and the grid electrode of the fourth NMOS transistor; the source electrode of the fourth NMOS transistor is connected with the drain electrode and the grid electrode of the third NMOS transistor; the source of the third NMOS transistor is grounded.

6. The circuit according to claim 5, wherein the current configurable amplifier unit comprises:

a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor, wherein,

the source electrode of the fourth PMOS transistor is connected with the power supply, the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor and the grid electrode of the fifth PMOS transistor, and the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the sixth NMOS transistor, the drain electrode of the fifth NMOS transistor and the output end of the crystal oscillator; the grid electrode of the sixth NMOS transistor is connected with the source electrode of the fifth NMOS transistor and the input end of the crystal oscillator, and the source electrode is grounded; the source electrode of the eighth PMOS transistor is connected with the power supply, the grid electrode of the eighth PMOS transistor is connected with the current control signal, and the drain electrode of the eighth PMOS transistor is connected with the source electrode of the fifth PMOS transistor; the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the seventh NMOS transistor and the output end of the crystal oscillator; the source electrode of the seventh NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, and the grid electrode of the seventh NMOS transistor is connected with the grid electrode of the sixth NMOS transistor; the source electrode of the tenth NMOS transistor is grounded, and the grid electrode of the tenth NMOS transistor is connected with a current control signal; the source electrode of the ninth PMOS transistor is connected with a power supply, the grid electrode of the ninth PMOS transistor is connected with a current control signal, and the drain electrode of the ninth PMOS transistor is connected with the source electrode of the sixth PMOS transistor; the grid electrode of the sixth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor, and the drain electrode of the sixth PMOS transistor is connected with the drain electrode of the eighth NMOS transistor and the output end of the crystal oscillator; the grid electrode of the eighth NMOS transistor is connected with the grid electrode of the seventh NMOS transistor, and the source electrode of the eighth NMOS transistor is connected with the drain electrode of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor is connected with a current control signal, and the source is grounded.

7. The circuit according to claim 6, wherein the signal amplifying and shaping unit comprises:

the transistor comprises a seventh PMOS transistor, a ninth NMOS transistor, a Schmidt trigger and a counter, wherein the source electrode of the seventh PMOS transistor is connected with a power supply, the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the sixth PMOS transistor, and the drain electrode of the seventh PMOS transistor is connected with the input end of the Schmidt trigger and the drain electrode of the ninth NMOS transistor; the grid electrode of the ninth NMOS transistor is connected with the grid electrode of the eighth NMOS transistor, and the source electrode of the ninth NMOS transistor is grounded; the output end of the Schmitt trigger is connected with the input end of the counter, and the output end of the counter outputs a start-oscillation marking signal.

8. The circuit according to claim 7, wherein the start-up unit comprises in particular:

a tenth PMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor, wherein the tenth PMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor are formed by three PMOS transistors connected in series,

the source electrode of the tenth PMOS transistor is connected with the power supply, the grid electrode of the tenth PMOS transistor is connected with the output end of the counter, and the drain electrode of the tenth PMOS transistor is connected with the grid electrode of the thirteenth NMOS transistor and the drain electrode of the twelfth NMOS transistor; the drain electrode of the thirteenth NMOS transistor is connected with the grid electrode of the first PMOS transistor, and the source electrode of the thirteenth NMOS transistor is grounded; the source of the twelfth NMOS transistor is grounded, and the grid of the twelfth NMOS transistor is connected with the grid of the first NMOS transistor.