CN106098698A - Array base palte and preparation method thereof, display device - Google Patents

Abstract

The invention provides a kind of array base palte and preparation method thereof, display device, wherein, in gate driver circuit scattering device region between adjacent rows sub-pixel unit.In this manner it is possible to the side edge at array base palte does not makes gate driver circuit so that corresponding region as viewing area, thus can also reduce the width of the frame region of array base palte further.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

In order to achieve a narrower frame of the display device, a GOA (Gate Driver On Array, gate driver circuit fabricated on an array substrate) design has been proposed in the prior art. Referring to Fig. 1, in the prior art, the gate drive circuit (including multiple GOA units) is generally fabricated on the two sides of the array substrate through a patterning process, and besides the GOA units, the side is also provided for The driving signal line CLK for driving the gate driving circuit is located on both sides of the display area (a plurality of sub-pixel arrays are formed in the display area; wherein the sub-pixels are represented as P; it also includes a plurality of data lines Data, a plurality of gate lines Gate, Wherein the nth gate line is represented as Gaten).

The main structure of the gate driving circuit is generally made of opaque materials such as metal, so in the prior art, the side is generally not used as a display area to emit light. Since the gate driving circuit needs to occupy a certain space, the corresponding display device still has the problem of a wide frame.

Contents of the invention

One object of the present invention is to reduce the frame width of a display device.

In a first aspect, the present invention provides an array substrate, including: a substrate and a sub-pixel unit array formed on the substrate, a gate line for providing scan pulses for the sub-pixel unit array, and a grid line for providing data for the sub-pixel unit array. Voltage data lines, gate drive circuits for providing scan pulses to the gate lines, and drive signal lines for driving the gate drive circuits; wherein,

The gate drive circuits are distributed in multiple first non-opening regions, and the parts distributed in the first non-opening area are electrically connected to each other through connection lines extending along the direction of the data lines;

Wherein, the first non-opening area is an area between two adjacent rows of sub-pixel units.

Further, the gate drive circuit includes multiple sets of shift register units, the multiple sets of shift register units are scattered in multiple first non-opening areas, and each set of shift register units is only set in the same In the first non-aperture area; each group of shift register units is used to output at least one scan pulse in one frame.

Further, each group of shift register units is connected to N gate lines closest to the group of shift register units through connection lines; where N is the number of scan pulses output by a group of shift register units in one frame.

Further, the gate line connected to the row of sub-pixel units on the first side of the two rows of sub-pixel units located on both sides of the first non-opening region where the gate drive circuit is located is located on the second row of sub-pixel units on the first side of the row of sub-pixel units. In a non-opening area, the gate lines connected to a row of sub-pixel units on the second side are located in the first non-opening area on the second side of the row of sub-pixel units.

Further, in every two adjacent first non-opening regions, one of the first non-opening regions is provided with two gate lines, and each gate line is connected to a row of sub-pixel units close to the gate line; the other first non-opening region A group of shift register units is arranged in a non-opening area; each group of shift register units is used to output two scan pulses in one frame.

Further, the gate drive circuit and the sub-pixel unit array include a plurality of thin film transistors; the gates of the plurality of thin film transistors are located on the side of the active layer away from the substrate; the array substrate also includes a The side of the layer away from the gate is used to shield the light-shielding pattern of the channel region of the thin film transistor;

The driving signal line and the light-shielding pattern are formed in the same layer.

Further, the light-shielding pattern is electrically connected to the driving signal line.

Further, the light-shielding pattern is suitable for being multiplexed as a touch electrode pattern.

In a second aspect, the present invention provides a method for manufacturing an array substrate, including: a sub-pixel unit array formed on a substrate, a grid line for providing a scan pulse for the sub-pixel unit array, and a grid line for providing a sub-pixel unit array. Data lines for data voltages, gate drive circuits for providing scan pulses to the gate lines, and drive signal lines for driving the gate drive circuits; wherein,

The gate drive circuits are distributed in multiple first non-opening regions, and the parts distributed in the first non-opening area are electrically connected to each other through connection lines extending along the direction of the data lines;

Wherein, the first non-opening area is an area between two adjacent rows of sub-pixel units.

In a third aspect, the present invention provides a display device, comprising the array substrate described in any one of the above.

In the array substrate provided by the present invention, the gate driving circuits are dispersedly arranged in the area between two adjacent rows of sub-pixel units. In this way, it is not necessary to manufacture the gate driving circuit at the side of the array substrate, so that the corresponding area can also be used as a display area, so that the width of the frame area of the array substrate can be further reduced.

Description of drawings

The characteristic information and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way, in the accompanying drawings:

FIG. 1 is a schematic structural diagram of an array substrate in the prior art;

FIG. 2 is a schematic structural diagram of a partial structure of an array substrate provided by an embodiment of the present invention;

FIG. 3a and FIG. 3b are structural schematic diagrams of some structures in an array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a manufacturing process of an array substrate provided by the present invention.

detailed description

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

The first aspect of the present invention provides an array substrate, including a substrate, a sub-pixel unit array formed on the substrate, a gate line for providing a scan pulse for the sub-pixel unit array, and a data voltage for providing the sub-pixel unit array. data lines, a gate drive circuit for providing scan pulses to the gate lines, and a drive signal line for driving the gate drive circuit; wherein,

The gate drive circuits are distributed in multiple first non-opening regions, and the parts distributed in the first non-opening area are electrically connected to each other through connection lines extending along the direction of the data lines;

Wherein, the first non-opening area is an area between two adjacent rows of sub-pixel units. .

In the array substrate provided by the present invention, the gate driving circuits are dispersedly arranged in the area between two adjacent rows of sub-pixel units. In this way, it is not necessary to manufacture the gate driving circuit at the side of the array substrate, so that the corresponding area can also be used as a display area, so that the width of the frame area of the array substrate can be further reduced. In addition, because it is an area arranged between two adjacent rows of sub-pixel units, this part of the area usually corresponds to the position of the black matrix, so it will not have a great impact on the aperture ratio of the sub-pixel units.

Some specific embodiments of the above-mentioned array substrate will be described in detail below with reference to the accompanying drawings. Referring to FIG. 2 , it shows a schematic structural view of a partial structure of an embodiment of an array element; wherein the gate drive circuit GOA includes a plurality of dispersed shift register units (represented as GOA units in the figure), and each GOA The units are connected into an integral gate drive circuit GOA through connection lines (connection lines are not shown in the figure); each GOA unit is arranged in the area between two adjacent rows of sub-pixel units P (for ease of description, Hereinafter referred to as the first non-aperture area) for outputting scan pulses. In this way, there is no need to set GOA on both sides of the display area A, so that the border area can be designed to be smaller or no border area is set at all, so that narrower borders can be realized.

In specific implementation, under the premise that the gate drive circuit GOA is scattered in the area between two adjacent rows of sub-pixel units P, no matter how the gate drive circuit GOA is split, it will not affect the present invention. scope of protection. In the embodiment shown in FIG. 2 , dividing the GOA into multiple GOA units and distributing them is only an optional implementation manner. Since a GOA unit is a relatively complete basic functional unit capable of outputting one or more scan pulses, such an arrangement can make the design and fabrication of the array substrate less difficult and facilitate subsequent control.

It can be seen from the above description that, in actual implementation, on the premise that the gate drive circuit GOA is distributed in the area between two adjacent rows of sub-pixel units P, regardless of the connecting wires and The position of the driving signal line driven by the driving circuit (such as a clock signal line, etc., denoted as CLK here) will not affect the scope of protection of the present invention. Figure 2 shows an arrangement of connection lines and drive signal lines CLK, the connection lines and drive signal lines CLK are arranged in the area between two adjacent columns of sub-pixel units P (for the convenience of expression, two adjacent columns The area between the columns of sub-pixel units P is defined as the second non-aperture area). In this way, since neither the connection line nor the driving signal line CLK is arranged in the frame area, the width of the frame area can be further reduced. Of course, in a specific application, both the connecting line and the driving signal line CLK can be arranged in the frame area, or only the connecting line or the driving signal line CLK is arranged in the frame area.

Generally, one gate line is arranged in each first non-opening area. However, in the process of realizing the present invention, the inventor found that, in the case of setting a part of the GOA circuit in the first non-opening area, if the gate line is also set in the first non-opening area where the GOA circuit is located, then the comparison It is difficult to make a reasonable layout, and it is difficult to make. On this basis, the embodiment of the present invention also provides another optional design method. Referring to FIG. 2, for a GOA unit, the gate line connected to the sub-pixel unit P in the row above it is located in the row of sub-pixels In the first non-opening area above the unit P, the gate line connected to a row of sub-pixel units P below it is located in the first non-opening area below the row of sub-pixel units P. In this way, by arranging the gate lines and the GOA units in different first non-opening regions, the above problems can be well overcome. Of course, in specific implementation, as an alternative way, it is also possible to set gate lines in the first non-opening area of the partial structure of the GOA circuit. Such a technical solution can also achieve the basic purpose of the present invention, and also Should fall into the protection scope of the present invention.

In the case of setting the gate lines and GOA units in different first non-aperture areas in the above manner, each GOA unit can be further used to output two scan pulses, and every two adjacent In a non-opening area, a first non-opening area is provided with two gate lines, and each gate line is connected to a row of sub-pixel units P close to the gate line; another first non-opening area is provided with a group of shifting Register unit; each set of shift register units is used to output two scan pulses. In this way, the scanning requirements for sub-pixel units P of all rows can be met, and compared with the case where one GOA unit is set to output multiple scan pulses, the area of each GOA unit can be smaller, thereby reducing the first non-aperture The width of the area, to avoid the display brightness at the corresponding position being obviously dark.

In a specific implementation, the gate driving circuit here generally includes a plurality of thin film transistors, and similarly, the sub-pixel unit array generally also includes a plurality of thin film transistors. During specific fabrication, each thin film transistor included in the above-mentioned gate driving circuit can be formed through the same process as the plurality of thin film transistors included in the sub-pixel unit array, which can reduce manufacturing difficulty. In addition, in specific implementation, the structures of various thin film transistors may be different. For the case where the gate of the thin film transistor is located on the side of the active layer away from the substrate, the embodiment of the present invention also provides an optional arrangement, see Figure 3a (Figure 3a is a structure located at the thin film transistor of the GOA unit Schematic diagram) and FIG. 3b (FIG. 3b is a schematic structural diagram of the thin film transistor in the sub-pixel array), a light-shielding pattern LS is set on the side of the active layer PL away from the gate Gate; the light-shielding pattern LS is on the same layer as the driving signal line CLK formed to shield the channel region of the thin film transistor. The advantage of this setting is that it can prevent the active layer from being affected by the light from the side away from the gate (the bottom in the figure), and because it is formed on the same layer as the driving signal line CLK, it reduces the difficulty of manufacturing and layout.

Furthermore, the light-shielding pattern LS here can be electrically connected to the driving signal line, which can reduce the resistance of the signal when it is transmitted on the driving signal line CLK; and/or, further, the light-shielding pattern here can also be multiplexed as a touch control electrode graphics. In this way, separate fabrication of corresponding touch electrode patterns can be avoided, and the thickness and fabrication difficulty of the display device can be reduced.

In specific implementation, the electrical connection here may refer to the direct connection between the light-shielding pattern LS (the light-shielding pattern here is a conductive pattern) and the driving signal line CLK, or it may also mean that the light-shielding pattern LS is connected to the driving signal line through other conductive structures. CLK is indirectly connected. The shading pattern here can be reused as a touch electrode pattern, which means that the design of the shading pattern LS here can be used as a touch electrode pattern. For example, the shading pattern can be made into a plurality of block electrodes distributed in an array. Each electrode It can be used as a touch electrode pattern to realize a touch detection function.

During specific implementation, the light-shielding pattern mentioned in any of the above items can be made of Ti/Al or the like.

In a specific implementation, in addition to the structure described above, the array substrate in ADS mode may also include a base GL, a plurality of interlayer dielectric layers ILD1, ILD2 and ILD3, an active layer PL, Other structures such as the source-drain electrode pattern SD and the common electrode (not shown in the figure) will not be described one by one here. In addition, during specific implementation, the above connection lines and the driving signal line CLK may be connected to various parts of the gate driving circuit GOA through via holes. According to the description of the present disclosure, those skilled in the art can think of various ways to design the connection lines and the driving signal lines CLK and GOA, and the present invention will not be described in detail here.

It is not difficult to understand that during specific implementation, the various optional configurations described here can be combined arbitrarily, and the corresponding technical solutions will not affect the implementation of the present invention.

Another aspect of the present invention also provides a method for manufacturing an array substrate, which can be used to manufacture the above-mentioned array substrate, and the method may include:

A sub-pixel unit array formed on the substrate, a gate line for providing a scan pulse for the sub-pixel unit array, a data line for providing a data voltage for the sub-pixel unit array, and a gate driver for providing a scan pulse for the gate line circuit and a driving signal line for driving the gate driving circuit; wherein,

The gate drive circuits are distributed in multiple first non-opening regions, and the parts distributed in the first non-opening area are electrically connected to each other through connection lines extending along the direction of the data lines;

Wherein, the first non-opening area is an area between two adjacent rows of sub-pixel units.

It is not difficult to understand that, during specific implementation, those skilled in the art may think of different implementations of the above-mentioned fabrication method to fabricate any of the above-mentioned array substrates. The process of manufacturing the array substrate shown in FIG. 2 and FIG. 3 will be exemplarily described below. Referring to Figure 4, the method includes:

Step S1 , forming a shielding pattern LS and a driving signal line CLK on the substrate GL through a patterning process; the position of the shielding pattern LS here should be able to cover the part of the channel region in the active layer formed on the substrate later.

Step S2, forming a first interlayer dielectric layer ILD1 above the shielding pattern LS; the interlayer dielectric layer ILD here mainly plays the role of insulation and separates the shielding pattern LS from the active layer PL.

Step S3, fabricating the active layer PL through a patterning process;

Step S4, fabricating the second interlayer dielectric layer ILD2.

In step S5, the gate layer Gate is fabricated through a patterning process.

Step S6, fabricating the third interlayer dielectric layer ILD3.

In step S7, the source-drain electrode layer SD is fabricated through a patterning process.

So far, the structures shown in Fig. 3a and Fig. 3b can be obtained.

Step S8, making a resin layer.

In step S9, a pixel electrode is fabricated through a patterning process.

Step S10, making a passivation layer.

Step S11 , fabricating a common electrode layer through a patterning process.

The structures formed in step S8-step S11 are not shown in Fig. 3a and Fig. 3b.

How to implement the above-mentioned steps can refer to the process in the prior art, and the present invention will not describe it in detail here.

In a third aspect, the present invention further provides a display device, comprising the array substrate described in any one of the above.

During specific implementation, the display device here can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (11)

1. An array substrate, comprising: the pixel driving circuit comprises a substrate, a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on the substrate; wherein,

the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;

the first non-opening area is an area between two adjacent rows of sub-pixel units.

2. The array substrate of claim 1, wherein each driving signal line and/or connecting line is disposed in the second non-opening region; the second non-opening area is an area between two adjacent columns of sub-pixel units.

3. The array substrate of claim 1, wherein the gate driving circuit comprises a plurality of groups of shift register units, the groups of shift register units are dispersedly disposed in a plurality of first non-opening areas, and each group of shift register units is disposed in only one same first non-opening area; each group of shift register units is used for outputting at least one scanning pulse in one frame.

4. The array substrate of claim 3, wherein each group of shift register units is connected to the N gate lines nearest to the group of shift register units through the connecting lines; wherein, N is the number of the scanning pulses output by a group of shift register units in one frame.

5. The array substrate of claim 1, wherein the gate line connected to the sub-pixel unit in the first side of the two rows of sub-pixel units on two sides of the first non-opening area where the gate driving circuit is located in the first non-opening area on the first side of the row of sub-pixel units, and the gate line connected to the sub-pixel unit in the second side of the row of sub-pixel units is located in the first non-opening area on the second side of the row of sub-pixel units.

6. The array substrate of claim 5,

in every two adjacent first non-opening areas, two grid lines are arranged in one first non-opening area, and each grid line is connected with a row of sub-pixel units close to the grid line; a group of shift register units are arranged in the other first non-opening area; each group of shift register units is used for outputting two scanning pulses in one frame.

7. The array substrate of claim 1, wherein the gate driving circuit and the array of sub-pixel units comprise a plurality of thin film transistors; the grid electrodes of the thin film transistors are positioned on one side of the active layer, which is far away from the substrate; the array substrate further comprises a light shielding pattern which is arranged on one side of the active layer, which is far away from the grid electrode, and is used for shielding a channel region of the thin film transistor;

the driving signal line and the light-shielding pattern are formed in the same layer.

8. The array substrate of claim 7, wherein the light-shielding pattern is electrically connected to the driving signal line.

9. The array substrate of claim 7, wherein the light-shielding pattern is suitable for multiplexing as a touch electrode.

10. A method for manufacturing an array substrate comprises the following steps: the pixel driving circuit comprises a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on a substrate; wherein,

the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;

the first non-opening area is an area between two adjacent rows of sub-pixel units.

11. A display device comprising the array substrate according to any one of claims 1 to 9.