CN106062957A - Method of fabricating a charge-trapping gate stack using a CMOS process flow - Google Patents
Method of fabricating a charge-trapping gate stack using a CMOS process flow Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 139
- 230000008569 process Effects 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 230000005641 tunneling Effects 0.000 claims abstract description 38
- 230000003647 oxidation Effects 0.000 claims abstract description 35
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 35
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 238000000059 patterning Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000011435 rock Substances 0.000 claims description 70
- 239000000203 mixture Substances 0.000 claims description 32
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 28
- 239000001301 oxygen Substances 0.000 claims description 28
- 229910052760 oxygen Inorganic materials 0.000 claims description 28
- 230000001590 oxidative effect Effects 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 230000005611 electricity Effects 0.000 claims description 10
- 238000011065 in-situ storage Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 210
- 229910052710 silicon Inorganic materials 0.000 description 47
- 239000010703 silicon Substances 0.000 description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 46
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 27
- 229910052581 Si3N4 Inorganic materials 0.000 description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- 239000007789 gas Substances 0.000 description 16
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 12
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 8
- 229910052735 hafnium Inorganic materials 0.000 description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 240000002853 Nelumbo nucifera Species 0.000 description 6
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 6
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000001272 nitrous oxide Substances 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 150000003254 radicals Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000002485 combustion reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000007800 oxidant agent Substances 0.000 description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical group [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000002927 oxygen compounds Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- DUFGEJIQSSMEIU-UHFFFAOYSA-N [N].[Si]=O Chemical compound [N].[Si]=O DUFGEJIQSSMEIU-UHFFFAOYSA-N 0.000 description 1
- YIMRKFDMAYRUSJ-UHFFFAOYSA-N [Si].Cl[SiH2]Cl Chemical compound [Si].Cl[SiH2]Cl YIMRKFDMAYRUSJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002516 radical scavenger Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
Description
Cross-Reference to Related Applications
According to 35U.S.C.119 (e), the application requires that the U.S. Patent Application Serial Number in JIUYUE in 2014 submission on the 18th is
The benefit of priority of the temporary patent application serial number 61/936,549 that on February 6th, 14/490,514 and 2014 submits to, it passes through
Quote and be integrally incorporated herein with it.
Technical field
The disclosure relates generally to the field of semiconductor device, and relates more particularly to whole for charge-trapping gate stack
The method closing CMOS flow.
Background
When including logical device and interface circuit based on mos field effect transistor (MOSFET)
When integrated circuit generally uses complementary metal oxide semiconductors (CMOS) (CMOS) technological process of standard to manufacture, relate to conducting electricity, partly
The formation with dielectric substance of conductor and patterning.In such cmos process flow use these materials combination with
And the combination of reagent treatment and concentration and temperature are strict controls for each operation, to guarantee that obtained MOSFET will
Properly functioning.Many is applied, it is desirable to including nonvolatile memory device based on FET, this FET includes integrated electricity
Charge-trapping gate stack in road.The formation of charge-trapping gate stack relates to being sandwiched in two electrolytes or oxide layer is (usual
Be referred to as ONO stacking) between nitride or the formation of nitrogen oxides electric charge capture layer.For manufacturing traditional skill of ONO stacking
Art uses those materials with the cmos process flow of standard and the visibly different material of technique and technique, and it can be unfavorable
Ground affects manufacturing or being negatively affected by the manufacture of MOSFET of MOSFET.Especially, formed MOSFET gate oxide or
Electrolyte can significantly reduce, by changing top oxide or the thickness of barrier oxide or composition, the ONO heap formed before
Folded performance.
General introduction
Describe the method manufacturing the circuit including memory device and logical device.In one embodiment, method includes
Forming dielectric stack on the surface of the substrate, this dielectric stack includes Tunneling dielectric and overlies the electricity of Tunneling dielectric
Lotus trapping layer.First cover including oxide is deposited on dielectric stack, and includes the second cap rock of nitride
It is formed on first cover.First cover and the second cap rock and dielectric stack are patterned to form memory device
Gate stack.Remove the second cap rock, and perform oxidizing process to form barrier oxide on electric charge capture layer, at it
In, oxidizing process consumes first cover.
Accompanying drawing is sketched
Embodiments of the invention are by from detailed description below and from the accompanying drawing provided below and claims
In be more fully understood, wherein:
Fig. 1 is to illustrate that manufacture includes mos field effect transistor (MOSFET) and has charge-trapping grid
The flow chart of the embodiment of the method for the integrated circuit (IC) of nonvolatile memory (NVM) device of stacks；
Fig. 2 A-2Q is the block diagram of the cross-sectional view of the part illustrating IC during it manufactures according to the method for Fig. 1, its
In, first cover includes the oxide of deposition；
Fig. 3 A-3C shows IC at it according to the block diagram of the cross-sectional view of the part during the manufacture of the method for Fig. 1,
Wherein, first cover includes nitride；
Fig. 4 A-4F is the method illustrating the IC manufacturing the NVM device including MOSFET and have charge-trapping gate stack
The block diagram of another embodiment, wherein, first cover includes the oxide of growth；
Fig. 5 is be shown with having for growth of oxygen compound first cover and cvd nitride thing or nitrogen oxides single
The cluster tool (cluster tool) of settling chamber manufactures the NVM device including MOSFET He having charge-trapping gate stack
The flow chart of another embodiment of method of IC；And
Fig. 6 A and 6B is to illustrate to include MOSFET and on-plane surface, many according to what one of them that embodiment of the disclosure manufactured
The block diagram of the IC of the NVM device of grid.
Describe in detail
The disclosure is generally directed to be incorporated into the memory device including charge-trapping gate stack the side of cmos process flow
Method.
In the following description, many details of the most concrete configuration, compositions and technique etc. are set forth carrying
Thorough understanding for the present invention.In other instances, known technique and manufacturing technology describe in detail the most especially, with will not
Obscure the present invention necessarily.Moreover, it should be appreciated that the various embodiments shown in accompanying drawing are illustrative expressions and unnecessary
Drawn to scale.
As the term is employed herein " ... above (above) ", " ... on (over) ", " ... between
(between) " and " ... upper (on) " refer to the layer relative position relative to other layers.Deposit or be arranged in another layer
One layer of above or below can directly contact with other layer maybe can have one or more intermediate layer.Additionally, deposition or
It is arranged in a layer of interlayer directly to contact with these layers and maybe can have one or more intermediate layer.On the contrary, the second layer
On " " ground floor contact with this second layer.
Describe in detail referring now to Fig. 1 and Fig. 2 A to 2Q and include that metal oxide semiconductor field-effect is brilliant for integration
Body pipe (MOSFET) and include the embodiment of method of circuit of nonvolatile memory device of charge-trapping gate stack.Figure
1 is to illustrate that manufacture includes mos field effect transistor (MOSFET) and has the non-of charge-trapping gate stack
The flow chart of the embodiment of the method for the integrated circuit (IC) of volatile memory (NVM) device.Fig. 2 A-2Q is to illustrate that IC is at it
The block diagram of the cross-sectional view of the part during method manufacture according to Fig. 1.
With reference to Fig. 1 and Fig. 2 A, technique starts from being formed the ditch for memory device in the first area 204 of substrate 206
Road 202 and being formed for the raceway groove 208 (step 102) of one or more MOS device in the second area 210 of this substrate.Base
The body wafer that the end 206 can be made up of any monocrystal material being suitable for semiconductor device manufacture, or can include being formed
Top epitaxial layer at suprabasil applicable material.The material being suitable for includes, but not limited to silicon, germanium, silicon-germanium or iii-v
Compound semiconductor materials.
Usually, raceway groove 202,208 is by the pad oxide 211 in first area 204 and second area 210
The injection of suitable ionic species and formed.Such as, BF2 can at the energy of kiloelectron-volt (keV) from about 5 to about 100 and
From about lel4cm-2To about lel6cm-2Dosage at be injected into, to form N-type nonvolatile memory device.P-type device is permissible
Formed with any suitable dosage and the injection of energy again by arsenic or phosphonium ion.It should be understood that injection can be used
, simultaneously or in the different time in two regions of substrate 206, to use the standard of the photoresist oxidant layer including patterning
Photoetching technique form raceway groove 202,208 with in this region of mask.Pad oxide 211 is to have from about 10 nanometers
(nm) is to the silicon dioxide (SiO2) of about 20nm thickness, it is possible to by thermal oxidation process or in position steam generate (ISSG) and come
Growth.
In certain embodiments, it is all as indicated, isolation structure 212 can be formed in substrate 206 with by first area
The memory device formed in 204 electrically insulates with the MOS device of formation in second area 210.Isolation structure 212 is to be formed
Formed before pad oxide 211 and raceway groove 202,208, and any conventional art can be passed through, such as, but be not limited to shallow ridges
Groove is isolated (STI) or local oxidation of silicon (LOCOS) and is formed.
It follows that with reference to Fig. 1 and Fig. 2 B, the mask layer 215 of patterning is or to overlie liner in pad oxide 211
Oxide 211 is formed, and this pad oxide is etched or patterns, to remove from the first area 204 of substrate 206
Oxide (step 104).The mask layer 215 of patterning can include the photoresist of the photoetching technique patterning of use standard
Layer, and pad oxide 211 can use wet type or dry etch process to be etched or go divided by stopping at substrate 206
On surface.In one exemplary embodiment, pad oxide 211 is to use to comprise surfactant in wet cleaning processes
10:1 buffer oxide etch (BOE) be removed.Alternatively, wet cleaning processes can use 20:1BOE wet type to lose
Quarter, the etching of 50:1 Fluohydric acid. (HF) Wet-type etching, liner or any other like Wet-type etching chemistry based on Fluohydric acid. come
Perform.
With reference to Fig. 1 and Fig. 2 C, dielectric stack 214 is formed, its start from the first area 204 of substrate 206
Tunneling dielectric 216 (step 106) is formed at least one raceway groove 202 of memory device.Tunneling dielectric 216 can be to appoint
What material, and have and be adapted to allow for electric charge carrier tunnelling under the grid bias applied and enter electric charge capture layer, simultaneously
When memory device no-bias, seepage is kept any thickness of the barrier being suitable for.In certain embodiments, Tunneling dielectric 216
Silicon dioxide, silicon oxynitride or combinations thereof, and can pass through thermal oxidation process, situ steam generate (ISSG) or from
By base oxidation growth.
Such as, in one embodiment, silicon dioxide Tunneling dielectric 216 can grow in free-radical oxidation technique,
This free-radical oxidation technique relates to making hydrogen (H2) gas and oxygen (O2) gas flows into process chamber with the speed of mutually about 1:1, and do not have
Combustion incident, the formation of such as plasma, it generally will be otherwise used for H2And O2Carry out being pyrolyzed to form steam.
On the contrary, H2And O2It is allowed in about temperature in the range of 900 DEG C to 1000 DEG C with about pressure in the range of 0.5 to 5 torr
Power carries out reacting to be formed on the surface of the substrate free radical, such as OH base, HO2Base or O-double-basis.Free-radical oxidation process is by reality
Execute the persistent period about in the range of 1 to 10 minute, to be realized by the oxidation of the exposed surface of substrate and consumption having
Growth from about 1.5 nanometers (nm) to the Tunneling dielectric 216 of about 3.0nm thickness.It will be understood that at this and subsequently
In accompanying drawing, for the sake of clarity, relative to liner oxide 211, exaggerating the thickness of Tunneling dielectric 216, it is about 7 times
Thick.Even if the Tunneling dielectric 216 of growth is that both ratio had passed through wet oxidation at the thickness reduced during free-radical oxidation
The Tunneling dielectric of technology formation is the finest and close to be made up of substantially less than this Tunneling dielectric hydrogen atom/cubic centimetre again.
In certain embodiments, free-radical oxidation process is to carry out, to carry in the batch processing room that can process multiple substrate or stove
For the Tunneling dielectric 216 of high-quality, without affecting the requirement of the handling capacity (brilliant tablets h) that manufacturing facility may need.
In another embodiment, tunnel dielectric layer 216 is sunk by chemical gaseous phase deposition (CVD) or ald
Long-pending, and by including, but are not limited to silicon dioxide, silicon oxynitride, silicon nitride, aluminum, hafnium oxide, zirconium oxide, hafnium silicate, silicic acid
The dielectric layer composition of zirconium, hafnium oxy-nitride, hafnium Zirconium oxide and lanthana.In another embodiment, Tunneling dielectric 216
It is to include such as, but is not limited to, the bottom of the material of silicon dioxide or silicon oxynitride and nitridation can be included, but are not limited to
The top layer of silicon, aluminium oxide, hafnium oxide, zirconium oxide, hafnium silicate, Zirconium orthosilicate., hafnium oxy-nitride, hafnium Zirconium oxide and lanthana double
Layer dielectric area.
With reference to Fig. 1 and Fig. 2 D, electric charge capture layer 218 is on Tunneling dielectric 216 or overlies Tunneling dielectric formation (step
Rapid 108).Usually, as in the embodiment shown, electric charge capture layer 218 is multilamellar electric charge capture layer, its at least include closer to
The bottom of Tunneling dielectric 216 or the first electric charge capture layer 218a, and relative to the first electric charge capture layer oxygen deprivation and include distribution
The the second electric charge capture layer 218b of most at the charge trap of multilamellar electric charge capture layer.
First electric charge capture layer 218a of multilamellar electric charge capture layer 218 can include silicon nitride (Si3N4), silicon-rich silicon nitride
Or silicon oxynitride (SiOxNy (Hz)).Such as, the first electric charge capture layer 218a can include having between 2.0nm to 4.0nm
The silicon oxynitride layer of thickness, by CVD technique, uses proportional and is being adapted to provide for a kind of Silicon-rich and oxygen-enriched nitrogen oxides
Dichlorosilane (DCS)/ammonia (NH of the flow velocity of layer3) and nitrous oxide (N2O)/NH3Admixture of gas and formed.
Second electric charge capture layer 218b of multilamellar electric charge capture layer 218 then shape on the first electric charge capture layer 218a
Become.Second electric charge capture layer 218b can include having the oxygen of composition, nitrogen and/or the silicon being different from the first electric charge capture layer 218a
The silicon nitride of stoichiometric composition and silicon oxynitride layer.Second electric charge capture layer 218b can include having at 2.0nm extremely
The silicon oxynitride layer of the thickness between 5.0nm, it is possible to used by CVD technique and include proportional and be adapted to provide for one
Silicon-rich, the DCS/NH of flow velocity of top nitride layer of oxygen deprivation3And N2O/NH3Admixture of gas and be formed or deposit.
As used herein, term " oxygen-enriched " and " Silicon-rich " are relative to stoichiometric silicon nitride or " nitride ", logical
Often be deployed in have (Si3N4) and possess about 2.0 refractive index (RI) compositions field in.Therefore, " oxygen-enriched " nitrogen oxygen
SiClx brings chemically stoichiometric silicon nitride to change (i.e. reduce nitrogen) towards the higher percentage by weight of silicon and oxygen.The most oxygen-enriched nitrogen
Silicon oxide film is more similar silicon dioxide and RI to be reduced towards the 1.45RI of pure silicon dioxide.Similarly, it is described herein as " rich
Silicon " thin film bring chemically stoichiometric silicon nitride towards the higher percentage by weight with the silicon more less than the oxygen of " oxygen-enriched " thin film
Change.The most oxygen-enriched silicon oxynitride film is more similar silicon and RI to be increased towards the 3.5RI of pure silicon.
In certain embodiments, multilamellar electric charge capture layer 218 is the electric charge capture layer separated, and also includes catching the first electric charge
Obtain layer 218a and the second electric charge capture layer 218b and carry out separate thin, intermediate oxide layer 220.Intermediate oxide layer 220 is substantially
The electron charge reducing the boundary being accumulated in the second electric charge capture layer 218b during programming is tunneling to the first electric charge capture layer
The probability of 218a, causes the leakage current lower than traditional memory device.
In one embodiment, intermediate oxide layer 220 is by using heat or free-radical oxidation to be oxidized to selected
The degree of depth and formed.Such as, free-radical oxidation can use single wafer instrument at the temperature of 1000 DEG C-1100 DEG C, or
Batch reactor instrument is used to perform at 800 DEG C of-900 DEG C of temperature.H2And O2The mixture of gas can use single wafer
In the time of 1 to 2 minute of instrument or 30 minutes to 1 hour of use batch processing, with the ratio of about 1:1 with at criticizing
Reason 300 to 5005 torr, or use single gaseous state instrument 10 to 155 torr pressure at be introduced in process chamber.Real at some
Executing in example, free-radical oxidation technique is not have combustion incident, the formation of such as plasma, and it generally will be otherwise used for
To H2And O2Carry out being pyrolyzed to form steam.On the contrary, H2And O2Be allowed to the surface of the first electric charge capture layer 218a reaction with
Form free radical, such as OH base, HO2Base or O-double-basis, in order to form intermediate oxide layer 220.
With reference to Fig. 1 and Fig. 2 E, cap rock 222 is formed on dielectric stack 214 or electric charge capture layer 218 or overlies electricity
Medium stacking 214 or electric charge capture layer 218 (step 110).In certain embodiments, it is all as indicated, cap rock 222 is multilayer cover
Layer, including overlying at least one bottom or the first cover 222a of electric charge capture layer 218 and overlying first cover 222a's
Second cap rock 222b.
In one embodiment, first cover 222a can include high-temperature oxide (HTO), such as silicon dioxide
(SiO2), it has the thickness between 2.0nm to 4.0nm, use low-pressure chemical vapor deposition (LPCVD) thermal oxidation process and
Deposition.Such as, oxidizing process can include substrate 206 is exposed to such as silane, chlorosilane or dichlorosilane silicon source and
O in such as settling chamber2Or N2The oxygen-containing gas of O, from the cycle of about 10 minutes to about 120 minutes, with from about 50mT to about
The pressure of 1000mT, keeps substrate at the temperature of about 900 DEG C to about 1000 DEG C simultaneously.In certain embodiments, aoxidized
Journey is to perform with for forming the identical process chamber situ of the second electric charge capture layer 218b, and and then the second electric charge
The formation of trapping layer.
What the second cap rock 222b can include having the thickness between 2.0nm and 4.0nm uses N by CVD technique2O/
NH3And DCS/NH3Silicon nitride, silicon-rich silicon nitride or the silicon-rich silicon oxy-nitride layer that admixture of gas is formed.
With reference to Fig. 1 and Fig. 2 F, sacrificial oxide layer 224 is formed on cap rock 222 or overlies cap rock 222 (step 112).
In one embodiment, sacrificial oxide layer 224 can include being grown by thermal oxidation process or free-radical oxidation and have
There is high-temperature oxide (HTO) layer of thickness between 2.0nm and 4.0nm.In another embodiment, sacrificial oxide layer 224
Can be formed by the chemical vapor deposition method in low-pressure chemical vapor deposition (LPCVD) room or deposit.Such as, sacrificial
Domestic animal oxide layer 224 can use proportional and to be adapted to provide for the sacrificial oxide layer of silicon dioxide (SiO2) by CVD technique
The silane of flow velocity or DCS and such as O2And N2The admixture of gas of the oxygen-containing gas of O and deposit.
It follows that with reference to Fig. 1 and Fig. 2 G, the mask layer 226 of patterning is formed on sacrificial oxide layer 224 or overlies
Sacrificial oxide layer 224, and with reference to Fig. 2 H, sacrificial oxide layer, cap rock 222 and dielectric stack 214 are etched or pattern, and use
In forming the gate stack 228 of the raceway groove 202 overlying memory device and for from the second area 210 of substrate 206
Except sacrificial oxide layer, cap rock and dielectric stack (step 114).The mask layer 226 of patterning can include the light of use standard
The photoresist oxidant layer of lithography, and sacrificial oxide layer 224, cap rock 222 and dielectric stack 214 can use and include one
Or the dry etch process of multiple single step is etched or removes, to stop at surface and the lining of Tunneling dielectric 216
On pad oxide 211.
With reference to Fig. 1 and Fig. 2 I, the top in sacrificial oxide layer 224 and multilamellar cap rock 222 or the one of the second cap rock 222b
Partially or substantially whole are removed (step 116) in high selectivity cleaning from gate stack 228.This scavenger
Skill also removes any oxide in the first area 204 and second area 210 being retained in outside gate stack 228, such as aoxidizes
Thing Tunneling dielectric 216 and pad oxide 211, in order to prepare the substrate 206 in that region for gate oxide growth.
In an exemplary realization, sacrificial oxide layer 224 and the second cap rock 222b is to use to comprise surface in wet cleaning processes
The 10:1 buffer oxide etch (BOE) of activating agent is removed.Alternatively, wet cleaning processes can use 20:1BOE wet
Formula etching, the etching of 50:1 Fluohydric acid. (HF) Wet-type etching, liner or any other like Wet-type etching based on Fluohydric acid.
Learn composition to perform.
It follows that with reference to Fig. 1 and Fig. 2 J, oxidizing process is performed to aoxidize cap rock 222 or the first cover of multilamellar cap rock
The remaining part of 222a, and alternatively, the part aoxidizing the second electric charge capture layer 218b overlies the second electricity to be formed
The barrier oxide layer 230 of lotus trapping layer.In one embodiment, oxidizing process is suitable for aoxidizing first cover 222a to form resistance
Gear oxide layer 230, at least some of of the surface of the substrate 206 in simultaneous oxidation second area 210 overlies at least to be formed
The first grid oxide 232 (step 118) of at least one raceway groove 208 of one MOS device.Oxidizing process can be included in band
Or generate without the situ steam carried out in the batch processing of such as Plasma burning event or single base treatment room
(ISSG), CVD or free-radical oxidation.Such as, in one embodiment, barrier oxide layer 230 and gate oxide 232 can be
Growing in free-radical oxidation technique, this free-radical oxidation technique relates to making hydrogen (H2) gas and oxygen (O2) gas is with the speed of mutually about 1:1
Rate flows into process chamber, and does not has combustion incident, and the formation of such as plasma, it generally will be otherwise used for H2And O2
Carry out being pyrolyzed to form steam.On the contrary, H2And O2It is allowed to about temperature in the range of 700 DEG C-800 DEG C about to exist
Pressure in the range of 0.5 to 5 torr carries out reacting to form free radical on the surface of cap rock 222 or first cover 222a, such as OH
Base, HO2 base or O-double-basis free radical.Free-radical oxidation process be carried out about lasting in the range of 10 to 15 minutes time
Between, with by first cover 222a with have of the second electric charge capture layer 218b from about 3nm to the thickness of about 4.5nm
Point oxidation and consumption and realize the growth of barrier oxide layer 230, and realize there are the grid from about 5nm to the thickness of about 7nm
Pole oxide 232.
In certain embodiments, such as shown in Fig. 2 K to Fig. 2 Q, method also include dual-gate oxide process flow process with
MOS device 234 and HV MOS device 236 can be manufactured.With reference to Fig. 1 and Fig. 2 K, the mask layer 238 of patterning is formed on substrate
On the first area 204 of 206 and second area 210 (step 120).The mask layer 238 of patterning can be use standard
The photoresist oxidant layer of photoetching technique patterning, and at least one on the raceway groove 208 being included in second area 210 open
Mouth 240.Thick first grid oxide 232 is similar in appearance to above with reference to removing those conditions that sacrificial oxide layer 224 describes
Under by use BOE etch and by expose region in etch, and patterning mask layer 238 be then removed.
With reference to Fig. 1 and Fig. 2 L, substrate 206 is used the Wet-type etching not etching oxide to be cleaned by, in order to protection HV
The first grid oxide 232 of MOS device 236 and the barrier oxide layer 230 of gate stack 228 and first grid oxide 232
(step 122).Substrate 206 be then subjected to thermal oxidation process with growth have from about 1.5nm to the thickness of about 3nm thin, the
Two gate oxides 242.
In certain embodiments, thin high-k or high-k dielectric material can substitute for silicon dioxide and use.High k
Dielectric substance can include, but not limited to such as by ald (ALD), physical vapour deposition (PVD) (PVD), chemistry gas
Deposition (CVD), low pressure chemical vapor deposition (LPCVD) or the hafnium oxide of plasma enhanced CVD (PECVD) process deposits, zirconium oxide, silicon mutually
Acid hafnium, hafnium oxy-nitride, hafnium oxide zirconium and lanthana.
With reference to Fig. 1 and Fig. 2 M, it is suitable for adapting to any conduction of the operation of the bias of memory device and MOS device or partly leading
The grid layer 244 of body material is formed on the first grid oxide 232 and MOS of gate stack 228, HV MOS device 236
On the second grid oxide 242 of device 234 (step 124).In one embodiment, this grid layer is to pass through physical vapor
Deposition and be formed and by can include, but not limited to metal nitride, metal carbides, metal silicide, hafnium, zirconium, titanium,
The metal-containing material composition of tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel.In another embodiment, grid layer is by CVD technique
It is formed and is made up of the polysilicon adulterated.
With reference to Fig. 1 and Fig. 2 N, grid layer 244 be use the photoetching technique of mask layer (not shown) and standard pattern with
Stop on the surface of barrier oxide layer 230, first grid oxide 232 and second grid oxide 242, thus formed and be used for
The grid 246 of the gate stack 228 of memory device 248, for the grid 250 of HV MOS device 236 and for MOS device
The grid 252 (step 126) of 234.
With reference to Fig. 1 and Fig. 2 O-2P, sidewall spacers 254 adjacent to the grid 246,250,252 about whole devices,
And the part of the remaining exposure of barrier oxide layer 230, first grid oxide 232 and second grid oxide 242 are formed,
Anisotropically it is etched to produce and there is essentially completed memory device 248, HV MOS device 236 and MOS device 234
Structure (step 128) shown in Fig. 2 P.
With reference to Fig. 1 and Fig. 2 Q, at the grid that memory device 248, HV MOS device 236 and MOS device 234 are essentially completed
In the case of stacking, most advanced and sophisticated and/or HALO injects and can be performed to be formed extended area 256, and source electrode and drain electrode injection are performed
To form the source electrode about whole devices and drain region 258 (step 130).
In other embodiments, cap rock can include silicon nitride or the simple layer of silicon oxynitride or multiple layer.Cap rock 322 can
Be have the silicon nitride of uniformly composition or the simple layer of silicon oxynitride, the silicon nitride of the gradient having in stoichiometric composition or
The simple layer of silicon oxynitride, or as the most in the embodiment shown, can be include overlying electric charge capture layer 318 include nitridation
At least bottom of thing or the multilamellar cap rock of first cover 322a and nitride the second cap rock 322b overlying first cover 322a.
With reference to Fig. 3 A, use the method that multilamellar cap rock 322 manufactures the integrated circuit (IC) including MOSFET and non-NVM device
Start from being formed Tunneling dielectric 316 and electric charge capture layer 318 on the surface of substrate 306.Tunneling dielectric 316, electric charge
Trapping layer 318 and substrate 306 have such as the composition above with reference to described in Fig. 1 and Fig. 2 A to 2D and/or can be as above with reference to Fig. 1
Formed with describing with Fig. 2 A to 2D.Usually, as in the embodiment shown, electric charge capture layer 318 is multilamellar electric charge capture layer, its
At least include the bottom closer to Tunneling dielectric 316 or the first electric charge capture layer 318a, and relative to the first electric charge capture layer
Oxygen deprivation also includes the second electric charge capture layer 318b of most being distributed in the charge trap of multilamellar electric charge capture layer.Alternatively,
As described above with reference to Fig. 2 D, electric charge capture layer 318 can be the electric charge capture layer separated, and also includes the first electric charge capture layer
318a and the second electric charge capture layer 318b carries out separate thin, intermediate oxide layer (not shown in this drawing).
What first cover 322a can include having the thickness between 2.0nm and 4.0nm uses N by CVD technique2O/
NH3And DCS/NH3Silicon nitride, silicon-rich silicon nitride or the silicon-rich silicon oxy-nitride layer that admixture of gas is formed.Similarly, the second cap rock
What 322b can also include having the thickness between 1.5nm and 4.0nm uses N by CVD technique2O/NH3And DCS/NH3Gas
Silicon nitride, silicon-rich silicon nitride or the silicon-rich silicon oxy-nitride layer that body mixture is formed.Alternatively, first cover 322a and the second cap rock
322b can include different stoichiometries.Such as, first cover 322a can have silicon or oxygen-enriched composition, such as, first
Cap rock can include oxygen-enriched nitride or the nitrogen with substantially identical for electric charge capture layer 318a with first stoichiometric composition
Oxide, to promote the oxidation subsequently of first cover, substantially the same stoichiometry
Similarly, the second cap rock 322b can also include having the thickness between 1.5nm and 4.0nm by CVD work
Skill uses N2O/NH3And DCS/NH3Silicon nitride, silicon-rich silicon nitride or the silicon-rich silicon oxy-nitride layer that admixture of gas is formed.Optional
Ground, the second cap rock 322b can have the stoichiometric composition substantially the same for electric charge capture layer 318b with second, its relative to
First cover 322a oxygen deprivation.
It follows that sacrificial oxide layer 324 is formed on dielectric covers 322 or overlies dielectric covers 322.Sacrifice
Oxide layer 324 can have the composition of the composition being substantially identical to sacrificial oxide layer 224, and can be as above with reference to that
Layer is described and is formed.
It follows that as above with reference to described in Fig. 2 G to 2H, sacrificial oxide layer 324, electric charge capture layer 318 and cap rock 322
It is patterned to form the gate stack 328 in the first area of substrate 306 or NVM region, and with from second area or MOS
Region (the most shown in this figure) is removed described layer.
With reference to Fig. 3 B, sacrificial oxide layer 324 and top or a part of the second cap rock 322b or substantially whole
High selectivity cleaning is removed from gate stack 328.This cleaning can be substantially identical to above with reference to figure
The GOX prerinse that 2I describes.
With reference to Fig. 3 C, oxidizing process is performed to aoxidize the remaining of the first cover 322a of cap rock 322 or multilamellar cap rock
Part, and alternatively, aoxidize a part of the second electric charge capture layer 318b to form the resistance overlying the second electric charge capture layer
Gear oxide layer 330.Oxidizing process can be substantially identical to that process described above with reference to Fig. 2 J.In some embodiments
In, oxidizing process is used at least one grid of MOS device or the transistor concurrently forming in the second area of substrate
Oxide (the most shown in this figure).
As above with reference to described in Fig. 2 H to 2Q, substantially continue this technological process to complete NVM and MOS device or crystal
The manufacture of pipe.
In other other embodiments, with reference to described by Fig. 4 A-4F, the first cover of multilamellar cap rock includes using wet
The silicon oxide that formula thermal oxidation process or situ steam generate (ISSC) technique and grow, do not deposit.
With reference to Fig. 4 A, method starts from being formed Tunneling dielectric 416 on the surface of substrate 406, and includes the first electricity
Lotus trapping layer 418a and the electric charge capture layer 418 of the second electric charge capture layer 418b.Tunneling dielectric 416, electric charge capture layer 418 and
Substrate 406 has such as the composition above with reference to described in Fig. 1 and Fig. 2 A to 2D and/or can be as above with reference to Fig. 1 and Fig. 2 A to 2D
Describe ground to be formed.It follows that the first sacrificial oxide layer 423 is formed on the second electric charge capture layer 418b or overlies the second electricity
Lotus trapping layer 418b.Sacrificial oxide layer 423 can have the composition of the composition being substantially identical to sacrificial oxide layer 224 and 324,
And can be as being formed above with reference to described by those layers.
It follows that with reference to Fig. 4 B, the first sacrificial oxide layer 423 is in the substantially phase described above with reference to Fig. 2 I and Fig. 3 B
It is same as in the prewashed cleaning of GOX being removed.As those cleanings, remove the first sacrificial oxide layer 423
Cleaning can also remove a part of the second electric charge capture layer 418b of overlying.
It follows that be to use wet type thermal oxidation process ISSG technique to be formed on the with reference to Fig. 4 C, first cover 422a
On two electric charge capture layer 418b or overlie the second electric charge capture layer 418b.Usually, use at least about in ISSG room
Water at the temperature of 1000 DEG C performs or carries out ISSG technique.
It follows that with reference to Fig. 4 D, substrate is returned to the Tunneling dielectric 416 for forming initial dielectric stack and electricity
The instrument of lotus trapping layer 418, and the second cap rock 422b is formed on first cover 422a or overlies first cover 422a.
Usually, the second cap rock 422b can include having the composition being substantially identical to the second cap rock 222b and 322b described above
Composition, and can include having thickness between 2.0nm and 4.0nm use N by CVD technique2O/NH3And DCS/
NH3Silicon nitride, silicon-rich silicon nitride or the silicon-rich silicon oxy-nitride layer that admixture of gas is formed.Second sacrificial oxide layer 424 is formed
On the second cap rock 222b or overlie the second cap rock 222b.Usually, sacrificial oxide layer 424 have 2.0nm and 4.0nm it
Between thickness and be substantially identical to the composition of composition of sacrificial oxide layer 224,324 and 423, can be as above with reference to those layers
Described and be formed.Sacrificial oxide layer 424, cap rock 422, Tunneling dielectric 416 and electric charge capture layer 418 are etched or pattern
Change, overlie the gate stack 428 on the raceway groove 402 of memory device and for (not existing from the second area of substrate to be formed
Shown in this figure) in remove sacrificial oxide layer, cap rock and dielectric stack.
With reference to Fig. 4 E, sacrificial oxide layer 424 and top or a part of the second cap rock 422b or substantially whole
High selectivity cleaning is removed from gate stack 428.This cleaning can be substantially identical to above with reference to figure
The GOX prerinse that 2I describes.
Finally, with reference to Fig. 4 F, oxidizing process is performed to aoxidize the surplus of the first cover 422a of cap rock 422 or multilamellar cap rock
Remaining part, and alternatively, the part aoxidizing the second electric charge capture layer 418b overlies the second electric charge capture layer to be formed
Barrier oxide layer 430.Oxidizing process can be substantially identical to that process described above with reference to Fig. 2 J.Implement at some
In example, oxidizing process is used for concurrently forming the MOS device in the second area (the most shown in this figure) for substrate or crystalline substance
At least one gate oxide of body pipe.
As above with reference to described in Fig. 2 H to 2Q, substantially continue this technological process to complete NVM and MOS device or crystal
The manufacture of pipe.
In another embodiment replaced, including the IC of MOSFET He the NVM device with charge-trapping gate stack
It is to use to have for growth of oxygen compound first cover and the cluster work of the single settling chamber of cvd nitride thing or nitrogen oxides
Tool is manufactured.Suitably single-chip cluster tool includes, such as, from being positioned at Santa, and the Applied Materials of Calif
The commercially available Centura of IncTMPlatform.
With reference to the flow chart of Fig. 5, method starts by the ISSG long tunnel in next life in first room (room 1) of cluster tool
Oxide layer (TUNOX) (step 502).It follows that substrate to be transferred to second room (room 2) of cluster tool, and deposit multilamellar
Bottom nitride silicon (B_SiN) layer of electric charge capture layer and top nitride silicon (T_SiN) layer (step 504).For deposited bottom layer
It is substantially identical to those composition and the techniques above with reference to described by Fig. 1 and Fig. 2 A to 2D with composition and the technique of top layers.
It follows that substrate returns to first room (room 1) of cluster tool, and growth is used as multilayer cover on top (T_SiN) layer
The thin oxide (step 506) of the ground floor of layer.Composition and technique for growing thin oxide be substantially identical to
Upper with reference to the wet type thermal oxidation process described by first cover 422a or ISSG technique.Substrate is returned to the second of cluster tool
Room (room 2), and second silicon nitride of the second layer of multilamellar cap rock it is used as at the grown on top of thin oxide first cover
Layer (the 2nd T_SiN) (step 508).In the final step using cluster tool to perform, cluster tool is transferred in substrate
3rd room (room 3), and deposited sacrificial oxide layer (step 510) on the second silicon nitride layer.For deposited sacrificial oxide layer
Composition and technique be substantially identical to such as the dry type thermal oxidation process above with reference to described by sacrificial oxide layer 224.Then will
Substrate is removed from cluster tool, performs to clean to remove sacrificial oxide layer and the second whole silicon nitrides
Layer, and perform oxidizing process to aoxidize a part for thin oxide or first cover and overlying top charge trapping layer with shape
Become the barrier oxide (step 512) on electric charge capture layer.
As above with reference to described in Fig. 2 H to 2Q, substantially continue this technological process to complete NVM and MOS device or crystal
The manufacture of pipe.
In one aspect of the method, it relates to many grids or the memory device of many gate surface, it includes overlaying on by shape
Become on the surface of the substrate or on raceway groove two or more sides on charge-trapping region, and relate to manufacturing it
Method.Nonplanar multigate device generally include be formed on the surface of the substrate or on and by grid around three or more
Horizontally or vertically raceway groove on many sides.
Fig. 6 A shows and is included in the nonplanar many grids memory device formed on the first area 604 of substrate 606
602 and the second area 610 that is adjacent in the embodiment of the integrated circuit 600 of MOS device 608 that forms.
With reference to Fig. 6 A, memory device 602 (being commonly called finFET) includes that the thin film from semi-conducting material or layer are formed
Raceway groove 614, this raceway groove 614 overlays on the surface 616 in substrate 606, by source electrode 618 and drain electrode 620 connection of memory device.
Raceway groove 614 is closed by the fin of the gate stack 622 forming this device on three sides.The thickness of gate stack 622 is (from source
Pole is measured in drain directions) determine the length of effective channel of this device.
According to the disclosure, nonplanar many grids memory device 602 of Fig. 6 A can include multilamellar electric charge capture layer and lead to
Cross the oxidation of a part for cap rock and electric charge capture layer and consume the barrier oxide layer formed.Fig. 6 B is that the nonplanar of Fig. 6 A deposits
The cross-sectional view of a part for memory device, including a part, raceway groove 614 and the gate stack 622 of substrate 606.Gate stack 622
Including the Tunneling dielectric 624 on the raceway groove 614 overlaying on protuberance, electric charge capture layer 626, barrier oxide layer 628 with overlay on stop
Grid layer 630 on layer is to form the control gate of memory device 602.As it has been described above, grid layer 630 can include that doping is many
Crystal silicon or metal level.Raceway groove 614 and gate stack 622 can directly be formed or at insulation or dielectric layer in substrate 606
On 632 formed, be such as formed in substrate or on buried oxide layer.
Although illustrating the most in these figures, it should be understood that electric charge capture layer 626 can be multilamellar electric charge capture layer,
It includes at least one bottom including nitride or first electric charge capture layer closer to Tunneling dielectric 624, and overlays on
Top on one electric charge capture layer or the second electric charge capture layer.Usually, the second electric charge capture layer includes Silicon-rich, lean oxynitride
Layer and include being distributed in most of charge trap of multiple electric charge capture layer, the first electric charge capture layer includes oxygen-enriched nitridation simultaneously
Thing or silicon oxynitride, and be oxygen-enriched relative to top charge trapping layer to reduce the quantity of wherein charge trap.By oxygen-enriched, meaning
It is from about 15% to about 40% that taste the concentration of the oxygen in wherein the first electric charge capture layer, but the oxygen in the second electric charge capture layer
Concentration be less than about 5%.In certain embodiments, multilamellar electric charge capture layer also includes the second electric charge capture layer and the first electricity
Lotus trapping layer at least one thin, middle or middle part oxide layer separate.
Finally, as above with reference to described in Fig. 2 A-2Q, barrier oxide layer 628 can include by catching cap rock and electric charge
The oxide obtaining the oxidation of a part for layer 626 and consumption and formed.
In the embodiment shown in Fig. 6 A, MOS device 608 be also finFET and include the thin film from semi-conducting material or
The raceway groove 634 that layer is formed, this raceway groove 634 overlays on the surface 616 in substrate 606, by source electrode 636 and the drain electrode 638 of MOS device
Connect.Raceway groove 634 is closed by the fin of grid 640 or grid forming MOS device 608 the most on three sides.With reference to Fig. 6 B,
The grid 640 of MOS device 608 includes the gate oxide 642 overlaying on the raceway groove 634 of protuberance and overlays on gate oxide
The polycrystalline silicon gate layer 644 of metal or doping.
Therefore, including the integrated circuit of MOSFET and the nonvolatile memory device including charge-trapping gate stack
Embodiment has been described with forming identical method.Although present disclosure is carried out by reference to specific exemplary embodiment
Describe, but it will be apparent that various modifications and changes these embodiments can be made without deviating from the disclosure wider
Spirit and scope.Therefore, specification and drawings is considered as illustrative and not restrictive.
The summary of the disclosure is provided to meet require summary reader will to be allowed quickly to determine technology disclosure one
Or 37CFR § 1.72 (b) of the character of multiple embodiment.It will not be used to explain or limit the scope of claim based on it
Or the understanding of implication is submitted.It addition, in aforementioned detailed description, it can be seen that various features combine in single embodiment
Together, for simplifying the purpose of the disclosure.Disclosed method is not necessarily to be construed as reflecting that embodiment required for protection needs
Intention than the more feature being expressly recited in each claim.On the contrary, as the following claims reflect, send out
Bright theme is all features less than single open embodiment.Therefore, claim below is hereby incorporated into specifically
In bright, each claim is independently as independent embodiment.
In description, the reference to an embodiment or embodiment means to combine special characteristic, the knot that this embodiment describes
Structure or characteristic are included at least one embodiment of this circuit or method.Each local phrase occurred in this manual
One embodiment is not necessarily all referring to identical embodiment.
Claims (20)
1. a method, including:
Forming dielectric stack in substrate, described dielectric stack is included in the Tunneling dielectric on described substrate and in institute
State the electric charge capture layer on Tunneling dielectric；
The first cover including oxide is formed on described dielectric stack；
The second cap rock including nitride is formed on described first cover；
Described first cover and the second cap rock and described dielectric stack is patterned with shape in the first area of described substrate
Become the gate stack of memory device；
Remove described second cap rock；And
Execution oxidizing process is to form barrier oxide on described electric charge capture layer, and wherein, described oxidizing process consumes institute
State first cover.
Method the most according to claim 1, wherein, forms first cover and includes using the low-pressure oxidized process performed in situ
Depositing high temperature oxide (HTO) in the identical room for forming described dielectric stack.
Method the most according to claim 1, wherein, described oxidizing process consumes a part for described electric charge capture layer.
Method the most according to claim 1, wherein, described oxidizing process does not the most consume any described charge-trapping
Layer.
Method the most according to claim 1, is additionally included in formation sacrifical oxide, Yi Jiqi on described second cap rock
In, patterning is included in the described first area of described substrate with the described gate stack of formation and patterns described sacrificial oxidation
Thing, described first cover and the second cap rock and described dielectric stack to form the described gate stack of described memory device,
From the second area of described substrate, remove described sacrifical oxide, described first cover and the second cap rock simultaneously and described electricity is situated between
Matter stacks.
Method the most according to claim 5, wherein, removes described second cap rock and includes removing institute from described gate stack
State sacrifical oxide and described second cap rock, from the described second area of described substrate, remove oxide simultaneously.
Method the most according to claim 6, wherein, performs described oxidizing process and includes same to form described barrier oxide
Time in the described second area of described substrate, form the gate oxide of logical device.
8. a method, including:
Forming dielectric stack in substrate, described dielectric stack is included in the Tunneling dielectric on described substrate and in institute
State the electric charge capture layer on Tunneling dielectric；
The first cover including oxygen-enriched nitride is formed on described dielectric stack；
The second cap rock including nitride is formed on described first cover；
Described first cover and the second cap rock and described dielectric stack is patterned with shape in the first area of described substrate
Become the gate stack of memory device；
Remove described second cap rock；And
Execution oxidizing process is to form barrier oxide on described electric charge capture layer, and wherein, described oxidizing process consumes institute
State first cover.
Method the most according to claim 8, wherein, described electric charge capture layer includes multilamellar electric charge capture layer, and it at least wraps
Include closer to the first described Tunneling dielectric, oxygen-enriched nitride layer and the second nitridation on described first nitride layer
Nitride layer, described second nitride layer is oxygen deprivation relative to described first nitride layer, and includes being distributed in multilamellar charge-trapping
The major part of the charge trap in Ceng.
Method the most according to claim 9, wherein, described first cover and described the of described multilamellar electric charge capture layer
Mononitride layer includes substantially the same stoichiometric composition.
11. methods according to claim 10, wherein, described second cap rock and described the of described multilamellar electric charge capture layer
Second nitride layer includes substantially the same stoichiometric composition.
12. methods according to claim 8, are additionally included in formation sacrifical oxide, Yi Jiqi on described second cap rock
In, patterning is included in the described first area of described substrate with the described gate stack of formation and patterns described sacrificial oxidation
Thing, described first cover and the second cap rock and described dielectric stack to form the described gate stack of described memory device,
And to remove described sacrifical oxide, described first cover and the second cap rock and described from the second area of described substrate
Dielectric stack.
13. methods according to claim 12, wherein, remove described second cap rock and include removing institute from described gate stack
State sacrifical oxide and described second cap rock, from the described second area of described substrate, remove oxide simultaneously.
14. methods according to claim 13, wherein, perform described oxidizing process and include to form described barrier oxide
In the described second area of described substrate, form the gate oxide of logical device simultaneously.
15. 1 kinds of methods, including:
Forming dielectric stack in substrate, described dielectric stack is included in the Tunneling dielectric on described substrate and in institute
State the electric charge capture layer on Tunneling dielectric；
In the first Room of cluster tool, on described dielectric stack, growth includes the first cover of thin oxide；
On described first cover, the second cap rock including nitride is formed in the second Room of described cluster tool；
Use free-radical oxidation process to be formed in the 3rd Room of described cluster tool on described second cap rock and include high temperature
The sacrifical oxide of oxide (HTO)；
The first area of described substrate patterns described sacrifical oxide, described first cover and described second cap rock and
Described dielectric stack is to form the gate stack of memory device；
Remove described sacrifical oxide and described second cap rock；And
Execution oxidizing process is to form barrier oxide on described electric charge capture layer, and wherein, described oxidizing process consumes institute
State first cover.
16. methods according to claim 15, wherein, described electric charge capture layer includes multilamellar electric charge capture layer, and it is at least
Including the first nitride layer closer to described Tunneling dielectric and the second nitride layer on described first nitride layer,
Described second nitride layer is oxygen deprivation relative to described first nitride layer, and includes being distributed in multilamellar electric charge capture layer
The major part of charge trap.
17. methods according to claim 16, wherein, described second cap rock and described the of described multilamellar electric charge capture layer
Second nitride layer includes substantially the same stoichiometric composition.
18. methods according to claim 15, wherein, pattern and also include from described substrate with the described gate stack of formation
Second area in remove described sacrifical oxide, described first cover and the second cap rock and described dielectric stack.
19. methods according to claim 18, wherein, remove described sacrifical oxide and described second cap rock include simultaneously
Oxide is removed from the described second area of described substrate.
20. methods according to claim 19, wherein, perform described oxidizing process and include to form described barrier oxide
In the described second area of described substrate, form the gate oxide of logical device simultaneously.
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| US14/490,514 | 2014-09-18 | ||
| US14/490,514 US8993457B1 (en) | 2014-02-06 | 2014-09-18 | Method of fabricating a charge-trapping gate stack using a CMOS process flow |
| PCT/US2015/014118 WO2015119893A2 (en) | 2014-02-06 | 2015-02-02 | Method of fabricating a charge-trapping gate stack using a cmos process flow |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8071453B1 (en) * | 2009-04-24 | 2011-12-06 | Cypress Semiconductor Corporation | Method of ONO integration into MOS flow |
| CN103258798A (en) * | 2012-02-15 | 2013-08-21 | 赛普拉斯半导体公司 | Method of integrating a charge-trapping gate stack into a cmos flow |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8071453B1 (en) * | 2009-04-24 | 2011-12-06 | Cypress Semiconductor Corporation | Method of ONO integration into MOS flow |
| CN103258798A (en) * | 2012-02-15 | 2013-08-21 | 赛普拉斯半导体公司 | Method of integrating a charge-trapping gate stack into a cmos flow |
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