CN106059512A - Novel low-complexity broadband variable gain amplifier - Google Patents

Abstract

The invention discloses a novel low-complexity broadband variable gain amplifier, which comprises an active load circuit, a current source circuit, a differential input circuit, a gm-boost circuit and a gain control circuit, and the active load circuit is connected with the gm-boost respectively. The circuit is connected to the differential input circuit, and the current source circuit is respectively connected to the differential input circuit, the gm-boost circuit and the gain control circuit. The present invention can realize the dB linear relationship between the output and the input without an exponential generating circuit, and effectively enhances the equivalent input transconductance of the VGA through the gm-boost circuit, so that the VGA can have higher linearity and a wider dB linear range At the same time, the bandwidth of the VGA can be greatly expanded without increasing the power consumption of the VGA through the active load circuit. The invention can be widely used in amplifier products.

Description

A Novel Low Complexity Broadband Variable Gain Amplifier

technical field

The invention relates to the technical field of electronic circuits, in particular to a novel low-complexity broadband variable gain amplifier.

Background technique

VGA is a variable gain amplifier. In an analog integrated circuit system, VGA can adjust different signal gains according to different control voltages. In the fields of wireless communication transceiver system, human body medium communication, disk access circuit and weak signal processing, due to the influence of factors such as communication distance, transmission path and blocking fading, the dynamic range of the received signal is large. Therefore, in order to ensure better stability of the received signal, the adjustable characteristic of the gain of the receiving system becomes particularly important. VGA can adjust the output gain according to the feedback signal, and stabilize the received signal near a predetermined amplitude. The linearity, dB linear range and bandwidth of VGA largely determine its performance and application range. The existing VGA usually increases its linearity and dB linear range by adding a relatively complex exponential generating circuit, which increases the complexity of the circuit and the area of the chip, and increases the production cost of the chip. In order to increase the bandwidth of the VGA, most VGAs achieve the goal by increasing the current consumption, which greatly increases the power consumption of the system.

Contents of the invention

In order to solve the above technical problems, the object of the present invention is to provide a novel low-complexity broadband variable gain amplifier capable of improving linearity and extending bandwidth.

The technical scheme that the present invention takes is:

A novel low-complexity wideband variable gain amplifier, comprising an active load circuit, a current source circuit, a differential input circuit, a gm-boost circuit and a gain control circuit, the active load circuit is connected to the gm-boost circuit and the differential input circuit respectively The circuit is connected, and the current source circuit is respectively connected with the differential input circuit, the gm-boost circuit and the gain control circuit.

As a further improvement of the present invention, the active load circuit includes a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, The first capacitor and the second capacitor, the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are all connected to the power supply terminal, and the source of the first PMOS transistor is connected to the power supply terminal. The gates of the five PMOS transistors are connected to the gates of the first PMOS transistors through the third resistor, the gates of the sixth PMOS transistors are connected to the gates of the second PMOS transistors through the fourth resistor, and the gates of the first PMOS transistors The gate is connected to the gate of the second PMOS transistor, the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor through a first resistor, and the gate of the second PMOS transistor is connected through a second resistor To the drain of the second PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor through the first capacitor, and the gate of the sixth PMOS transistor is connected to the first PMOS transistor through the second capacitor The drain of the transistor, the drain of the first PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the differential input circuit and the gm-boost circuit, the drain of the second PMOS transistor is respectively connected to the sixth PMOS transistor The drain is connected to the differential input circuit and the gm-boost circuit, the drain of the first PMOS transistor is connected to the negative output terminal, and the drain of the second PMOS transistor is connected to the positive output terminal.

As a further improvement of the present invention, the differential input circuit includes a first NMOS transistor and a second NMOS transistor, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the source of the first NMOS transistor respectively connected to the gm-boost circuit, the gain control circuit and the current source circuit, the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, and the source of the second NMOS transistor is respectively connected to the gm- The boost circuit, the gain control circuit and the current source circuit are connected, the gate of the first NMOS transistor is connected to the positive input terminal, and the gate of the second NMOS transistor is connected to the negative input terminal.

As a further improvement of the present invention, the gm-boost circuit includes a third PMOS transistor and a fourth PMOS transistor, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply terminal, and the first The gates of the three PMOS transistors are respectively connected to the drain of the first NMOS transistor and the drain of the first PMOS transistor, the drain of the third PMOS transistor is connected to the source of the first NMOS transistor, and the fourth PMOS The gate of the transistor is respectively connected to the drain of the second NMOS transistor and the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the source of the second NMOS transistor.

As a further improvement of the present invention, the gain control circuit includes a third NMOS transistor and a fourth NMOS transistor, the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are both connected to the gain control voltage terminal, the Both the source of the third NMOS transistor and the source of the fourth NMOS transistor are connected to the source of the first NMOS transistor, and the drain of the third NMOS transistor and the drain of the fourth NMOS transistor are both connected to the second NMOS transistor. source.

As a further improvement of the present invention, the current source circuit includes a fifth NMOS transistor and a sixth NMOS transistor, the gates of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the bias voltage terminal, the The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the ground, and the drain of the fifth NMOS transistor is respectively connected to the source of the first NMOS transistor, the drain of the third PMOS transistor, the third NMOS transistor The source of the transistor is connected to the source of the fourth NMOS transistor, and the drain of the sixth NMOS transistor is respectively connected to the source of the second NMOS transistor, the drain of the fourth PMOS transistor, the drain of the third NMOS transistor and the drain of the sixth NMOS transistor. The drains of the fourth NMOS transistors are connected.

The beneficial effects of the present invention are:

A novel low-complexity wideband variable gain amplifier of the present invention can realize the dB linear relationship between the output and the input without an exponential generating circuit, and effectively enhances the equivalent input transconductance of the VGA through the gm-boost circuit, so that the VGA can have a relatively high High linearity and wide dB linear range. At the same time, the bandwidth of the VGA can be greatly expanded without increasing the power consumption of the VGA through the active load circuit.

Description of drawings

The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

Fig. 1 is a circuit schematic diagram of a novel low-complexity broadband variable gain amplifier of the present invention;

Fig. 2 is a block diagram of the VGA application principle of the embodiment of the present invention;

Fig. 3 is the half-side equivalent circuit diagram when the present invention assumes that there is no gm-boost circuit;

Fig. 4 is half side equivalent circuit diagram of the present invention;

Fig. 5 is a small-scale model diagram of a half-side equivalent circuit of the present invention;

Fig. 6 is an active load circuit diagram of the present invention;

Fig. 7 is a small signal model diagram of the active load circuit of the present invention;

Fig. 8 is the simulation result figure after VGA gain of the present invention;

Fig. 9 is the gain simulation result figure of VGA of the present invention under different control voltages;

Fig. 10 is a dB linear relationship diagram between VGA gain control voltage and gain of the present invention;

Fig. 11 is the dB linear curve fitting figure of the present invention;

Fig. 12 is a schematic diagram of the dB linearity error of the present invention.

detailed description

Referring to Fig. 1, a novel low-complexity broadband variable gain amplifier of the present invention includes an active load circuit, a current source circuit, a differential input circuit, a gm-boost circuit and a gain control circuit, and the active load circuit is respectively connected to gm - the boost circuit is connected to the differential input circuit, and the current source circuit is respectively connected to the differential input circuit, the gm-boost circuit and the gain control circuit.

Preferably, the active load circuit is used to compensate the pole of the system of the present invention to achieve the purpose of extending the bandwidth of the VGA. The current source circuit is used to provide a current source for the present invention, so that it can work at a suitable static operating point. The gm-boost circuit is used to enhance the equivalent input transconductance of the present invention to improve linearity. The differential input circuit is used to convert differential input voltage signals into current signals. The gain control circuit is used to adjust the gain of the present invention.

As a further preferred embodiment, the active load circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a first resistor R1, a second resistor R2, a third Resistor R3, fourth resistor R4, first capacitor C1 and second capacitor C2, the source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, the source of the fifth PMOS transistor PM5 and the sixth PMOS The sources of the transistor PM6 are all connected to the power supply terminal, the gate of the fifth PMOS transistor PM5 is connected to the gate of the first PMOS transistor PM1 through the third resistor R3, and the gate of the sixth PMOS transistor PM6 is connected through the fourth resistor R3. The resistor R4 is connected to the gate of the second PMOS transistor PM2, the gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, and the gate of the first PMOS transistor PM1 is connected to the gate of the first PMOS transistor PM1 through the first resistor R1 connected to the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2 is connected to the drain of the second PMOS transistor PM2 through the second resistor R2, and the gate of the fifth PMOS transistor PM5 is connected to the drain of the second PMOS transistor PM5 through the first The capacitor C1 is connected to the drain of the second PMOS transistor PM2, the gate of the sixth PMOS transistor PM6 is connected to the drain of the first PMOS transistor PM1 through the second capacitor C2, and the drains of the first PMOS transistor PM1 are respectively It is connected with the drain of the fifth PMOS transistor PM5, the differential input circuit and the gm-boost circuit, and the drain of the second PMOS transistor PM2 is respectively connected with the drain of the sixth PMOS transistor PM6, the differential input circuit and the gm-boost circuit , the drain of the first PMOS transistor PM1 is connected to the negative output terminal, and the drain of the second PMOS transistor PM2 is connected to the positive output terminal.

Further as a preferred embodiment, the differential input circuit includes a first NMOS transistor NM1 and a second NMOS transistor NM2, the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1, and the first NMOS The source of the transistor NM1 is connected to the gm-boost circuit, the gain control circuit and the current source circuit respectively, the drain of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2, and the second NMOS transistor The source of NM2 is respectively connected to the gm-boost circuit, the gain control circuit and the current source circuit, the gate of the first NMOS transistor NM1 is connected to the positive input terminal, and the gate of the second NMOS transistor NM2 is connected to the negative pole input.

Further as a preferred embodiment, the gm-boost circuit includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4, the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4 are both connected to the power supply terminal , the gate of the third PMOS transistor PM3 is respectively connected to the drain of the first NMOS transistor NM1 and the drain of the first PMOS transistor PM1, and the drain of the third PMOS transistor PM3 is connected to the drain of the first NMOS transistor NM1 The source is connected, the gate of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2 and the drain of the second PMOS transistor PM2 respectively, and the drain of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor PM4 Source connection of transistor NM2.

Wherein, the principle of enhancing the linearity of the gm-boost circuit is as follows:

When there is no gm-boost circuit, the active load circuit is equivalent to R _out , and the source impedance of the first NMOS transistor NM1 (the equivalent resistance of the third PMOS transistor PM3 and the equivalent resistance of the fourth PMOS transistor PM4 Parallel connection) is equivalent to R _s , the circuit is shown in Figure 3, this circuit is a typical common source amplifier circuit with source negative feedback resistance, and the gain A of the circuit is easily obtained from the auxiliary theorem:

A＝-G _m R _out (1)

Let G _m be the input equivalent transconductance of the input circuit, we can get:

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Where g _m1 is the transconductance of the first NMOS transistor NM1, when g _m1 >>1/R _s , G _m ≈1/R _s , that is:

A＝R _out /R _s (3)

It can be known from formulas (2) and (3) that when g _m1 >>1/R _s , the gain changes with the linear change of R _s , and the linearity of the circuit is high, but with the third NMOS transistor NM3 and the fourth The NMOS transistor NM4 gate voltage increases, the equivalent resistance R _s decreases, and g _m1 >> 1/R _s is no longer established, which will seriously affect the linearity of the circuit.

The function of the gm-boost circuit is analyzed below, that is, considering the functions of the third PMOS transistor PM3 and the fourth PMOS transistor PM4, the equivalent circuit of the present invention is shown in FIG. 4 , and the small signal model of the circuit in FIG. 4 is shown in FIG. 5 . The test signal V _t is added, the test current is I _t , r _o1 is the channel resistance of the first NMOS transistor NM1, g _mb1 is the equivalent transconductance of the first NMOS transistor NM1 lining bias effect, V _g3 is the third NMOS transistor NM3 Gate voltage, g _m3 is the transconductance of the third NMOS transistor NM3, r _o3 is the channel resistance of the third NMOS transistor NM3, assuming that the input signal Vin is 0, and V _g3 =V _out , according to the small signal model circuit in Figure 5 The KCL equation can be obtained:

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

Because R _out is much smaller than r _o1 , the resistance R _t seen from the source of the first NMOS transistor NM1 is obtained from equations (4) and (5):

$\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

It can be seen that, after introducing the gm-boost circuit, the impedance seen from the source of the first NMOS transistor NM1 is smaller than g _m3 *R _out in the case of only the source degeneration resistance (as shown in FIG. 3 ). Therefore, it can be known from the characteristics of the source follower circuit that the gain A _gs from the gate to the source of the first NMOS transistor NM1 is:

${\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

It can be easily known from the characteristics of a typical source follower circuit that after adding the gm-boost circuit, the input equivalent transconductance of the circuit increases by about g _m3 *R _out times, so the linearity of the circuit is improved.

Further as a preferred embodiment, the gain control circuit includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4, the gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4 are both connected to the gain control voltage terminal, the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to the source of the first NMOS transistor NM1, the drain of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 The drains are both connected to the source of the second NMOS transistor NM2.

Among them, 1/Rs is twice the sum of the equivalent admittances of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, namely:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

Where μ _n,3 and μ _n,4 are the carrier mobility in the third NMOS transistor NM3 and the fourth NMOS transistor NM4 respectively, C _ox,3 and C _ox,4 are respectively the third NMOS transistor NM3 and the fourth NMOS transistor NM4 The capacitance per unit area formed by the channel and the gate of the NMOS transistor NM4, and are respectively the width-to-length ratios of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, V _gs3 and V _gs4 are respectively the gate-source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, and V _TH3 and V _TH4 are respectively the The threshold voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4. V _ds5 and V _ds6 are the gate-drain voltages of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 respectively, and the gain of the VGA can be further written as:

A＝A3+A4 (11)

$\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

V _gs3 =V _gs4 =VC-V _ds5 =VC-V _ds6 (14)

Let x=VC, b ₁ ＝-V _ds5 -V _TH3 , b ₂ ＝-V _ds5 -V _TH4 , then the gain expression of VGA is:

A＝A3+A4 (15)

A3＝a ₁ (x+b ₁ ) (16)

A4＝a ₂ (x+b ₂ ) (17)

When the three-level VGA structure is used for cascading, the total gain expression of the entire VGA can be approximately equal to A _all by properly selecting the types and aspect ratios of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 . And by the mathematical formula:

a ⁿ (x+b) ⁿ ≈a ⁿ n ⁿ e ^x+bn (established when x≈nb) gets:

A _all ≈27a ³ e ^x+b-3 (18)

It can be seen from formula (18) that the VGA gain is A _all and the control voltage is x. According to this characteristic, the exponential relationship between the gain and the control voltage (dB linearity) can be realized. in

Further as a preferred embodiment, the current source circuit includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6, the gates of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are both connected to the bias voltage terminal, the source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6 are both connected to the ground, and the drain of the fifth NMOS transistor NM5 is connected to the source of the first NMOS transistor NM1 and the third PMOS transistor NM1 respectively. The drain of the transistor PM3, the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected, and the drain of the sixth NMOS transistor NM6 is respectively connected to the source of the second NMOS transistor NM2 and the fourth PMOS transistor NM2. The drain of the transistor PM4, the drain of the third NMOS transistor NM3, and the drain of the fourth NMOS transistor NM4 are connected.

Among them, the active load is separated for independent analysis, as shown in Figure 6, and the small signal model of the active load circuit is shown in Figure 7. Among them, r _o1 , r _o2 , r _o5 and r _o6 are the channel resistances of the first PMOS transistor PM1, the second PMOS transistor PM2, the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 respectively, and V _g5 and V _g6 are respectively The gate voltage of the fifth PMOS transistor PM5 and the sixth PMOS transistor _PM6 , gm is the transconductance of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6. The s-domain analysis of the above circuit has:

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 19</span>}<span\; class="notranslate">\; )</span>$

$<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 20</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; twenty\; one</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; twenty\; two</span>}<span\; class="notranslate">\; )</span>$

Let R1=R2=R0, C1=C2=C, R3=R4=R, r _o1 =r _o2 , r _o5 =r _o6 . Due to the symmetry of the circuit, it can be obtained from formulas (19)-(22):

$\mathrm{<span\; class="notranslate">\; Z</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; \&lsqb;</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; \&rsqb;</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; twenty\; three</span>}<span\; class="notranslate">\; )</span>$

From formula (23), it can be known that active loads will introduce zeros and poles, among which the zeros we focus on are:

${\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; twenty\; four</span>}<span\; class="notranslate">\; )</span>$

Properly tuned, the newly introduced zero cancels out the dominant pole, increasing gain and extending bandwidth.

Referring to Fig. 2, in the embodiment of the present invention, three variable gain amplifiers of the present invention can be used for cascading. The three variable gain amplifiers have the same structure but different device parameters. They are designed in a 180nm CMOS process and directly coupled to form a VGA output Linear approximation in dB with input. The output terminal of the first variable gain amplifier is further connected to the input terminal of the third variable gain amplifier through the second variable gain amplifier, so that the second variable gain amplifier amplifies the output signal of the first variable gain amplifier, and then The third variable gain amplifier amplifies the output signal of the second variable gain amplifier, and the three variable gain amplifiers are connected to the same gain control voltage terminal, so that the whole variable gain amplifier has a relatively high frequency through the three variable gain amplifiers. high gain.

Referring to FIG. 8 and FIG. 9 , the post-simulation of the circuit in this embodiment shows that the highest gain is 67dB, and the minimum -3dB bandwidth is 125MHz (as shown in FIG. 8 ). Different control voltage VC can change the gain of VGA (as shown in Figure 9). The VC of the control voltage and the gain of VGA have a wider dB linear range: -25dB to 37dB, that is, 62dB (as shown in Figure 10). The fitting of the dB linear curve and the dB linear error are shown in Figure 11 and Figure 12. In the dB linear range -25dB to 37dB, the dB linear error is less than ±1dB.

As can be seen from the foregoing, a novel low-complexity broadband variable gain amplifier of the present invention can realize the dB linear relationship between the output and the input without an exponential generating circuit, and effectively enhances the equivalent input transconductance of the VGA through the gm-boost circuit, The VGA can have higher linearity and a wider dB linear range, and at the same time, the bandwidth of the VGA can be greatly expanded without increasing the power consumption of the VGA through an active load circuit.

The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. , these equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (6)

1. A novel low-complexity broadband variable gain amplifier is characterized in that: it comprises an active load circuit, a current source circuit, a differential input circuit, a gm-boost circuit and a gain control circuit, and the active load circuit is respectively connected to gm - the boost circuit is connected to the differential input circuit, and the current source circuit is respectively connected to the differential input circuit, the gm-boost circuit and the gain control circuit. 2. A novel low-complexity broadband variable gain amplifier according to claim 1, wherein said active load circuit comprises a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor Transistors, first resistors, second resistors, third resistors, fourth resistors, first capacitors, and second capacitors, the source of the first PMOS transistor, the source of the second PMOS transistor, and the source of the fifth PMOS transistor The gate of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to the power supply terminal, the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor through the third resistor, and the gate of the sixth PMOS transistor is connected to the gate of the sixth PMOS transistor through the fourth resistor. The resistor is connected to the gate of the second PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the first PMOS transistor is connected to the first PMOS transistor through a first resistor the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor through a second resistor, the gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor through a first capacitor, The gate of the sixth PMOS transistor is connected to the drain of the first PMOS transistor through the second capacitor, and the drain of the first PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the differential input circuit and the gm-boost circuit connected, the drain of the second PMOS transistor is respectively connected to the drain of the sixth PMOS transistor, the differential input circuit and the gm-boost circuit, the drain of the first PMOS transistor is connected to the negative output terminal, and the second The drain of the PMOS transistor is connected to the positive output. 3. A novel low-complexity broadband variable gain amplifier according to claim 2, characterized in that: the differential input circuit comprises a first NMOS transistor and a second NMOS transistor, and the drain of the first NMOS transistor is connected to the second NMOS transistor. The drain of a PMOS transistor is connected, the source of the first NMOS transistor is connected with the gm-boost circuit, the gain control circuit and the current source circuit respectively, the drain of the second NMOS transistor is connected with the second PMOS transistor The drain is connected, the source of the second NMOS transistor is connected to the gm-boost circuit, the gain control circuit and the current source circuit respectively, the gate of the first NMOS transistor is connected to the positive input terminal, and the second NMOS transistor is connected to the positive input terminal. The gate of the NMOS transistor is connected to the negative input. 4. a kind of novel low-complexity broadband variable gain amplifier according to claim 3, is characterized in that: described gm-boost circuit comprises the 3rd PMOS transistor and the 4th PMOS transistor, the source of described 3rd PMOS transistor Both the pole and the source of the fourth PMOS transistor are connected to the power supply terminal, the gate of the third PMOS transistor is connected to the drain of the first NMOS transistor and the drain of the first PMOS transistor respectively, and the drain of the third PMOS transistor The drain of the first NMOS transistor is connected to the source, the gate of the fourth PMOS transistor is respectively connected to the drain of the second NMOS transistor and the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor The pole is connected to the source of the second NMOS transistor. 5. a kind of novel low-complexity broadband variable gain amplifier according to claim 4, is characterized in that: described gain control circuit comprises the 3rd NMOS transistor and the 4th NMOS transistor, the gate of described 3rd NMOS transistor and the gate of the fourth NMOS transistor are connected to the gain control voltage terminal, the source of the third NMOS transistor and the source of the fourth NMOS transistor are connected to the source of the first NMOS transistor, and the third NMOS transistor Both the drain of the fourth NMOS transistor and the drain of the fourth NMOS transistor are connected to the source of the second NMOS transistor. 6. A novel low-complexity wideband variable gain amplifier according to claim 5, characterized in that: said current source circuit comprises a fifth NMOS transistor and a sixth NMOS transistor, and the gate of said fifth NMOS transistor and the gates of the sixth NMOS transistor are connected to the bias voltage terminal, the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected to the ground, and the drains of the fifth NMOS transistor are respectively connected to the first The source of an NMOS transistor, the drain of the third PMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are connected, and the drain of the sixth NMOS transistor is connected to the source of the second NMOS transistor respectively. electrode, the drain of the fourth PMOS transistor, the drain of the third NMOS transistor and the drain of the fourth NMOS transistor are connected.