CN106057822A - Array substrate, manufacturing method thereof and display device - Google Patents

Abstract

The present invention provides an array substrate, a manufacturing method thereof, and a display device, which include a passivation layer, a buffer layer, and a metal reflective layer sequentially arranged from bottom to top, and the buffer layer includes at least one first buffer layer and a first buffer layer arranged on it. There is at least one second buffer layer on top, and the densities of the two are different. The array substrate provided by the present invention can avoid the problem that the lower metal layer is corroded by the metal etching solution, thereby improving product yield and reducing product cost.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

At present, a thin film transistor liquid crystal display (TFT-LCD) has been widely used in various flat panel displays, mobile displays, televisions and other products.

FIG. 1 is a schematic structural diagram of an existing array substrate. Please refer to FIG. 1, the array substrate includes a gate electrode layer 1, a gate insulating layer 2, an active layer 3, an S/D metal layer (4, 5), a passivation layer 6, and two ITO layers (7) from bottom to top. , 8) and metal reflective layer 9.

In the process of manufacturing the above-mentioned array substrate, two ITO layers (7, 8) are arranged in the crimping area, and cover the via hole 10 in the passivation layer 6, and are used as a wiring bonding layer to overlap the control circuit ( IC). The metal reflective layer 9 is used as a reflective layer and an electrode layer, and it is only arranged in the display area, but not in the crimping area (not covered in the via hole 10 of the passivation layer 6), so as to avoid the crimping and detachment of the control circuit. Therefore, During the process of manufacturing the metal reflective layer 9 , it is necessary to use a metal etchant to remove the metal layer in the crimping area.

But, because the film quality (density) of two ITO layers (7,8) is identical, when using metal etchant to etch the metal layer of crimping region (via hole 10 is positioned at this region), metal etchant It will penetrate through the two ITO layers (7, 8) and corrode the lower metal layer, for example, penetrate into the S/D metal layer through the via hole 10, thereby causing poor contact of the circuit and generating defects such as dark lines.

Contents of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an array substrate, a manufacturing method thereof, and a display device, which can avoid the problem that the lower metal layer is corroded by a metal etching solution, thereby improving product quality. Yield, reduce product cost.

In order to realize the object of the present invention, an array substrate is provided, comprising a passivation layer, a buffer layer and a metal reflective layer sequentially arranged from bottom to top, and the buffer layer includes at least one first buffer layer and a At least one second buffer layer, the densities of the two are different.

Optionally, the first buffer layer is a crystal of ITO; the second buffer layer is an amorphous ITO.

Optionally, both the first buffer layer and the second buffer layer are crystals of ITO; or,

Both the first buffer layer and the second buffer layer are amorphous ITO.

Optionally, the first buffer layer is a crystal of ITO or an amorphous body of ITO, and a smooth layer after plasma treatment is formed on the surface of the first buffer layer in contact with the second buffer layer;

The second buffer layer is a crystal of ITO or an amorphous body of ITO, and the density of the smoothing layer is different from that of the second buffer layer.

Optionally, the metal reflective layer includes any one of Al, Mo, Cu, Ti, Nb or an alloy composed of at least two of them.

Optionally, the passivation layer includes SiNx, SiOx or SiON.

As another technical solution, the present invention also provides a method for manufacturing an array substrate, including the following steps:

forming a buffer layer on the passivation layer;

forming a metal reflective layer on the buffer layer;

Wherein, the buffer layer includes at least one first buffer layer and at least one second buffer layer disposed thereon, and the densities of the two are different.

Optionally, the first buffer layer is a crystal of ITO; the second buffer layer is an amorphous ITO.

Optionally, both the first buffer layer and the second buffer layer are crystals of ITO; or,

Both the first buffer layer and the second buffer layer are amorphous ITO.

Optionally, the film forming power used to form the first buffer layer is lower than the film forming power used to form the second buffer layer; meanwhile, the film forming pressure used to form the first buffer layer is higher than The film-forming pressure adopted for forming the second buffer layer.

Optionally, the first buffer layer is a crystal of ITO or an amorphous ITO; the second buffer layer is a crystal of ITO or an amorphous ITO;

After forming the first buffer layer and before forming the second buffer layer, further comprising:

Plasma treatment is performed on the surface of the first buffer layer that is in contact with the second buffer layer to form a smooth layer; and the density of the smooth layer is different from that of the second buffer layer.

As another technical solution, the present invention also provides a display device, including an array substrate, and the array substrate adopts the above-mentioned array substrate provided by the present invention.

The present invention has the following beneficial effects:

In the array substrate provided by the present invention, the buffer layer disposed between the passivation layer and the metal reflective layer includes at least one first buffer layer and at least one second buffer layer disposed thereon, and by making the two Different densities can avoid overlapping grain boundary defects of the first buffer layer and the second buffer layer, thereby preventing the metal etchant from passing through the buffer layer and corroding the lower metal layer, thereby improving product yield and reducing product cost.

In the manufacturing method of the array substrate provided by the present invention, the buffer layer disposed between the passivation layer and the metal reflective layer includes at least one first buffer layer and at least one second buffer layer disposed thereon, and by making The density of the two is different, which can avoid the overlap of grain boundary defects in the first buffer layer and the second buffer layer, thereby preventing the metal etching solution from passing through the buffer layer and corroding the lower metal layer, thereby improving the product yield and reducing the Product Cost.

The display device provided by the present invention can prevent the metal etchant from passing through the buffer layer and corroding the lower metal layer by using the above-mentioned array substrate provided by the present invention, thereby improving product yield and reducing product cost.

Description of drawings

FIG. 1 is a schematic structural view of an existing array substrate;

FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.

detailed description

In order for those skilled in the art to better understand the technical solution of the present invention, the array substrate provided by the present invention and its manufacturing method will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention. Please refer to Figure 2, the array substrate includes gate electrode layer 1, gate insulating layer 2, active layer 3, S/D metal layer (4, 5), passivation layer 6, buffer layer and metal reflective layer from bottom to top 9. Wherein, the metal reflection layer 9 is located in the reflection area of the array substrate and on the right side of the via hole 10 of the passivation layer 6 .

In this embodiment, the buffer layer includes a first buffer layer 11 and a second buffer layer 12 disposed thereon, and the densities of the two are different. This can avoid the overlapping of the grain boundary defects of the first buffer layer 11 and the second buffer layer 12, so that the etchant of the metal reflective layer 9 above the buffer layer can be prevented from passing through the buffer layer and corroding the lower metal layer, thereby It can improve product yield and reduce product cost.

The specific implementation manners of the first buffer layer 11 and the second buffer layer 12 will be described in detail below. Specifically, in the first embodiment, the first buffer layer 11 is a crystal of ITO (P-ITO); the second buffer layer 12 is an amorphous ITO (A-ITO). Because the compactness of the crystalline body of ITO is higher than the amorphous body of ITO, the compactness of the two is different, thereby can avoid the grain boundary defect overlap of the first buffer layer 11 and the second buffer layer 12, and because the compactness of the crystalline body of ITO is more High, by making it closer to the underlying passivation layer 6, it is more conducive to protecting the underlying metal layer, thereby further enhancing the blocking effect on the metal etchant.

In the second embodiment, both the first buffer layer 11 and the second buffer layer 12 are crystals of ITO; or, both the first buffer layer and the second buffer layer are amorphous ITO. That is to say, both the first buffer layer 11 and the second buffer layer 12 adopt the crystal body of ITO or the amorphous body of ITO, but the densities of the two are different, which can also avoid the first buffer layer 11 and the second buffer layer 12. Grain boundary defects overlap. Preferably, the density of the first buffer layer 11 can be made higher than that of the second buffer layer 12, so as to further enhance the blocking effect on the metal etchant.

In a third embodiment, the first buffer layer 11 is a crystal of ITO or an amorphous ITO, and a plasma-treated smoothing layer is formed on the surface of the first buffer layer 11 that is in contact with the second buffer layer 12 . The second buffer layer 12 is a crystal of ITO or an amorphous body of ITO, and the density of the smoothing layer is different from that of the second buffer layer 12 , so that overlapping of grain boundary defects between the first buffer layer 11 and the second buffer layer 12 can be avoided. The so-called plasma treatment refers to the physical and chemical reaction between the plasma and the surface of the first buffer layer 11 which is in contact with the second buffer layer 12 , so as to form a cleaner and smoother smooth layer on the surface.

It should be noted that, in the above three implementation manners, the number of each of the first buffer layer 11 and the second buffer layer 12 can be one or more than two layers.

In practical applications, optionally, the metal reflective layer 9 includes any one of Al, Mo, Cu, Ti, Nb or an alloy composed of at least two of them.

In practical applications, optionally, the passivation layer 6 includes SiNx, SiOx or SiON and so on.

As another technical solution, the present invention also provides a method for manufacturing an array substrate, which includes the following steps:

A buffer layer is formed on the passivation layer.

A metal reflective layer is formed on the buffer layer.

Wherein, the buffer layer includes at least one first buffer layer and at least one second buffer layer disposed thereon, and the densities of the two are different. This can avoid the overlapping of grain boundary defects of the first buffer layer and the second buffer layer, thereby avoiding the etchant of the metal reflective layer above the buffer layer from passing through the buffer layer and corroding the underlying metal layer, thereby improving the product quality. Yield, reduce product cost.

Optionally, the above-mentioned first buffer layer is a crystal of ITO; the second buffer layer is an amorphous body of ITO. Since the density of the ITO crystal is higher than that of the ITO amorphous body, the density of the two is different, so that the overlap of grain boundary defects in the first buffer layer and the second buffer layer can be avoided, and because the ITO crystal has a higher density, By arranging it in the lower layer of the ITO amorphous body, the blocking effect on the metal etching solution can be further enhanced.

Optionally, both the first buffer layer and the second buffer layer are crystals of ITO; or, both the first buffer layer and the second buffer layer are amorphous ITO. That is to say, both the first buffer layer and the second buffer layer adopt ITO crystal or ITO amorphous, but the densities of the two are different, which can also avoid the overlapping of grain boundary defects in the first buffer layer and the second buffer layer . Preferably, the density of the first buffer layer can be higher than that of the second buffer layer, so as to further enhance the blocking effect on the metal etchant.

Preferably, the method for making the density of the first buffer layer higher than that of the second buffer layer is specifically: the film-forming power used to form the first buffer layer is lower than the film-forming power used to form the second buffer layer; at the same time, forming The film-forming pressure used for the first buffer layer is higher than the film-forming pressure used for forming the second buffer layer.

Optionally, the first buffer layer is ITO crystal or ITO amorphous; the second buffer layer is ITO crystal or ITO amorphous. Moreover, after forming the first buffer layer and before forming the second buffer layer, it also includes:

The surface of the first buffer layer in contact with the second buffer layer is subjected to plasma treatment to form a flat layer, which has a different density from the second buffer layer, so that the first buffer layer and the second buffer layer can be avoided. Grain boundary defects overlap. The so-called plasma treatment refers to the physical and chemical reaction between the plasma and the surface of the first buffer layer in contact with the second buffer layer, so as to form a cleaner and smoother smooth layer on the surface.

The structure of the array substrate obtained by using the manufacturing method of the array substrate provided in the embodiment of the present invention is the same as that of the array substrate provided in the embodiment of the present invention, as shown in FIG. The scheme has already been described in detail and will not be described in detail here.

The manufacturing method of the array substrate provided by the embodiment of the present invention can avoid overlapping grain boundary defects of the first buffer layer and the second buffer layer, thereby preventing the metal etchant from passing through the buffer layer and corroding the lower metal layer, and furthermore Improve product yield and reduce product cost.

As another technical solution, an embodiment of the present invention further provides a display device, including an array substrate, and the array substrate adopts the above-mentioned array substrate provided by the embodiment of the present invention.

In the display device provided by the embodiment of the present invention, by using the above-mentioned array substrate provided by the embodiment of the present invention, the metal etching solution can be prevented from passing through the buffer layer and corroding the lower metal layer, thereby improving product yield and reducing product cost.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (12)

1. An array substrate, comprising a passivation layer, a buffer layer and a metal reflective layer arranged sequentially from bottom to top, characterized in that the buffer layer includes at least one first buffer layer and at least one buffer layer arranged thereon The second buffer layer has different densities. 2 . The array substrate according to claim 1 , wherein the first buffer layer is a crystal of ITO; the second buffer layer is an amorphous ITO. 3. The array substrate according to claim 1, wherein both the first buffer layer and the second buffer layer are crystals of ITO; or, Both the first buffer layer and the second buffer layer are amorphous ITO. 4. The array substrate according to claim 1, wherein the first buffer layer is a crystal of ITO or an amorphous body of ITO, and the first buffer layer is in contact with the second buffer layer. A flat layer after plasma treatment is formed on the surface; The second buffer layer is a crystal of ITO or an amorphous body of ITO, and the density of the smoothing layer is different from that of the second buffer layer. 5. The array substrate according to any one of claims 1-4, wherein the metal reflective layer comprises any one of Al, Mo, Cu, Ti, Nb or an alloy composed of at least two of them. 6. The array substrate according to any one of claims 1-4, wherein the passivation layer comprises SiNx, SiOx or SiON. 7. A method for manufacturing an array substrate, comprising the following steps: forming a buffer layer on the passivation layer; forming a metal reflective layer on the buffer layer; Wherein, the buffer layer includes at least one first buffer layer and at least one second buffer layer disposed thereon, and the densities of the two are different. 8 . The manufacturing method of the array substrate according to claim 7 , wherein the first buffer layer is a crystal of ITO; the second buffer layer is an amorphous ITO. 9. The method for manufacturing an array substrate according to claim 7, wherein both the first buffer layer and the second buffer layer are crystals of ITO; or, Both the first buffer layer and the second buffer layer are amorphous ITO. 10. The method for manufacturing the array substrate according to claim 9, wherein the film forming power used for forming the first buffer layer is lower than the film forming power used for forming the second buffer layer; meanwhile, The film forming pressure used for forming the first buffer layer is higher than the film forming pressure used for forming the second buffer layer. 11. The manufacturing method of the array substrate according to claim 7, wherein the first buffer layer is a crystal of ITO or an amorphous ITO; the second buffer layer is a crystal of ITO or an amorphous ITO ; After forming the first buffer layer and before forming the second buffer layer, further comprising: Plasma treatment is performed on the surface of the first buffer layer that is in contact with the second buffer layer to form a smooth layer; and the density of the smooth layer is different from that of the second buffer layer. 12. A display device, comprising an array substrate, wherein the array substrate is the array substrate according to any one of claims 1-6.