CN106057731B - 3D global pixel unit and preparation method thereof - Google Patents

Abstract

The present invention provides a kind of 3D overall situation pixel units and preparation method thereof, including the photosensitive region arranged on vertical direction and the storage of 10T signal and reading region；The interconnection connected to realize light sensitive diode and signal storage and reading circuit that structure is directly connected to structure with second is directly connected to by the connection of the first dielectric layer and the second dielectric layer, first；By the first, second, third and fourth switching tube according to certain timing, reset switch and transfer tube are stored respectively on the first, second sampling capacitance, the signal voltage obtained in time for exposure is stored in pixel unit by final realization to be read again for a period of time, to realize the global shutter exposure of entire pixel unit array；The perpendicular interconnection of 10T signal storage and reading circuit and light sensitive diode may be implemented in the present invention, not only increases the extraneous light-path with light sensitive diode, improves the optical isolation degree of signal storage capacitance, and reduce the occupied chip area of pixel unit.

Description

3D global pixel unit and preparation method thereof

technical field

The invention relates to the technical field of semiconductor image sensing, in particular to a 3D global pixel unit and a preparation method thereof.

Background technique

Traditional global shutter pixel technology is mainly used in CCD image sensors. Due to the growing popularity of CMOS image sensors, and because machine vision, film production, industrial, automotive, and scanning applications must capture fast-moving objects with high image quality, major image sensor manufacturers have worked to overcome the use of global Related traditional barriers to shutter pixel technology. With this effort, the provided global shutter pixel technology with smaller pixel size, larger fill factor, lower dark current, and lower noise makes CMOS image sensors the best choice for CCD sensors in more applications. viable alternative.

In the global pixel unit of a conventional CMOS image sensor, the photosensitive diode and the signal storage and readout circuit unit devices are all made in the same plane. The storage unit needs to occupy a large area to make the capacitor for storing the signal, so the area of the global pixel is always difficult to reduce, and the filling factor is always small. In addition, the photosensitive unit, the storage capacitor and the readout circuit are prone to interfere with each other.

SUMMARY OF THE INVENTION

In order to overcome the above problems, the present invention aims to provide a global pixel unit with a 3D structure and a preparation method thereof. By adopting a back-illumination process and a 3D structure, a three-dimensional unit structure is fabricated at different levels, which can realize the vertical alignment between the signal readout circuit and the photosensitive diode. interconnection.

In order to achieve the above object, the present invention provides a 3D global pixel unit, which is characterized in that it at least includes a photosensitive area located in the first silicon substrate layer (06) and a 10T signal storage and readout area located in the second silicon substrate layer (15). The output circuit area is characterized in that the photosensitive area and the 10T signal storage and readout circuit area are arranged in the vertical direction; wherein,

The photosensitive area includes:

an anti-reflection coating (07), a color filter layer (08) and a microlens (09) arranged in sequence from bottom to top on the back of the first silicon substrate layer (06);

A photodiode (05) and a first dielectric layer (01) are arranged in sequence from top to bottom on the front surface of the first silicon substrate layer (06), and isolation trenches filled with a dielectric are provided on both sides of the photodiode (05) slot(04);

The first dielectric layer (01) has a first through hole (03) and a first direct connection structure (02). One end of the first through hole (03) is connected to the photosensitive diode (05), and the other end is connected to the photosensitive diode (05). connecting the first direct connection structure (02);

Metal is deposited in the first direct connection structure (02) and the first through hole (03), the metal bottom surface of the first direct connection structure (02) and the bottom of the first dielectric (06) layer surface flush;

The 10T signal storage and readout circuit unit area includes:

a third dielectric layer (14), a light shielding layer (13), and a second dielectric layer (12) arranged in sequence from bottom to top on the back of the second silicon substrate layer (15);

A 10T signal storage and readout circuit (18) and a fourth dielectric layer (19) located below the 10T signal storage and readout circuit (18) are sequentially arranged on the front surface of the second silicon substrate layer (15) from top to bottom and a metal layer (M) under the fourth dielectric layer (19); wherein,

A second direct connection structure (10) is connected to the top of the second through hole (11), and the second through hole (11) passes through the second dielectric layer (12), the light shielding layer (13), and the third dielectric layer (14) a second silicon substrate (15), wherein the sidewall of the second through hole (11) has a fifth dielectric layer (17);

One end of the second through hole (11) is connected with the second direct connection structure (10), and the other end is connected with the 10T signal storage and readout circuit (18);

Metal is deposited in the second direct connection structure (10) and the second via (03), and the metal top surface of the second direct connection structure (10) and the second dielectric layer (12) the top surface is flush;

The fourth dielectric layer (19) is used for isolation between the 10T signal storage and readout circuit (18) and the metal layer (M); the 10T signal storage and readout circuit (18) is connected by A hole (CT) is interconnected with the metal layer (M);

The second direct connection structure (10) is connected with the first direct connection structure (02), and the first dielectric layer (01) is connected with the second dielectric layer (12); wherein,

The 10T signal storage and readout circuit includes: a reset switch, a first sampling capacitor, a second sampling capacitor, a transmission tube, a first source follower, a precharge tube, a first switch tube, a second switch tube, and a third switch tube, the fourth switch tube, the second source follower, the row selector; the drain of the reset switch is connected to the reset voltage, the gate of the reset switch is connected to the pixel input terminal, and the source of the reset switch is connected to the transfer tube , the drain of the transfer tube is connected to the cathode of the pinned photodiode, the gate of the transfer tube is connected to the input terminal of the pixel unit; the drain of the first source follower is connected to VDD, the first source The source of the follower is connected to the drain of the charger, the source of the charger is grounded, and the gate of the charger is connected to the pixel input; the source of the first source follower and the precharge tube The drain of the first switch is connected to the drain of the first switch and the drain of the second switch, and the source of the first switch is connected to the drain of the first sampling capacitor and the third switch. The drain of the second switch is connected to the first sampling capacitor and the fourth switch, and the source of the fourth switch is connected to the source of the third switch. and the gate of the second source follower is connected to the gate of the second source follower, the source of the second source follower is connected to the drain of the row selector; the gate of the precharge tube is the input end of the pixel unit, and the first The gates of a switch tube, the second switch tube, the third switch tube and the fourth switch tube are respectively connected to the input end of the pixel unit, the other end of the first sampling capacitor and the second sampling The other end of the capacitor is grounded; the drain of the second source follower is connected to VDD, the gate of the row selector is the input terminal of the pixel unit, and the source of the row selector is the output terminal of the entire pixel unit.

Preferably, the materials of the first dielectric layer and the second dielectric layer are both insulating materials.

Preferably, the material of the first dielectric layer and the second dielectric layer is silicon oxide.

Preferably, the material of the silicon substrate is single crystal silicon.

In order to achieve the above object, the present invention also provides a method for preparing the above-mentioned 3D global pixel unit, which includes the preparation process of the photosensitive unit area, the preparation process of the 10T signal storage and readout circuit area, and the connection process ;in,

The preparation process of the photosensitive region includes:

Step 101: depositing a first dielectric layer on the front side of the first silicon substrate layer; then, preparing the first direct connection structure and the first through hole in the first dielectric layer;

Step 102: thinning the back surface of the first silicon substrate layer;

Step 103: perform ion implantation into the back of the first silicon substrate layer to prepare the photosensitive diode, so that the photosensitive diode is connected to the first through hole; and, prepare the photosensitive diode around the photosensitive diode isolating trenches, and filling the isolation trenches with a dielectric;

Step 104: depositing an anti-reflection coating on the back of the first silicon substrate layer after completing the step 103, and then forming the color filter layer and the microlens on the anti-reflection coating in sequence;

The preparation process of the 10T signal storage and readout circuit area includes:

Step 201 : forming the 10-signal storage and readout circuit on the front side of the second silicon substrate layer, and forming a fourth dielectric layer on the surface of the 10T signal storage and readout circuit, and then, on the fourth dielectric forming the contact hole in the layer, and forming the metal layer on the surface of the fourth dielectric layer and the contact hole;

Step 202: thinning the back surface of the second silicon substrate layer;

Step 203 : forming the third dielectric layer, the light shielding layer and the second dielectric layer in sequence on the back of the second silicon substrate layer;

Step 204: forming a second through hole in the 10T signal storage and readout circuit, the second silicon substrate layer, the third dielectric layer, the light shielding layer and the second dielectric layer;

Step 205 : forming the fifth dielectric layer on the sidewall of the second through hole, and filling the second through hole with metal;

Step 206 : preparing the second direct connection structure in the second dielectric layer, and filling the second direct connection structure with metal;

The connection process includes: connecting the first direct connection structure of the photosensitive diode with the second direct connection structure of the 10T signal storage and readout circuit area, and connecting the first dielectric layer of the photosensitive area to the second direct connection structure of the photosensitive area. The 10T signal storage is connected to the second dielectric layer of the readout circuit region; wherein,

The 10T signal storage and readout circuit includes: a reset switch, a first sampling capacitor, a second sampling capacitor, a transmission tube, a first source follower, a precharge tube, a first switch tube, a second switch tube, and a third switch tube, the fourth switch tube, the second source follower, the row selector; the drain of the reset switch is connected to the reset voltage, the gate of the reset switch is connected to the pixel input terminal, and the source of the reset switch is connected to the transfer tube , the drain of the transfer tube is connected to the cathode of the pinned photodiode, the gate of the transfer tube is connected to the input terminal of the pixel unit; the drain of the first source follower is connected to VDD, the first source The source of the follower is connected to the drain of the charger, the source of the charger is grounded, and the gate of the charger is connected to the pixel input; the source of the first source follower and the precharge tube The drain of the first switch is connected to the drain of the first switch and the drain of the second switch, and the source of the first switch is connected to the drain of the first sampling capacitor and the third switch. The drain of the second switch is connected to the first sampling capacitor and the fourth switch, and the source of the fourth switch is connected to the source of the third switch. and the gate of the second source follower is connected to the gate of the second source follower, the source of the second source follower is connected to the drain of the row selector; the gate of the precharge tube is the input end of the pixel unit, and the first The gates of a switch tube, the second switch tube, the third switch tube and the fourth switch tube are respectively connected to the input end of the pixel unit, the other end of the first sampling capacitor and the second sampling The other end of the capacitor is grounded; the drain of the second source follower is connected to VDD, the gate of the row selector is the input terminal of the pixel unit, and the source of the row selector is the output terminal of the entire pixel unit.

Preferably, in the step 101, a Damascus process is used to prepare the first direct connection structure and the first through hole.

Preferably, in the step 103, a chemical vapor deposition process is used to fill the isolation trenches with a dielectric.

Preferably, in the step 104, an anti-reflection layer is coated or deposited on the backside of the first silicon substrate layer.

Preferably, the step 205 specifically includes:

Step 2051: depositing the fifth dielectric layer on the bottom and sidewalls of the second through hole and on the surface of the second dielectric layer;

Step 2052: Using photolithography and etching processes, etch and remove the fifth dielectric layer on the bottom of the second through hole and the surface of the second dielectric layer, and retain the fifth dielectric layer on the sidewall of the second through hole. Five dielectric layers;

Step 2053: Electroplating a seed layer and a filling metal in sequence in the second through hole.

The global pixel unit of the 3D structure and the preparation method thereof of the present invention can realize the vertical interconnection between the 10T signal readout circuit and the photosensitive diode by adopting the back-illumination process and the 3D structure to make the three-dimensional unit structure at different levels; The optical path between the outside world and the photosensitive diode improves the optical isolation of the signal storage capacitor and reduces the chip area occupied by the pixel unit.

Description of drawings

1 is a schematic cross-sectional structure diagram of a 3D global pixel unit according to a preferred embodiment of the present invention

2 is a schematic structural diagram of a 10T signal and a storage circuit of a 3D global pixel unit according to a preferred embodiment of the present invention

3 is a schematic flowchart of a method for preparing a 3D global pixel unit according to a preferred embodiment of the present invention

4-13 are schematic diagrams of various steps of a method for preparing a 3D global pixel unit according to a preferred embodiment of the present invention

Detailed ways

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below with reference to the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general substitutions known to those skilled in the art are also covered within the protection scope of the present invention.

In the present invention, the photosensitive unit of the first silicon substrate layer and the signal storage and readout unit of the second silicon substrate layer are arranged in the vertical direction, and the photosensitive unit is located above the signal storage and readout unit; through the first dielectric layer The connection with the second dielectric layer and the connection between the first direct connection structure and the second direct connection structure realize the interconnection of the photosensitive unit and the signal storage and readout unit.

The present invention will be further described in detail below with reference to the accompanying drawings 1-13 and specific embodiments. It should be noted that, the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly achieve the purpose of assisting the description of the present embodiment.

In this embodiment, please refer to FIG. 1, the 3D 10T global pixel unit includes at least first, second, third, fourth, and fifth dielectric layers 01, 12, 14, 19, and 17, a first through hole 03, and a second through hole 11. The contact hole CT and the first direct connection structure 02 and the second direct connection structure 10; the photosensitive unit and the signal storage and readout circuit unit are arranged in the vertical direction; wherein, the photosensitive area (the upper dotted frame in FIG. 1 ) is located in the The first silicon substrate layer, the signal storage and readout circuit unit area (the lower dotted frame in FIG. 1 ) is located in the second silicon substrate layer;

The photosensitive area includes: microlenses 09, color filter layers 08, and anti-reflection coatings 07 arranged in order from top to bottom on the back of the first silicon substrate 06; photosensitive diodes 05 arranged in order from top to bottom on the front of the first silicon substrate 06 (that is, a photosensitive unit, in this embodiment, a photosensitive diode can be used as a photosensitive unit but not limited to), the first dielectric layer 01 located on the surface of the photosensitive diode 05, and the isolation trench 04 filled with dielectric on both sides of the photosensitive diode 05; A dielectric layer 01 has a first through hole 03 and a first direct connection structure 02. One end of the first through hole 03 is connected to the photodiode 05, and the other end is connected to the first direct connection structure 02; the first direct connection structure 02 and the first direct connection structure 02 Metal is deposited in the through holes 03, and the bottom surface of the metal of the first direct connection structure 02 is flush with the bottom surface of the first dielectric layer 06;

The 10T signal storage and readout circuit area includes: the second dielectric layer 12, the light shielding layer 13, and the third dielectric layer 14, which are arranged in sequence from top to bottom on the back of the second silicon substrate layer 15; the 10T signal storage and readout circuit can be Prepared by standard CMOS process;

The 10T signal storage and readout circuit 18, the fourth dielectric layer 19 located above it, and the metal layer M located above the fourth dielectric layer 19 are sequentially arranged on the front surface of the second silicon substrate layer 15 from top to bottom;

Wherein, the second dielectric layer 12 has a second through hole 11 and a second direct connection structure 10, the top of the second pupil 11 is connected with a second direct connection structure 10, and the second through hole 11 passes through the second dielectric layer 12, the light The shielding layer 13, the third dielectric layer 14, the second silicon substrate 15, and the sidewall of the second through hole 11 has a fifth dielectric layer 17;

One end of the second through hole 11 is connected to the second direct connection structure 10, and the other end is connected to the signal storage and readout circuit unit 18;

Metal is deposited in both the second direct connection structure 10 and the second through hole 03, and the metal top surface of the second direct connection structure 10 is flush with the top surface of the second dielectric layer 12;

The fourth dielectric layer 19 is used for isolation between the 10T signal storage and readout circuit 18 and the metal layer M; the metal layer M here is a metal layer that can be interconnected later;

The 10T signal storage and readout circuit 18 is interconnected with the metal layer M through the contact hole CT;

The second direct connection structure 10 is connected to the first direct connection structure 02 , and the first dielectric layer 01 is connected to the second dielectric layer 12 . Here, the active and inactive regions 16 in the backside of the second silicon substrate layer 15 are also included. Preferably, the materials of the first dielectric layer 01 and the second dielectric layer 12 are both insulating materials, such as oxides, and the active regions in the active and passive regions 16 are P-type doped active regions. The second through hole 11 may be fabricated by using a through silicon via process (Through Silicon Via).

In this embodiment, please refer to FIG. 2, the 10T signal storage and readout circuit 18 includes: a reset switch M1, a first sampling capacitor C1, a second sampling capacitor C2, a transmission transistor M2, a first source follower SF1 (M3), Precharge tube M4, first switch tube M5, second switch tube M6, third switch tube M7, fourth switch tube M8, second source follower SF2 (M9), row selector M10; drain of reset switch M1 Connect the reset voltage Vreset, the gate of the reset switch M1 is connected to the pixel input terminal RX, the source of the reset switch M1 is connected to the source (FD node) of the transfer tube M2, the drain of the transfer tube M2 is connected to the cathode of the photodiode, and the transfer tube The gate of M2 is connected to the input terminal TG of the pixel unit; the drain of the first source follower SF1 (M3) is connected to VDD, the source of the first source follower SF1 (M3) is connected to the drain of the pre-charging tube M4, The source of the charging tube M4 is grounded, the gate of the pre-charging tube M4 is connected to the pixel input terminal PC; the source of the first source follower SF1 (M3), the drain of the pre-charging tube M4 and the drain of the first switching tube M5 , The drain of the second switch M6 is connected, the source of the first switch M5 is connected to the drain of the first sampling capacitor C1, the drain of the third switch M7, and the source of the second switch M6 is connected to the first sampling capacitor C1. The sampling capacitor C1 is connected to the fourth switch M8, the source of the fourth switch M8 is connected to the source of the third switch M7 and the gate of the second source follower SF2 (M9), and the second source follower SF2 ( The source of M9) is connected to the drain of the row selector M10; the gate of the precharge tube M4 is the input terminal PC of the pixel unit, the first switch tube M5, the second switch tube M6, the third switch tube M7 and the fourth switch tube The gate of M8 is connected to the pixel unit input terminals S1, S2, S3, and S4 respectively, the other end of the first sampling capacitor C1 is grounded, and the other end of the second sampling capacitor C2 is grounded; the second source follower SF2 (M9) The drain is connected to VDD, the gate of the row selector M10 is the input terminal RS of the pixel unit, and the source of the row selector M10 is the output terminal of the entire pixel unit. Through the first, second, third and fourth switch tubes, the reset switch and the transfer tube are stored on the first and second sampling capacitors respectively according to a certain timing sequence, and finally the signal voltage obtained during the exposure time is stored in the pixel. The unit is read out for a period of time, thereby realizing global shutter exposure of the entire pixel unit array.

Please refer to FIGS. 3-13. In this embodiment, the above-mentioned 3D10T global pixel unit preparation method includes the preparation process of the photosensitive area, the preparation process of the 10T signal storage and readout circuit area, and the connection process; wherein,

The preparation process of the photosensitive area includes:

Step 101: Referring to FIG. 4, deposit a first dielectric layer 01 on the front side of the first silicon substrate layer 06; then, prepare a first direct connection structure 02 and a first through hole 03 in the first dielectric layer 01;

Specifically, with the front side of the first silicon substrate layer 06 facing up, a thermal oxidation process is used to prepare the first dielectric layer 01; a Damascus process is used to prepare the first direct connection structure 02 and the first through hole 03; in the first direct connection Metal is deposited in the structure 02 and the first through hole 03;

Step 102 : referring to FIG. 5 , thin the back surface of the first silicon substrate layer 06 ;

Specifically, the backside of the first silicon substrate layer 06 is turned upwards, and it is thinned; the thinning process can adopt a conventional process, which will not be repeated here.

Step 103 : Referring to FIG. 6 , ion implantation is performed into the back surface of the first silicon substrate layer 06 to prepare the photodiode 05 , so that the photodiode 05 is connected to the first through hole 03 , and an isolation trench is prepared around the photodiode 05 trench 04, and fill the isolation trench 04 with a dielectric;

Specifically, with the backside of the first silicon substrate layer 06 facing upward, N-type ion implantation is performed into the first silicon substrate layer 06 to a certain depth, so that the formed photodiode 05 is in phase with the first through hole 03 Connection, here, ions are implanted into the front side of the first silicon substrate 06; photolithography and etching are performed around the photodiode 05 to form an isolation trench 04, and then the isolation trench 04 can be filled by but not limited to a chemical vapor deposition process Dielectric.

Step 104: Referring to FIG. 7, an anti-reflection layer 07 is deposited on the back of the first silicon substrate layer 06 after the step 103 is completed, and then a color filter layer 08 and a microlens 09 are formed on the anti-reflection coating 07 in sequence;

Specifically, the anti-reflection layer 07 may be coated or deposited on the backside of the first silicon substrate layer 06, but not limited thereto, and the preparation of the color filter layer 08 and the microlenses 09 may adopt conventional processes, which will not be repeated here.

The preparation process of the 10T signal storage and readout circuit area includes:

Step 201 : Referring to FIG. 8 , a 10T signal storage and readout circuit 18 is formed on the front surface of the second silicon substrate layer 15 , and a fourth dielectric layer 19 is formed on the surface of the 10T signal storage and readout circuit 18 , and then, a fourth dielectric layer is formed on the surface of the 10T signal storage and readout circuit 18 A contact hole CT is formed in the layer 19, and a metal layer M is formed on the surface of the fourth dielectric layer 19 and the contact hole CT;

Specifically, the front side of the second silicon substrate layer 15 is turned up, and the above-mentioned 10T signal storage and readout circuit 18 is prepared on the front side of the second silicon substrate layer 15, which can be prepared by using a standard CMOS process. For example, step 201 may include:

Step 2011 : forming active and inactive regions 16 in the second silicon substrate layer 15 ; the active regions in the active and inactive regions 16 here are P-type doped active regions.

Step 2012: prepare the above-mentioned 10T signal storage and readout circuit 18;

Step 2013 : forming a fourth dielectric layer 19 on the surfaces of the active and passive regions 16 completed in step 2012; the fourth dielectric layer 19 can be deposited by but not limited to thermal oxidation process;

Step 2014 : forming a contact hole CT in the fourth dielectric layer 19 , and filling the contact hole CT with metal M; here, the formation of the contact hole CT may adopt a conventional process, which will not be repeated here.

Step 2015 : forming a metal layer M on the contact hole CT and the fourth dielectric layer 19 ; the metal layer M can be prepared by a Damascus process here.

Step 202 : referring to FIG. 9 , the backside of the second silicon substrate layer 15 is thinned;

Specifically, the backside of the second silicon substrate layer 15 is turned up to thin it; the thinning process can be a conventional process, which will not be repeated here.

Step 203 : referring to FIG. 10 , the third dielectric layer 14 , the light shielding layer 13 and the second dielectric layer 12 are sequentially formed on the backside of the second silicon substrate layer 15 ;

Specifically, when the backside of the second silicon substrate layer 15 faces upwards, the light shielding layer 13 can be prepared by a Damascus process; the third dielectric layer 14 and the second dielectric layer 12 can be formed by, but not limited to, thermal oxidation process or chemical Vapor deposition process.

Step 204: Referring to FIG. 11, a second through hole 11' is formed in the 10T signal storage and readout circuit 18, the second silicon substrate layer 15, the third dielectric layer 14, the light shielding layer 13 and the second dielectric layer 12;

Specifically, the second through hole 11' is etched by using a through silicon via process (Through Silicon Via).

Step 205: Referring to FIG. 12, a fifth dielectric layer 17 is formed on the sidewall of the second through hole 11', and metal is filled in the second through hole 11', thereby forming the second through hole 11;

Specifically, including:

Step 2051: deposit a fifth dielectric layer 17 on the bottom and sidewalls of the second through hole 11' and on the surface of the second dielectric layer 12;

Step 2052: Using photolithography and etching processes, the fifth dielectric layer 17 on the bottom of the second through hole 11' and the surface of the second dielectric layer 12 is removed by etching, and the fifth dielectric layer 17 on the sidewall of the second through hole 11' is retained. ;

Step 2053: Electroplating the seed layer and filling metal in sequence in the second through hole 11'; thereby forming the second through hole 11;

Step 206 : referring to FIG. 13 , prepare the second direct connection structure 10 in the second dielectric layer 12 , and deposit metal on the second direct connection structure 10 ;

Specifically, the Damascus process can be used to prepare the second direct connection structure 10 .

Then, a connection process is performed, which specifically includes: connecting the first connection structure 02 of the photodiode 05 to the second connection structure 10 of the 10T signal storage and readout circuit 18, and connecting the first dielectric layer 01 of the photosensitive region to the 10T signal The memory is connected to the second dielectric layer 12 of the readout circuit region.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are merely examples for the convenience of description, and are not intended to limit the present invention. Those skilled in the art can make With certain changes and modifications, the protection scope claimed by the present invention should be based on the claims.

Claims (5)

1. A preparation method of a 3D global pixel unit is characterized by comprising a preparation process of a photosensitive unit area, a preparation process of a 10T signal storage and readout circuit area and a connection process; wherein,

the preparation process of the photosensitive unit area comprises the following steps:

step 101: depositing a first dielectric layer on the front surface of the first silicon substrate layer; then, preparing a first direct connection structure and a first through hole in the first dielectric layer;

step 102: thinning the back of the first silicon substrate layer;

step 103: carrying out ion implantation in the back of the first silicon substrate layer to prepare a photosensitive diode so that the photosensitive diode is connected with the first through hole; preparing an isolation trench around the photosensitive diode, and filling a dielectric medium in the isolation trench;

step 104: depositing an anti-reflection coating on the back of the first silicon substrate layer after the step 103 is completed, and then sequentially forming a color filter layer and a micro lens on the anti-reflection coating;

the preparation process of the 10T signal storage and readout circuit area comprises the following steps:

step 201: forming the 10 signal storage and readout circuit on the front surface of a second silicon substrate layer, forming a fourth dielectric layer on the surface of the 10T signal storage and readout circuit, then forming a contact hole in the fourth dielectric layer, and forming a metal layer on the surfaces of the fourth dielectric layer and the contact hole;

step 202: thinning the back of the second silicon substrate layer;

step 203: sequentially forming a third dielectric layer, a light shielding layer and a second dielectric layer on the back of the second silicon substrate layer;

step 204: forming a second via in the 10T signal storage and readout circuitry, the second silicon substrate layer, the third dielectric layer, the light blocking layer, and the second dielectric layer;

step 205: forming a fifth dielectric layer on the side wall of the second through hole, and filling metal in the second through hole;

step 206: preparing a second direct connection structure in the second dielectric layer, and filling metal in the second direct connection structure;

the connection process comprises: connecting a first direct connection structure of the photo sensing diode with a second direct connection structure of the 10T signal storage and readout circuitry area, and connecting a first dielectric layer of the photo sensing area with the second dielectric layer of the 10T signal storage and readout circuitry area; wherein,

the 10T signal storage and readout circuit comprises: the device comprises a reset switch, a first sampling capacitor, a second sampling capacitor, a transmission tube, a first source follower, a pre-charging tube, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a second source follower and a row selector; the drain electrode of the reset switch is connected with a reset voltage, the grid electrode of the reset switch is connected with the input end of the pixel, the source electrode of the reset switch is connected with the source electrode of the transmission tube, the drain electrode of the transmission tube is connected with the cathode of the photosensitive diode, and the grid electrode of the transmission tube is connected with the input end of the pixel unit; the drain electrode of the first source follower is connected with VDD, the source electrode of the first source follower is connected with the drain electrode of the pre-charging tube, the source electrode of the pre-charging tube is grounded, and the grid electrode of the pre-charging tube is connected with the pixel input end; the source electrode of the first source follower and the drain electrode of the pre-charging tube are connected with the drain electrode of the first switching tube and the drain electrode of the second switching tube, the source electrode of the first switching tube is connected with the drain electrode of the first sampling capacitor and the drain electrode of the third switching tube, the source electrode of the second switching tube is connected with the first sampling capacitor and the fourth switching tube, the source electrode of the fourth switching tube is connected with the source electrode of the third switching tube and the grid electrode of the second source follower, and the source electrode of the second source follower is connected with the drain electrode of the row selector; the grid electrode of the pre-charging tube is the input end of the pixel unit, the grid electrodes of the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are respectively connected with the input end of the pixel unit, and the other end of the first sampling capacitor and the other end of the second sampling capacitor are grounded; the drain electrode of the second source follower is connected with VDD, the grid electrode of the row selector is the input end of the pixel unit, and the source electrode of the row selector is used as the output end of the whole pixel unit.

2. The method of claim 1, wherein in step 101, a damascene process is used to fabricate the first direct connection structure and the first via.

3. The method according to claim 1, wherein in step 103, a chemical vapor deposition process is used to fill the dielectric in the isolation trench.

4. A method according to claim 1, wherein in step 104, an anti-reflection layer is coated or deposited on the back of the first silicon substrate layer.

5. The method according to claim 1, wherein the step 205 specifically comprises:

step 2051: depositing the fifth dielectric layer on the bottom and the side wall of the second through hole and the surface of the second dielectric layer;

step 2052: etching and removing the fifth dielectric layer at the bottom of the second through hole and on the surface of the second dielectric layer by adopting photoetching and etching processes, and reserving the fifth dielectric layer on the side wall of the second through hole;

step 2053: and sequentially electroplating a seed layer and filling metal in the second through hole.