CN106056052B - A kind of fingerprint collecting circuit - Google Patents

Abstract

The embodiment of the present invention discloses a fingerprint collection circuit, including: a coupling electrode, a sensing electrode array composed of N*M sensing electrodes, an N*M pixel PIXEL circuit correspondingly connected to the N*M sensing electrodes, and an N*M sensing electrode circuit. * The M-column PIXEL circuits in the M pixel PIXEL circuits are connected to M-channel bias and programmable gain amplifier PGA circuits, and the ADC is connected to the output terminals of the M-channel bias and PGA circuits. The embodiment of the present invention is beneficial to offset circuit mismatch and low-frequency flicker noise, and has smaller output noise.

Description

A fingerprint acquisition circuit

technical field

The invention relates to the technical field of fingerprint collection, in particular to a fingerprint collection circuit.

Background technique

The semiconductor fingerprint acquisition sensor is composed of an acquisition front-end circuit and a signal processing circuit.

At present, the semiconductor fingerprint collection circuit mostly reflects the fingerprint pattern by measuring the capacitance between the finger and the collection electrode. Since the capacitance is very small (less than 0.5fF), the signal is easily obliterated by circuit noise.

Contents of the invention

The embodiment of the present invention provides a fingerprint collection circuit, in order to propose a fingerprint collection circuit with low power consumption and low noise.

In the first aspect, the embodiment of the present invention discloses a fingerprint collection circuit, including:

Coupling electrode, the coupling electrode is used to couple the pulse signal Vdr to the user's finger, wherein the coupling electrode can be, for example, a metal drive ring, which is connected to a pulse generator or a pulse signal of a control chip with a pulse signal output function. Signal output port;

An sensing electrode array composed of N*M sensing electrodes, N is the number of rows of the sensing electrode array, M is the number of columns of the sensing electrode array, and N and M are positive integers;

An N*M pixel PIXEL circuit correspondingly connected to the N*M sensing electrodes, the PIXEL circuit includes an AND gate logic circuit, a switch S, an origin PH switch, a zero-number MOS transistor PM0, and a parasitic capacitance Cp. The first input terminal and the second input terminal of the gate logic circuit are used to respectively access the row selection enable signal and the column selection enable signal of the sensing electrode array, and the signal output terminal of the AND gate logic circuit is connected to the switch The control signal input end of S, the first end of the switch S is used to connect the output end of the current source IS, the second end of the switch S is connected to the source of the PM0, and the gate of the PM0 is connected to the corresponding The first end of the sensing electrode, the first end of the PH switch, and the first end of the Cp, the second end of the PH switch is connected to the positive pole of the reference voltage source, the second end of the Cp, the PM0 The drain of the reference voltage source and the negative electrode of the reference voltage source are grounded;

M-way bias and programmable gain amplifier PGA circuits connected to the M column PIXEL circuits in the N*M pixel PIXEL circuits, and the input terminals of the bias and PGA circuits are connected to N in a corresponding column of PIXEL circuits The first end of the switch S, the bias and PGA circuit includes a current source IS, a K-level switched capacitor amplifying circuit, K is a positive integer, wherein the output terminal of the current source IS and the K-level switched capacitor amplifying circuit The input end of the one-stage switched capacitor amplifying circuit constitutes the input end of the bias and the PGA circuit, and the one-stage switched capacitor amplifying circuit includes a first-stage capacitor, a second capacitor, a switch PHD1 and an amplifying circuit, the first end of the first-stage capacitor is the input end of the first-stage switched capacitor amplifying circuit, and the second end of the first-stage capacitor is connected to the second capacitor of the first stage and the first-stage switch PHD1 And the first end of the amplifying circuit, the first-level second capacitor, the first-level switch PHD1 and the second end of the amplifying circuit are used to connect the second-level switched capacitor amplifying circuit or the analog-to-digital converter ADC;

The ADC connected to the output terminals of the M biases and the PGA circuit through a multiplexing circuit.

Correspondingly, the working principle of the fingerprint collection circuit provided by the embodiment of the present invention is as follows:

PM0 and the current source IS form a source follower circuit, and the output terminal of the source follower circuit is connected to a K-level switched capacitor amplifier circuit;

When the user's finger touches the sensing electrode array, the pulse signal is coupled to the corresponding PIXEL circuit through the capacitance Cf between the finger and the sensing electrode;

When the PH switch is turned on, the sensing electrode and the corresponding parasitic capacitance Cp are set as the reference voltage VREF of the reference voltage source;

When the PH switch is turned off, the sensing electrode maintains the reference voltage VREF, and then the pulse signal Vdr steps, and the voltage of the sensing electrode changes accordingly, and the variation is: ΔV=Vdr*Cf/(Cp+Cf);

If the AC gain of the source follower circuit is 1, its output variation is ΔV, and the variation ΔV has nothing to do with the threshold voltage Vth of PM0, and has nothing to do with the low-frequency noise of PM0;

Then, the first capacitor connected in series in the M-way bias and programmable gain amplifier PGA circuit is short-circuited, the operational amplifier mismatch and low-frequency noise are stored in the first capacitor, and the output of the operational amplifier is equal to the reference voltage VREF (regardless of switch injection effect), when the voltage of the current source IS changes, the switched capacitor amplifying circuit only responds to the change, and the output is:

Vout

=VREF+ΔV*(Ci1 capacitance value/Cf1 capacitance value)*(Ci2 capacitance value/Cf2 capacitance value)

=VREF+Vdr*(Cf capacitance value*(the capacitance value product of K first capacitors))/((Cp capacitance value+Cf capacitance value)*(the capacitance value product of K second capacitors));

According to the above formula, it can be seen that the circuit mismatch and low-frequency flicker noise are offset, so the fingerprint acquisition circuit has a smaller output noise.

With reference to the first aspect, in some possible implementation manners, the K-level switched capacitor amplifier circuit includes the first-stage switched capacitor amplifier circuit and the second-stage switched capacitor amplifier circuit;

The one-stage switched capacitor amplifying circuit includes a first-stage capacitor Ci1, one-stage second capacitor Cf1, one-stage switch PHD1, and one-stage operational amplifier, and the two-stage switched capacitor amplifying circuit includes a two-stage first capacitor Ci2, A secondary second capacitor Cf2, and a secondary operational amplifier;

The first terminal of the Ci1 is connected to the output terminal of the current source IS, the second terminal of the Ci2 is connected to the negative input terminal of the first-stage operational amplifier, the first terminal of the Cf1 and the first terminal of the switch PHD1 One end, the second end of the Cf1, the second end of the switch PHD1 and the output end of the operational amplifier are connected to the first end of the Ci2, and the second end of the Ci2 is connected to the first end of the Cf2. end, the first end of the switch PHD2, and the negative input end of the second-stage operational amplifier, the second end of the Cf2, the second end of the PHD2, and the output end of the second-stage operational amplifier are connected to the ADC, the positive input terminals of the first-stage operational amplifier and the second-stage operational amplifier are connected to the positive pole of the reference voltage source.

Correspondingly, the working principle of the fingerprint collection circuit provided by the embodiment of the present invention is as follows:

PM0 and the current source IS form a source follower circuit, and the output terminal of the source follower circuit is connected to a K-level switched capacitor amplifier circuit;

When the user's finger touches the sensing electrode array, the pulse signal is coupled to the corresponding PIXEL circuit through the capacitance Cf between the finger and the sensing electrode;

When the PH switch is turned on, the sensing electrode and the corresponding parasitic capacitance Cp are set as the reference voltage VREF of the reference voltage source;

When the PH switch is turned off, the sensing electrode maintains the reference voltage VREF, and then the pulse signal Vdr takes a step, and the voltage of the sensing electrode changes accordingly, and the variation is: ΔV=Vdr*Cf capacitance value/(Cp capacitance value+Cf capacitance value) ;

If the AC gain of the source follower circuit is 1, its output variation is ΔV, and the variation ΔV has nothing to do with the threshold voltage Vth of PM0, and has nothing to do with the low-frequency noise of PM0;

Next, the switch PHD2 is turned on before the switch PHD1, and the switch PHD1 is turned on before the switch PH. When the switch PHD1 and the switch PHD2 are turned on, the op amp mismatch and low frequency noise are stored on Ci1 and Ci2, and the op amp output is equal to the reference voltage VREF (without considering the switch injection effect), when the voltage of the current source IS changes, the switched capacitor amplifying circuit only responds to the change, and the output is (assuming K is 2):

Vout

=VREF+ΔV*(Ci1 capacitance value/Cf1 capacitance value)*(Ci2 capacitance value/Cf2 capacitance value)

=VREF+Vdr*(Cf capacitance value*Ci1 capacitance value*Ci2 capacitance value)/((Cp capacitance value+Cf capacitance value)*Cf1 capacitance value*Cf2 capacitance value);

According to the above formula, it can be seen that the circuit mismatch and low-frequency flicker noise are offset, so the fingerprint acquisition circuit has a smaller output noise.

With reference to the first aspect, in some possible implementation manners, the current source IS includes a first MOS transistor PM1 and a second MOS transistor PM2, and the source of the PM1 is connected to a high level, and the drain of the PM1 is connected to The source of the PM2 and the drain of the PM2 are connected to the source of the PM0, and the gate of the PM1 and the gate of the PM2 are used to receive a driving voltage signal.

With reference to the first aspect, in some possible implementation manners, the K-level switched capacitor amplifier circuit includes the first-stage switched capacitor amplifier circuit and the second-stage switched capacitor amplifier circuit;

The first-stage switched capacitor amplifying circuit includes a first-stage capacitor Ci1, a second-stage capacitor Cf1, a primary switch PHD1, a third MOS transistor PM3, a fourth MOS transistor PM4, and a zero-number NPN type MOS transistor NM0. The secondary switched capacitor amplifying circuit includes a secondary first capacitor Ci2, a secondary second capacitor Cf2, and a secondary operational amplifier;

The first end of the Ci1 is connected to the output end of the current source IS, the second end of the Ci2 is connected to the negative input end of the first-stage operational amplifier, the first end of the Cf1, and the first end of the switch PHD1. one terminal and the gate of the NM0;

The gates of the PM3 and the PM4 are used to access the driving voltage signal; the source of the PM3 is connected to a high level, the drain of the PM3 is connected to the source of the PM4, and the drain of the PM4, The second end of the Cf1, the second end of the PHD1, and the drain of the NM0 are connected to the first end of the Ci2; the source of the NM0 is grounded;

The second end of the Ci2 is connected to the first end of the Cf2, the first end of the switch PHD2, and the negative input end of the second-stage operational amplifier, and the positive input end of the second-stage operational amplifier is connected to the reference The positive input terminal of the current source, the second terminal of the Cf2, the second terminal of the switch PHD2 and the output terminal of the second-stage operational amplifier are connected to the ADC.

In combination with the first aspect, in some possible implementations, the aspect ratio of the PM0 is much greater than the aspect ratio of the PM1; (to suppress thermal noise of the current source circuit)

The secondary operational amplifier is a single-ended amplifier;

The width-to-length ratio of the NMO is larger than the width-to-length ratio of the PM3. (to suppress the noise of the bias circuit)

With reference to the first aspect, in some possible implementation manners, the level of the pulse signal Vdr is greater than or equal to 3.3V and less than or equal to 20V.

With reference to the first aspect, in some possible implementation manners, the surface area of the sensing electrode is greater than or equal to 1600um ² .

With reference to the first aspect, in some possible implementation manners, the center-to-center distance between adjacent sensing electrodes in the sensing electrode array is 50 um.

With reference to the first aspect, in some possible implementation manners, the sensing electrode array has a resolution of 508 DPI.

With reference to the first aspect, in some possible implementation manners, the value of M is 8.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Figure 1.1 is a schematic structural diagram of a fingerprint collection circuit disclosed by an embodiment of the present invention;

Figure 1.2 is a schematic structural diagram of a PIXEL circuit in a fingerprint collection circuit disclosed by an embodiment of the present invention;

Figure 1.3 The embodiment of the present invention discloses a structural schematic diagram of the bias and PGA circuit in the fingerprint collection circuit;

Figure 1.4 The embodiment of the present invention discloses a structural schematic diagram of a single PIXEL circuit, a single bias and a PGA circuit in a fingerprint collection circuit;

Fig. 1.5 The embodiment of the present invention discloses a timing diagram between switch PHD1, switch PHD2, switch PH and signal Vdr of a fingerprint collection circuit;

FIG. 2 is a schematic diagram of an optional circuit structure of a K-class switched capacitor amplifier circuit of the fingerprint collection circuit shown in FIG. 1 disclosed in an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to Figure 1.1, Figure 1.2, Figure 1.3 and Figure 1.4, the embodiment of the present invention discloses a fingerprint acquisition circuit, as shown in Figure 1.1 to Figure 1.4, the fingerprint acquisition circuit includes:

Coupling electrode, the coupling electrode is used to couple the pulse signal Vdr to the user's finger, wherein the coupling electrode can be, for example, a metal drive ring, which is connected to a pulse generator or a pulse signal of a control chip with a pulse signal output function. Signal output port;

An sensing electrode array composed of N*M sensing electrodes, N is the number of rows of the sensing electrode array, M is the number of columns of the sensing electrode array, and N and M are positive integers;

An N*M pixel PIXEL circuit correspondingly connected to the N*M sensing electrodes, the PIXEL circuit includes an AND gate logic circuit, a switch S, an origin PH switch, a zero-number MOS transistor PM0, and a parasitic capacitance Cp. The first input terminal and the second input terminal of the gate logic circuit are used to respectively access the row selection enable signal and the column selection enable signal of the sensing electrode array, and the signal output terminal of the AND gate logic circuit is connected to the switch The control signal input end of S, the first end of the switch S is used to connect the output end of the current source IS, the second end of the switch S is connected to the source of the PM0, and the gate of the PM0 is connected to the corresponding The first end of the sensing electrode, the first end of the PH switch, and the first end of the Cp, the second end of the PH switch is connected to the positive pole of the reference voltage source, the second end of the Cp, the PM0 The drain of the reference voltage source and the negative electrode of the reference voltage source are grounded;

M-way bias and programmable gain amplifier PGA circuits connected to the M column PIXEL circuits in the N*M pixel PIXEL circuits, and the input terminals of the bias and PGA circuits are connected to N in a corresponding column of PIXEL circuits The first end of the switch S, the bias and PGA circuit includes a current source IS, a K-level switched capacitor amplifying circuit, K is a positive integer, wherein the output terminal of the current source IS and the K-level switched capacitor amplifying circuit The input end of the one-stage switched capacitor amplifying circuit constitutes the input end of the bias and the PGA circuit, and the one-stage switched capacitor amplifying circuit includes a first-stage capacitor, a second capacitor, a switch PHD1 and an amplifying circuit, the first end of the first-stage capacitor is the input end of the first-stage switched capacitor amplifying circuit, and the second end of the first-stage capacitor is connected to the second capacitor of the first stage and the first-stage switch PHD1 And the first end of the amplifying circuit, the first-level second capacitor, the first-level switch PHD1 and the second end of the amplifying circuit are used to connect the second-level switched capacitor amplifying circuit or the analog-to-digital converter ADC;

The ADC connected to the output terminals of the M biases and the PGA circuit through a multiplexing circuit.

Correspondingly, the working principle of the fingerprint collection circuit provided by the embodiment of the present invention is as follows:

PM0 and the current source IS form a source follower circuit, and the output terminal of the source follower circuit is connected to a K-level switched capacitor amplifier circuit;

When the user's finger touches the sensing electrode array, the pulse signal forms a finger capacitance Cf through the finger and the sensing electrode and is coupled to the corresponding pixel PIXEL circuit;

When the PH switch is turned on, the sensing electrode and the corresponding parasitic capacitance Cp are set as the reference voltage VREF of the reference voltage source;

When the PH switch is turned off, the sensing electrode maintains the reference voltage VREF, and then the pulse signal Vdr takes a step, and the voltage of the sensing electrode changes accordingly, and the amount of change is:

ΔV=Vdr*Cf capacitance value/(Cp capacitance value+Cf capacitance value);

The AC gain of the source follower circuit is preset to 1, then its output variation is ΔV, and the variation ΔV has nothing to do with the threshold voltage Vth of PM0, and has nothing to do with the low-frequency noise of PM0;

Next, when the switch PHD1 and the switch PHD2 are turned on, the operational amplifier mismatch and low-frequency noise are stored in the K first capacitors corresponding to the K-level switched capacitor amplifier circuit, and the output of the operational amplifier is equal to the reference voltage VREF (regardless of the switch injection effect ), when the voltage of the current source IS changes, the switched capacitor amplifying circuit only responds to the change, and the output is:

Vout

=VREF+ΔV*(Ci1 capacitance value/Cf1 capacitance value)*(Ci2 capacitance value/Cf2 capacitance value)

=VREF+Vdr*(Cf capacitance value*(the capacitance value product of K first capacitors))/((Cp capacitance value+Cf capacitance value)*(the capacitance value product of K second capacitors));

According to the above formula, it can be seen that the circuit mismatch and low-frequency flicker noise are offset, so the fingerprint acquisition circuit has a smaller output noise.

Further, please refer to FIG. 2. FIG. 2 is a schematic diagram of an optional circuit structure of a K-level switched capacitor amplifier circuit of the fingerprint collection circuit shown in FIG. 1 disclosed in an embodiment of the present invention. As shown in the figure, the fingerprint collection circuit middle:

The K-level switched capacitor amplifier circuit includes the first-stage switched capacitor amplifier circuit and the second-stage switched capacitor amplifier circuit;

The one-stage switched capacitor amplifying circuit includes a first-stage capacitor Ci1, one-stage second capacitor Cf1, one-stage switch PHD1, and one-stage operational amplifier, and the two-stage switched capacitor amplifying circuit includes a two-stage first capacitor Ci2, A secondary second capacitor Cf2, and a secondary operational amplifier;

The first terminal of the Ci1 is connected to the output terminal of the current source IS, the second terminal of the Ci2 is connected to the negative input terminal of the first-stage operational amplifier, the first terminal of the Cf1 and the first terminal of the switch PHD1 One end, the second end of the Cf1, the second end of the switch PHD1 and the output end of the operational amplifier are connected to the first end of the Ci2, and the second end of the Ci2 is connected to the first end of the Cf2. end, the first end of the switch PHD2, and the negative input end of the second-stage operational amplifier, the second end of the Cf2, the second end of the PHD2, and the output end of the second-stage operational amplifier are connected to the ADC, the positive input terminals of the first-stage operational amplifier and the second-stage operational amplifier are connected to the positive pole of the reference voltage source.

Correspondingly, the working principle of the fingerprint collection circuit provided by the embodiment of the present invention is as follows:

PM0 and the current source IS form a source follower circuit, and the output terminal of the source follower circuit is connected to a K-level switched capacitor amplifier circuit;

When the user's finger touches the sensing electrode array, the pulse signal is coupled to the corresponding PIXEL circuit through the capacitance Cf between the finger and the sensing electrode;

When the PH switch is turned on, the sensing electrode and the corresponding parasitic capacitance Cp are set as the reference voltage VREF of the reference voltage source;

When the PH switch is turned off, the sensing electrode maintains the reference voltage VREF, and then the pulse signal Vdr steps, and the voltage of the sensing electrode changes accordingly, and the variation is: ΔV=Vdr*Cf/(Cp+Cf);

The AC gain of the source follower circuit is 1, so its output variation is ΔV, which has nothing to do with the threshold voltage Vth of PM0, and has nothing to do with the low-frequency noise of PM0;

Next, the switch PHD2 is turned on before the switch PHD1, and the switch PHD1 is turned on before the switch PH. The timing sequence of the switch PHD1, the switch PHD2, and the switches PH and Vdr is shown in Figure 1.5. When the switch PHD1 and the switch PHD2 are turned on, the operational amplifier mismatch and Low-frequency noise is stored on Ci1 and Ci2, and the output of the operational amplifier is equal to the reference voltage VREF (regardless of the switch injection effect). When the voltage of the current source IS changes, the switched capacitor amplifier circuit only responds to the change, and the output is:

Vout

=VREF+ΔV*(Ci1 capacitance value/Cf1 capacitance value)*(Ci2 capacitance value/Cf2 capacitance value)

=VREF+Vdr*(Cf capacitance value*Ci1 capacitance value*Ci2 capacitance value)/((Cp capacitance value+Cf capacitance value)*Cf1 capacitance value*Cf2 capacitance value);

According to the above formula, it can be seen that the circuit mismatch and low-frequency flicker noise are offset, so the fingerprint acquisition circuit has a smaller output noise.

Optionally, please refer to FIG. 2. FIG. 2 is a schematic diagram of an optional circuit structure of the current source IS in the fingerprint acquisition circuit shown in FIG. 1 disclosed in the third embodiment of the present invention, as shown in the figure:

The current source IS includes a No. 1 MOS transistor PM1 and a No. 2 MOS transistor PM2, and the source of the PM1 is connected to a high level, the drain of the PM1 is connected to the source of the PM2, and the drain of the PM2 is connected to a high level. The source of the PM0 is connected, and the gate of the PM1 and the gate of the PM2 are used to access a driving voltage signal.

Optionally, in the embodiment of the present invention, the K-level switched capacitor amplifying circuit includes the first-level switched capacitor amplifying circuit and the second-level switched capacitor amplifying circuit;

The first-stage switched capacitor amplifying circuit includes a first-stage capacitor Ci1, a second-stage capacitor Cf1, a primary switch PHD1, a third MOS transistor PM3, a fourth MOS transistor PM4, and a zero-number NPN type MOS transistor NM0. The secondary switched capacitor amplifying circuit includes a secondary first capacitor Ci2, a secondary second capacitor Cf2, and a secondary operational amplifier;

The first end of the Ci1 is connected to the output end of the current source IS, the second end of the Ci2 is connected to the negative input end of the first-stage operational amplifier, the first end of the Cf1, and the first end of the switch PHD1. one terminal and the gate of the NM0;

The gates of the PM3 and the PM4 are used to access the driving voltage signal; the source of the PM3 is connected to a high level, the drain of the PM3 is connected to the source of the PM4, and the drain of the PM4, The second end of the Cf1, the second end of the PHD1, and the drain of the NM0 are connected to the first end of the Ci2; the source of the NM0 is grounded;

The second end of the Ci2 is connected to the first end of the Cf2, the first end of the switch PHD2, and the negative input end of the second-stage operational amplifier, and the positive input end of the second-stage operational amplifier is connected to the reference The positive input terminal of the current source, the second terminal of the Cf2, the second terminal of the switch PHD2 and the output terminal of the second-stage operational amplifier are connected to the ADC.

Optionally, in this embodiment of the present invention, the width-to-length ratio of the PM0 is much larger than the width-to-length ratio of the PM1, so as to suppress thermal noise of the current source circuit.

The secondary operational amplifier is a single-ended amplifier;

The width-to-length ratio of the NM0 is greater than the width-to-length ratio of the PM3, so as to suppress the noise of the bias circuit.

Optionally, the level of the pulse signal Vdr is greater than or equal to 3.3V and less than or equal to 20V.

Optionally, the surface area of the sensing electrode is greater than or equal to 1600um ² .

Optionally, the center-to-center distance between adjacent sensing electrodes in the sensing electrode array is 50 um.

Optionally, the sensing electrode array has a resolution of 508DPI.

Above, the fingerprint acquisition circuit provided by the embodiment of the present invention has been introduced in detail. In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its implementation. core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as limiting the present invention .

Claims (10)

1. a kind of fingerprint collecting circuit characterized by comprising

Coupling electrode, the coupling electrode are used to pulse signal Vdr being coupled to user's finger；

The induction electrode array as composed by N*M induction electrode, N are the line number of the induction electrode array, and M is the induction The columns of electrod-array, N, M are positive integer；

The road the N*M pixel PIXEL circuit being correspondingly connected with the N*M induction electrode, the PIXEL circuit include and gate logic Circuit, switch S, point of origin P H switch, No. zero metal-oxide-semiconductor PM0, parasitic capacitance Cp, the first input end of the AND gate and The row that second input terminal is used to be respectively connected to the induction electrode array selects enable signal and column selection enable signal, described to patrol with door The signal output end for collecting circuit connects the control signal input of the switch S, and the first end of the switch S is for connecting electric current The output end of source IS, the second end of the switch S connect the source electrode of the PM0, and the grid of the PM0 connects corresponding induced electricity The first end of the first end of pole, the first end of PH switch and the Cp, the second end connection of the PH switch is with reference to electricity The anode of potential source, the cathode ground connection of the second end of the Cp, the drain electrode of the PM0 and the reference voltage source；

The biasing of the road M and programmable gain amplifier with the M column PIXEL circuit connection in the N*M pixel PIXEL circuit PGA circuit, the biasing connect the N in corresponding column PIXEL circuit with the input terminal of programmable gain amplifier PGA circuit The first end of a switch S, the biasing and programmable gain amplifier PGA circuit include IS, K grades of switching capacity amplifications of current source Circuit, K are positive integer, wherein the level-one switch in the output end of the current source IS and the K grades of switched capacitor amplifier circuit The input terminal of capacitor amplifier circuit forms the input terminal of the biasing and programmable gain amplifier PGA circuit, and the level-one is opened Closing capacitor amplifier circuit includes level-one first capacitor, the second capacitor of level-one, level-one switch PHD1 and amplifying circuit, the level-one The first end of first capacitor is the input terminal of the level-one switched capacitor amplifier circuit, and the second end of the level-one first capacitor connects Connect the first end of second capacitor of level-one, level-one switch PHD1 and amplifying circuit, second capacitor of level-one, level-one switch The second end of PHD1 and amplifying circuit is for connecting secondary switch capacitor amplifier circuit or analog-digital converter ADC；

When the second end of second capacitor of level-one, level-one switch PHD1 and amplifying circuit is for passing through when connecting the ADC The ADC that multiplex electronics are biased with the road M and the output end of programmable gain amplifier PGA circuit is connect.

2. circuit according to claim 1, which is characterized in that the K grades of switched capacitor amplifier circuit includes the level-one Switched capacitor amplifier circuit and secondary switch capacitor amplifier circuit；

The level-one switched capacitor amplifier circuit includes level-one first capacitor Ci1, level-one the second capacitor Cf1, level-one switch PHD1, And level-one operational amplifier, the secondary switch capacitor amplifier circuit include second level first capacitor Ci2, the second capacitor of second level Cf2 and two-level operating amplifier；

The first end of the Ci1 connects the output end of the current source IS, and the second end of the Ci1 connects the level-one operation and puts The first end of the big negative input end of device, the first end of the Cf1 and the switch PHD1, the second end of the Cf1, the switch The second end of PHD1 connects the first end of the Ci2 with the output end of the level-one operational amplifier, and the second end of the Ci2 connects The first end, the first end of the switch PHD2 and the negative input end of the two-level operating amplifier of the Cf2 are connect, it is described The output end of the second end of Cf2, the second end of the PHD2 and the two-level operating amplifier connects the ADC, and described one Grade operational amplifier connects the anode of the reference voltage source with the positive input terminal of the two-level operating amplifier.

3. circuit according to claim 1, which is characterized in that the current source IS includes No.1 metal-oxide-semiconductor PM1 and No. two Metal-oxide-semiconductor PM2, and the source electrode of the PM1 connects high level, the drain electrode of the PM1 connects the source electrode of the PM2, the leakage of the PM2 Pole connects the source electrode of the PM0, and the grid of the grid of the PM1 and the PM2 are for accessing drive voltage signal.

4. circuit according to claim 3, which is characterized in that the K grades of switched capacitor amplifier circuit includes the level-one Switched capacitor amplifier circuit and secondary switch capacitor amplifier circuit；

The level-one switched capacitor amplifier circuit includes level-one first capacitor Ci1, level-one the second capacitor Cf1, level-one switch PHD1, No. three metal-oxide-semiconductor PM3, No. four metal-oxide-semiconductor PM4 and No. zero NPN type metal-oxide-semiconductor NM0, the secondary switch capacitor amplifier circuit include two Grade first capacitor Ci2, second level the second capacitor Cf2 and two-level operating amplifier；

The first end of the Ci1 connects the output end of the current source IS, and the second end of the Ci1 connects the first of the Cf1 It holds, the grid of the first end of the switch PHD1 and the NM0；

The grid of the PM3 and the PM4 are for accessing drive voltage signal；The source electrode of the PM3 connects high level, described The drain electrode of PM3 connects the source electrode of the PM4, the drain electrode of the PM4, the second end of the Cf1, the second end of the PHD1 and The drain electrode of the NM0 connects the first end of the Ci2；The source electrode of the NM0 is grounded；

The second end of the Ci2 connects the first end of the Cf2, the first end of the switch PHD2 and the second level operation and puts The negative input end of big device, the positive input terminal of the two-level operating amplifier connects the positive input terminal of the reference voltage source, described The output end of the second end of Cf2, the second end of the switch PHD2 and the two-level operating amplifier connects the ADC.

5. circuit according to claim 4, which is characterized in that the breadth length ratio of the PM0 is long much larger than the width of the PM1 Than；

The two-level operating amplifier is single-ended amplifier；

The breadth length ratio of the NM0 is greater than the breadth length ratio of the PM3.

6. circuit according to claim 1-5, which is characterized in that the pulse signal Vdr level is more than or equal to 3.3V, and it is less than or equal to 20V.

7. circuit according to claim 1-5, which is characterized in that the surface area of the induction electrode is greater than or waits In 1600um²。

8. circuit according to claim 1-5, which is characterized in that the adjacent induction in the induction electrode array Center spacing between electrode is 50um.

9. circuit according to claim 1-5, which is characterized in that the resolution ratio of the induction electrode array is 508DPI。

10. circuit according to claim 1-5, which is characterized in that the value of the M is 8.