CN106054472A - Low-temperature polysilicon thin film transistor array substrate, manufacture method of substrate and liquid crystal panel comprising substrate - Google Patents
Low-temperature polysilicon thin film transistor array substrate, manufacture method of substrate and liquid crystal panel comprising substrate Download PDFInfo
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- CN106054472A CN106054472A CN201610701193.2A CN201610701193A CN106054472A CN 106054472 A CN106054472 A CN 106054472A CN 201610701193 A CN201610701193 A CN 201610701193A CN 106054472 A CN106054472 A CN 106054472A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims description 27
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 14
- 239000010409 thin film Substances 0.000 title claims description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 239000002184 metal Substances 0.000 claims abstract description 109
- 238000002161 passivation Methods 0.000 claims abstract description 33
- 239000010408 film Substances 0.000 claims description 51
- 239000010936 titanium Substances 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000012528 membrane Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000002131 composite material Substances 0.000 abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910003087 TiOx Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 241001062009 Indigofera Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a low-temperature polysilicon film transistor array substrate, comprising a substrate, a display portion on the substrate and a non-display portion extended along an edge of the display portion, and the non-display portion includes: a composite metal layer on the substrate; a flat layer on the composite metal layer; a first through hole exposing partially the composite metal layer in the flat layer; a common electrode layer on the flat layer; a passivation layer covering the common electrode layer and exposing the composite metal layer; a second through hole and a third through hole in the passivation layer, wherein the second through hole exposes partially the composite metal layer and the third through hole exposes partially the common electrode layer; an electric connection layer on the passivation layer, wherein the electric connection layer fills respectively the second through hole and the third through hole to contact the composite metal layer and the common electrode layer respectively. Since metal oxides formed on the composite metal layer contacted with the passivation layer can be removed during manufacture of the passivation layer, contact condition of the composite metal layer with the common electrode layer is improved and product quality is thus improved.
Description
Technical field
The invention belongs to technical field of liquid crystal display, specifically, relate to a kind of low-temperature polysilicon film transistor array
Substrate and preparation method thereof, liquid crystal panel.
Background technology
Along with the evolution of photoelectricity Yu semiconductor technology, also drive the fluffy of flat faced display (Flat Panel Display)
The exhibition of breaking out, and in many flat faced displays, liquid crystal display (Liquid Crystal Display is called for short LCD) is because having
Many advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, it has also become the master in market
Stream.
At present, widely used as the switch element of LCD is amorphous silicon membrane audion (a-Si TFT), but a-Si
TFT LCD requires still to be restricted meeting slim, light weight, high-fineness, high brightness, high reliability, low-power consumption etc..Low temperature is many
Compared with crystal silicon (Lower Temperature Polycrystal Silicon, LTPS) TFT LCD and a-Si TFT LCD,
Meet above-mentioned requirements aspect, there is clear superiority.
But, in the manufacturing process of existing LTPS array base palte, public voltage signal is by LTPS array base palte
Viewing area (i.e. AA district) periphery flatness layer (PLN) in via be sent to public electrode, and below the flatness layer of periphery
Holding wire formed by composite metal structures (such as Ti/Al/Ti structure), but Ti (titanium) metal at processing environment and
Rear processing procedure (such as baking) environment easily aoxidizes, thus forms TiOx, and TiOxResistance value is higher and is difficult to remove, and easily causes
Public voltage signal input is abnormal, thus causes product display characteristic the best.
Summary of the invention
In order to solve above-mentioned technical problem, it is an object of the invention to provide a kind of low-temperature polysilicon film transistor battle array
Row substrate, including: substrate, arrange display part on the substrate and by the edge of described display part extend non-display
Portion, described display part includes multiple low-temperature polysilicon film transistors of array arrangement, and described non-display portion includes: on substrate
Complex metal layer；Flatness layer on described complex metal layer；The first through hole in described flatness layer, described first through hole
Part complex metal layer is exposed；Common electrode layer on described flatness layer；Cover described common electrode layer and exposure
The passivation layer of complex metal layer；The second through hole in described passivation layer and third through-hole, described second through hole is compound by part
Metal level exposes, and part common electrode layer is exposed by described third through-hole；Electric connection layer on described passivation layer, described in be electrically connected
Connect layer and fill described second through hole and described third through-hole respectively, with respectively with expose complex metal layer and the common electrical of exposure
Pole layer contact.
Further, described complex metal layer includes: set gradually the first metal layer on the substrate, the second metal
Layer and the 3rd metal level.
Further, described the first metal layer and described 3rd metal level use titanium to make, and described second metal level uses
Aluminum is made.
Further, described display part also includes the pixel being connected with the drain electrode of each low-temperature polysilicon film transistor
Electrode, described pixel electrode concurrently forms with described electric connection layer, and described pixel electrode is independent of one another with described electric connection layer.
Further, described pixel electrode and described electric connection layer all use tin indium oxide to make.
Another object of the present invention also resides in the manufacture method providing a kind of low-temperature polysilicon film transistor array base palte,
Described manufacture method includes: form display part and the non-display portion extended by the edge of described display part on substrate；Described
The concrete manufacture method of display part includes: form multiple low-temperature polysilicon film transistors of array arrangement on substrate, described
The concrete manufacture method of non-display portion includes: form complex metal layer on substrate；Described complex metal layer is formed smooth
Layer；The first through hole is formed in described flatness layer；Part complex metal layer is exposed by described first through hole；On described flatness layer
Form common electrode layer；Form the passivation layer of the complex metal layer covering described common electrode layer and exposure；In described passivation
The second through hole and third through-hole is formed in Ceng；Part complex metal layer is exposed by described second through hole, and described third through-hole is by portion
Common electrode layer is divided to expose；Described passivation layer is formed electric connection layer；Described electric connection layer fills described second through hole respectively
With described third through-hole, to contact with the complex metal layer exposed and the common electrode layer of exposure respectively.
Further, the concrete grammar forming described complex metal layer on substrate includes: utilize titanium on the substrate
Material forms the first metal layer；Described the first metal layer utilize aluminum form the second metal level；At described second metal
Titanium material is utilized to form the 3rd metal level on Ceng.
Further, the concrete manufacture method of described display part also includes: formed and each low-temperature polysilicon film crystal
The pixel electrode that the drain electrode of pipe is connected；Wherein, described pixel electrode concurrently forms with described electric connection layer, and described pixel electricity
Pole is independent of one another with described electric connection layer.
Further, tin indium oxide is utilized to concurrently form described pixel electrode and described electric connection layer.
A further object of the present invention is again to provide a kind of liquid crystal panel, many including color membrane substrates and the low temperature arranging box
Polycrystal silicon film transistor (TFT) array substrate, described low-temperature polysilicon film transistor array base palte is above-mentioned low-temperature polysilicon film
Transistor (TFT) array substrate, or utilize above-mentioned manufacture method to make described low-temperature polysilicon film transistor array base palte.
Beneficial effects of the present invention: owing to directly forming passivation layer on the part complex metal layer that the first through hole exposes,
And in the manufacturing process of passivation layer, can be effectively by the top-level metallic oxygen of the part complex metal layer by the first through hole exposure
Compound (metal-oxide on the surface of the i.e. the 3rd metal level) is removed, thus improves connecing of complex metal layer and common electrode layer
The situation of touching, and then improving product quality.
Accompanying drawing explanation
By combining the following description that accompanying drawing is carried out, above and other aspect, feature and the advantage of embodiments of the invention
Will become clearer from, in accompanying drawing:
Fig. 1 is the top view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention；
Fig. 2 is low-temperature polysilicon film transistor and the structural representation of pixel electrode according to an embodiment of the invention；
Fig. 3 is that the A-A in Fig. 1 is to profile；
Fig. 4 is the flow chart of the manufacture method of non-display portion according to an embodiment of the invention；
Fig. 5 is the structural representation of liquid crystal panel according to an embodiment of the invention.
Detailed description of the invention
Hereinafter, with reference to the accompanying drawings to describe embodiments of the invention in detail.However, it is possible to come real in many different forms
Execute the present invention, and the present invention should not be construed as limited to the specific embodiment that illustrates here.On the contrary, it is provided that these are implemented
Example is to explain the principle of the present invention and actual application thereof, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various amendments of specific intended application.In the accompanying drawings, identical label will be used for table all the time
Show identical element.
Fig. 1 is the top view of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention.Fig. 2 is root
Low-temperature polysilicon film transistor and the structural representation of pixel electrode according to embodiments of the invention.Fig. 3 is the A-A in Fig. 1
To profile.
Referring to figs. 1 through Fig. 3, low-temperature polysilicon film transistor array base palte includes according to an embodiment of the invention: base
Plate 100, arrange display part on the substrate 100 (or claiming viewing area) 200 and by the edge of display part 200 extend non-display
Portion's (or claiming non-display area) 300.
Specifically, substrate 100 can be transparent glass substrate or resin substrate.Display part 200 and non-display portion
300 are arranged on the same surface of substrate 100.During the processing procedure of low-temperature polysilicon film transistor array base palte, display
Portion 200 and non-display portion 300 are concurrently formed on the same surface of substrate 100.Generally, display part 200 includes array arrangement
The picture that multiple low-temperature polysilicon film transistors 210 and the drain electrode 211 with each low-temperature polysilicon film transistor 210 are connected
Element electrode 220.Certainly, it should be noted that display part 200 can also include the data wire that is crisscross arranged and gate line and
The element of other necessity.
Hereinafter non-display portion 300 will be described in detail.With continued reference to Fig. 1 to Fig. 3, non-display portion 300 includes: multiple
Metal layer 310, flatness layer 320, common electrode layer 330, passivation layer 340 and electric connection layer 350.
Specifically, complex metal layer 310 is arranged on the substrate 100.It should be noted that complex metal layer 310 and low temperature
The grid (not shown) of polycrystalline SiTFT 210 concurrently forms.Further, preferred as one, complex metal layer 310
Including: set gradually the first metal layer the 311, second metal level 312 on the substrate 100 and the 3rd metal level 313, but the present invention
Being not restricted to this, such as complex metal layer 310 can include two metal layers, four layers of metal level or more layers metal level.
In this embodiment, it is preferred that, the first metal layer 311 and the 3rd metal level 313 are made up of titanium (Ti), and the second metal level 312
It is made up of aluminum (Al)；But the present invention is not restricted to this, such as this three-layer metal layer can also utilize other conducting metal material
Material is made.So, the grid of complex metal layer 310 and low-temperature polysilicon film transistor 210 is respectively provided with Ti/Al/Ti metal knot
Structure.
Flatness layer 320 is arranged on complex metal layer 310, forms the first through hole 321 in flatness layer 320, this first lead to
Part complex metal layer 310 is exposed by hole 321, i.e. part the 3rd metal level 313 is exposed by this first through hole 321.Need explanation
, display part 200 also has flatness layer (not shown), and this flatness layer concurrently forms with flatness layer 320.
Common electrode layer 330 is arranged on flatness layer 320.It should be noted that display part 200 also has public electrode
Layer (not shown), and this common electrode layer concurrently forms with common electrode layer 330 and is electrically connected to each other.
Passivation layer 340 covers on the complex metal layer 310 of common electrode layer 330 and exposure, is formed in passivation layer 340
Second through hole 341 and third through-hole 342, part complex metal layer 310 is exposed by this second through hole 341, and this third through-hole 342 will
Part common electrode layer 330 exposes.It should be noted that also there is in display part 200 passivation layer (not shown), and this passivation layer
Concurrently form with passivation layer 340.
Electric connection layer 350 is arranged on passivation layer 340, and electric connection layer 350 fills the second through hole 341 and the 3rd respectively
Through hole 342, to contact with the complex metal layer 310 exposed and the common electrode layer 330 of exposure respectively, so that complex metal layer
310 and common electrode layer 330 be electrically connected, so that public voltage signal is transferred to public electrode by complex metal layer 310
Layer 330, and then it is transferred to the common electrode layer in display part 200.It should be noted that this electric connection layer 350 and pixel electrode
220 concurrently form, but the two is independent of one another.Preferably, transparent tin indium oxide is utilized to concurrently form electric connection layer 350 and pixel
Electrode 220, but the present invention is not restricted to this, utilizes and other conductive material can also be utilized to make both.
Owing to directly forming passivation layer 340 on the part complex metal layer 310 exposed by the first through hole 321, and blunt
Change in the manufacturing process of layer 340, can be effectively by golden for the top layer of the part complex metal layer 310 exposed by the first through hole 321
Belong to oxide (metal-oxide on the surface of the i.e. the 3rd metal level 313) to remove, thus improve complex metal layer 310 and public
The contact condition of electrode layer 330, and then improving product quality.
The manufacture method of low-temperature polysilicon film transistor array base palte according to an embodiment of the invention will be entered below
Row explanation.With reference to Fig. 1, first, it is provided that a substrate 100.Then, display part 200 is formed on the substrate 100 and by display part
The non-display portion (or claiming non-display area) 300 that the edge of 200 extends.
The concrete manufacture method of display part 200 is: form multiple low-temperature polysilicon films of array arrangement on the substrate 100
Transistor 210；Form the pixel electrode 220 being connected with the drain electrode 211 of each low-temperature polysilicon film transistor 210.Each
The manufacture method of low-temperature polysilicon film transistor 210 uses the manufacture method of the low-temperature polysilicon film transistor of prior art
, do not repeat them here.
The manufacture method of non-display portion 300 according to an embodiment of the invention will be described in detail below.Fig. 4 is root
The flow chart of manufacture method according to the non-display portion of embodiments of the invention.
Referring to figs. 1 through Fig. 4, in step S410, form complex metal layer 310 on the substrate 100.It should be noted that
Complex metal layer 310 concurrently forms with the grid 212 of low-temperature polysilicon film transistor 210.
Further, the manufacture method of complex metal layer 310 specifically includes: utilize titanium to form the first gold medal on the substrate 100
Belong to layer 311；The first metal layer 311 utilize aluminum form the second metal level 312；And utilize titanium on the second metal level 312
Form the 3rd metal level 313.So, the grid of complex metal layer 310 and low-temperature polysilicon film transistor 210 is respectively provided with Ti/
Al/Ti metal structure.
In the step s 420, complex metal layer 310 forms flatness layer 320.It should be noted that in display part 200
Also there is flatness layer (not shown), and this flatness layer concurrently forms with flatness layer 320.
In step S430, flatness layer 320 forms the first through hole 321；The compound gold of this first through hole 321 just part
Belong to layer 310 to expose, i.e. part the 3rd metal level 313 is exposed by this first through hole 321.
In step S440, flatness layer 320 forms common electrode layer 330.It should be noted that in display part 200
Also there is common electrode layer (not shown), and this common electrode layer concurrently forms with common electrode layer 330 and is electrically connected to each other.
In step S450, form the complex metal layer 310 covering common electrode layer 330 and being exposed by the first through hole 321
Passivation layer 340.It should be noted that display part 200 also has passivation layer (not shown), and this passivation layer and passivation layer
340 concurrently form.
In step S460, passivation layer 340 forms the second through hole 341 and third through-hole 342, this second through hole 341
Being exposed by part complex metal layer 310, part common electrode layer 330 is exposed by this third through-hole 342.
In step S470, forming electric connection layer 350 on passivation layer 340, this electric connection layer 350 is filled second respectively and is led to
Hole 341 and third through-hole 342, with respectively with the complex metal layer 310 exposed by the second through hole 341 and sudden and violent by third through-hole 342
The common electrode layer 330 of dew contacts.As such, it is possible to make complex metal layer 310 and common electrode layer 330 be electrically connected, so that
Public voltage signal is transferred to common electrode layer 330 by complex metal layer 310, so be transferred in display part 200 public
Electrode layer.It should be noted that this electric connection layer 350 concurrently forms with pixel electrode 220, but the two is independent of one another.
Fig. 5 is the structural representation of liquid crystal panel according to an embodiment of the invention.
With reference to Fig. 5, liquid crystal panel includes according to an embodiment of the invention: the low-temperature polysilicon film crystal arranging box
Pipe array base palte 1000 and color membrane substrates 2000, and it is located in low-temperature polysilicon film transistor array base palte 1000 and color film
Liquid crystal layer 3000 between substrate 2000.Liquid crystal layer 3000 has some liquid crystal molecules.Here, low-temperature polysilicon film crystal
Pipe array base palte 1000 is the low-temperature polysilicon film transistor array base palte shown in Fig. 1 and Fig. 3, or, low temperature polycrystalline silicon is thin
Film transistor array base palte 1000 is the low-temperature polysilicon film transistor array base palte using above-mentioned manufacture method to make.This
Outward, color membrane substrates 2000 generally include be made up of red (R) optical filter, green (G) optical filter, indigo plant (B) optical filter colored filter,
Black matrix", alignment film etc..The structure of color membrane substrates refer to the prior art being correlated with in further detail, repeats no more here.
Although illustrate and describing the present invention with reference to specific embodiment, but it should be appreciated by those skilled in the art that:
In the case of without departing from the spirit and scope of the present invention limited by claim and equivalent thereof, can carry out at this form and
Various changes in details.
Claims (10)
1. a low-temperature polysilicon film transistor array base palte, including: substrate, arrange display part on the substrate and
The non-display portion extended by the edge of described display part, described display part includes that multiple low-temperature polysilicon films of array arrangement are brilliant
Body pipe, it is characterised in that described non-display portion includes:
Complex metal layer on substrate；
Flatness layer on described complex metal layer；
The first through hole in described flatness layer, part complex metal layer is exposed by described first through hole；
Common electrode layer on described flatness layer；
Cover the passivation layer of the complex metal layer of described common electrode layer and exposure；
The second through hole in described passivation layer and third through-hole, part complex metal layer is exposed by described second through hole, described
Part common electrode layer is exposed by third through-hole；
Electric connection layer on described passivation layer, described electric connection layer fills described second through hole and described third through-hole respectively,
To contact with the complex metal layer of exposure and the common electrode layer of exposure respectively.
Low-temperature polysilicon film transistor array base palte the most according to claim 1, it is characterised in that described composition metal
Layer includes: set gradually the first metal layer on the substrate, the second metal level and the 3rd metal level.
Low-temperature polysilicon film transistor array base palte the most according to claim 2, it is characterised in that described first metal
Layer and described 3rd metal level use titanium to make, and described second metal level is adopted and is formed from aluminium.
Low-temperature polysilicon film transistor array base palte the most according to claim 1, it is characterised in that described display part is also
Including the pixel electrode being connected with the drain electrode of each low-temperature polysilicon film transistor, described pixel electrode electrically connects with described
Layer concurrently forms, and described pixel electrode is independent of one another with described electric connection layer.
Low-temperature polysilicon film transistor array base palte the most according to claim 4, it is characterised in that described pixel electrode
Tin indium oxide is all used to make with described electric connection layer.
6. a manufacture method for low-temperature polysilicon film transistor array base palte, described manufacture method includes: shape on substrate
Become display part and the non-display portion extended by the edge of described display part；
The concrete manufacture method of described display part includes: form multiple low-temperature polysilicon film crystal of array arrangement on substrate
Pipe, it is characterised in that the concrete manufacture method of described non-display portion includes:
Substrate is formed complex metal layer；
Described complex metal layer is formed flatness layer；
The first through hole is formed in described flatness layer；Part complex metal layer is exposed by described first through hole；
Described flatness layer is formed common electrode layer；
Form the passivation layer of the complex metal layer covering described common electrode layer and exposure；
The second through hole and third through-hole is formed in described passivation layer；Part complex metal layer is exposed by described second through hole, institute
State third through-hole part common electrode layer to be exposed；
Described passivation layer is formed electric connection layer；Described electric connection layer fills described second through hole and described threeway respectively
Hole, to contact with the complex metal layer of exposure and the common electrode layer of exposure respectively.
The manufacture method of low-temperature polysilicon film transistor array base palte the most according to claim 6, it is characterised in that
The concrete grammar forming described complex metal layer on substrate includes:
Titanium material is utilized to form the first metal layer on the substrate；
Described the first metal layer utilize aluminum form the second metal level；
Described second metal level utilize titanium material form the 3rd metal level.
The manufacture method of low-temperature polysilicon film transistor array base palte the most according to claim 6, it is characterised in that institute
The concrete manufacture method stating display part also includes: form the pixel being connected with the drain electrode of each low-temperature polysilicon film transistor
Electrode；Wherein, described pixel electrode concurrently forms with described electric connection layer, and described pixel electrode is with described electric connection layer each other
Independent.
The manufacture method of low-temperature polysilicon film transistor array base palte the most according to claim 8, it is characterised in that profit
Described pixel electrode and described electric connection layer is concurrently formed with tin indium oxide.
10. a liquid crystal panel, including the color membrane substrates arranging box and low-temperature polysilicon film transistor array base palte, it is special
Levying and be, described low-temperature polysilicon film transistor array base palte is that the low temperature polycrystalline silicon described in any one of claim 1 to 5 is thin
Film transistor array base palte, or it is thin to utilize the manufacture method described in any one of claim 6 to 9 to make described low temperature polycrystalline silicon
Film transistor array base palte.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610701193.2A CN106054472B (en) | 2016-08-22 | 2016-08-22 | Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610701193.2A CN106054472B (en) | 2016-08-22 | 2016-08-22 | Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106054472A true CN106054472A (en) | 2016-10-26 |
| CN106054472B CN106054472B (en) | 2019-09-10 |
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| CN201610701193.2A Active CN106054472B (en) | 2016-08-22 | 2016-08-22 | Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel |
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| CN114122019A (en) * | 2021-11-22 | 2022-03-01 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
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