CN106027006B - Electrification reset circuit - Google Patents
Electrification reset circuit Download PDFInfo
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- CN106027006B CN106027006B CN201610330481.1A CN201610330481A CN106027006B CN 106027006 B CN106027006 B CN 106027006B CN 201610330481 A CN201610330481 A CN 201610330481A CN 106027006 B CN106027006 B CN 106027006B
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- 230000007306 turnover Effects 0.000 claims abstract description 28
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- 230000006872 improvement Effects 0.000 description 15
- 230000008859 change Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 101000927793 Homo sapiens Neuroepithelial cell-transforming gene 1 protein Proteins 0.000 description 3
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- 101150110971 CIN7 gene Proteins 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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Abstract
The invention discloses a kind of electrification reset circuits, comprising: the first NMOS tube and the first PMOS tube；The source electrode of first NMOS tube is grounded, and the grid leak pole of the first NMOS tube and the grid of the first PMOS tube link together and be connected to supply voltage by the first current path；The source electrode of first PMOS tube is connected to supply voltage by the second current path；The drain electrode of first PMOS tube is grounded by third current path；The drain electrode output reset signal of first PMOS tube；Conducting electric current of the conducting electric current of third current path less than the second current path；Turnover voltage is the sum of the gate source voltage of the first NMOS tube and the first PMOS tube.The present invention can save area, reduce power consumption, be able to achieve technique and follow.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of electrification reset (Power On Reset,
POR) circuit.
Background technique
As shown in Figure 1, being the schematic diagram of existing por circuit, resistance R101 and R102 is divided and is being saved to supply voltage VDD
Point NET100 forms turnover voltage (Vtrip), and turnover voltage is input to the grid of NMOS tube M101, and the drain electrode of NMOS tube M101 is
Node NET101 meets supply voltage VDD by resistance R103, and the drain electrode of NMOS tube M101 also exports power-on reset signal to reverse phase
The input terminal of device INV100, the reset signal RSTB of the output end output reverse phase of phase inverter INV100.
As shown in Fig. 2, be the power-on and power-off timing diagram of existing electrification reset circuit, in upward and downward electric process, supply voltage VDD
It can be gradually increasing, turnover voltage, that is, node NET100 voltage can rise with the rising of supply voltage VDD, at this time reset signal
RSTB is 0, and when the value of turnover voltage reaches the threshold voltage of NMOS tube M101, NMOS tube M101 is begun to turn on, it is led at this time
Be powered resistance (Ron) and resistance R103 partial pressure, when power-on reset signal, that is, node NET101 voltage reaches phase inverter INV100's
Reset signal RSTB overturning is 1 when threshold value, and electrification reset process is completed, otherwise is lower electric process.
As shown in Figure 1 it is found that the turnover voltage of available circuit divides supply voltage VDD by resistance R101 and R102
It arrives, in integrated circuits, resistance can occupy biggish chip area, while there are also have biggish power consumption.
In addition, turnover voltage relatively realizes NMOS tube M101 on and off by the threshold voltage with NMOS tube M101
Control, the control to power-on reset signal is finally realized, since the threshold voltage of NMOS tube M101 in practical applications can be with
Technique change, namely the threshold voltage of NMOS tube M101 will not be unalterable in semiconductor integrated circuit, same NMOS tube
M101 can change with the variation of voltage and temperature, be formed in the threshold value electricity of the NMOS tube of the different location on same wafer
Pressure can also have difference from each other, and be formed between the threshold voltage of the NMOS tube on different wafers using same process
Difference is had, the turnover voltage formed by electric resistance partial pressure can not follow the threshold voltage of NMOS tube with technique change, namely work as
When the threshold voltage variation of NMOS tube, turnover voltage can not change in the same direction simultaneously.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of electrification reset circuits, can save area, reduce power consumption, also
Technique is able to achieve to follow.
In order to solve the above technical problems, electrification reset circuit provided by the invention includes:
First NMOS tube and the first PMOS tube.
The source electrode ground connection of first NMOS tube, the grid of first NMOS tube and drain electrode and first PMOS tube
Grid link together and supply voltage be connected to by the first current path.
The source electrode of first PMOS tube is connected to supply voltage by the second current path.
The drain electrode of first PMOS tube is grounded by third current path；The drain electrode of first PMOS tube, which exports, to be resetted
Signal.
The conducting electric current of the third current path is less than the conducting electric current of second current path.
The source electrode of first PMOS tube to the voltage difference between ground is the gate source voltage of first NMOS tube and described
The superposition of the gate source voltage of first PMOS tube, the gate source voltage of the gate source voltage of first NMOS tube and first PMOS tube
And formed turnover voltage.
In upward and downward electric process, first current path and the third current path are all connected, when the power supply electricity
When pressure is less than the turnover voltage, second current path cut-off, the drain voltage of first PMOS tube passes through described the
Three current paths drag down to make the reset signal low level；When the supply voltage is greater than the turnover voltage, institute
It states the second current path to be connected, the conducting electric current of the third current path and second current path is compared and makes institute
The drain voltage for stating the first PMOS tube draws high the value of supply voltage and exports the reset signal with mains voltage variations.
A further improvement is that, further includes:
Current generating circuit, the current generating circuit provide operating current, first current path, institute when powering on
State the work electricity that the conducting electric current of the second current path and the third current path is all provided by the current generating circuit
Traffic mirroring obtains.
A further improvement is that, further includes: start-up circuit, for providing starting when powering on for the current generating circuit
Electric current.
A further improvement is that the current generating circuit include: the second NMOS tube, third NMOS tube, the second PMOS tube,
Third PMOS tube and first resistor.
The source electrode of second PMOS tube connects supply voltage with the source electrode of the third PMOS tube.
The grid of second PMOS tube and the grid of the third PMOS tube link together.
The drain electrode of second PMOS tube connects the drain electrode of second NMOS tube.
The drain electrode of the third PMOS tube connects the drain electrode of the third NMOS tube.
The grid of second NMOS tube and the grid of the third NMOS tube link together.
The source electrode of second NMOS tube is grounded, and the source electrode of the third NMOS tube is grounded by the first resistor.
The electric current in path where the third NMOS tube of the current generating circuit by second NMOS tube grid source
The difference of voltage and the gate source voltage of the third NMOS tube is determined divided by the first resistor.
A further improvement is that start-up circuit, for providing starting current when powering on for the current generating circuit.
A further improvement is that the start-up circuit includes:
4th NMOS tube, the 4th PMOS tube and the 5th PMOS tube.
The source electrode of 4th PMOS tube and the source electrode of the 5th PMOS tube all connect the supply voltage.
The grid of 4th PMOS tube connects the grid of second PMOS tube.
Drain electrode, the grid of the 5th PMOS tube and the grid of the 4th NMOS tube of 4th PMOS tube are connected to
Together.
The source electrode and drain electrode of 4th NMOS tube is all grounded.
The drain electrode of 5th PMOS tube connects the drain electrode of second NMOS tube, in upward and downward electric process, the described 5th
PMOS tube is connected and provides the drain electrode of starting current to second NMOS tube；After current generating circuit starting, described the
The capacitor of four NMOS tubes composition is by the conducting electric current charging of the 4th PMOS tube until ending the 5th PMOS tube.
A further improvement is that first current path is made of the 6th PMOS tube, the source electrode of the 6th PMOS tube
Supply voltage is connected, the grid of the 6th PMOS tube connects the grid of the third PMOS tube, the leakage of the 6th PMOS tube
Pole exports the conducting electric current on first electric current road.
A further improvement is that the ratio of the breadth length ratio of the channel of the 6th PMOS tube and the third PMOS tube is 1:
1。
A further improvement is that second current path is made of the 7th PMOS tube, the source electrode of the 7th PMOS tube
Supply voltage is connected, the grid of the 7th PMOS tube connects the grid of the third PMOS tube, the leakage of the 7th PMOS tube
Pole exports the conducting electric current on second electric current road.
A further improvement is that the ratio of the breadth length ratio of the channel of the 7th PMOS tube and the third PMOS tube is N:
1, N is the integer more than or equal to 2.
A further improvement is that the third current path is made of the 5th NMOS tube, the source electrode of the 5th NMOS tube
Ground connection, the grid of the 5th NMOS tube connect the grid of second NMOS tube, and the drain electrode of the 5th NMOS tube exports institute
State the conducting electric current on third electric current road.
A further improvement is that the ratio of the breadth length ratio of the channel of the 5th NMOS tube and second NMOS tube is 1:
1。
A further improvement is that the drain electrode of first PMOS tube is connected with two concatenated phase inverters, described first
The reset signal is exported after the reverse phase that the drain electrode of PMOS tube passes through two phase inverters.
A further improvement is that first NMOS tube is made of a NMOS tube or is formed by multiple NMOS tube parallel connections；
First PMOS tube is made of a PMOS tube or is formed by multiple PMOS tube parallel connections.
A further improvement is that breadth length ratio or number or first PMOS tube by adjusting first NMOS tube
Breadth length ratio or number adjust the turnover voltage.
Turnover voltage of the invention is formed by the superposition of the gate source voltage of NMOS tube and PMOS tube, compared with the existing technology in
The structure formed using electric resistance partial pressure, the present invention can save circuit area, improve integrated level, while can also reduce power consumption.
In addition, cannot achieve technique relative between existing structure turnover voltage and the threshold voltage of the NMOS tube controlled
The situation followed, turnover voltage of the invention are the superposition of the gate source voltage of NMOS tube and PMOS tube, so turnover voltage can be with
Change in the same direction with the threshold voltage of NMOS tube and PMOS tube difference due to caused by process deviation, to realize turnover voltage
Technique follows；In addition, since turnover voltage of the invention can be adjusted by the breadth length ratio or number of NMOS tube and PMOS tube.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is existing electrification reset circuit figure；
Fig. 2 is the power-on and power-off timing diagram of existing electrification reset circuit；
Fig. 3 is electrification reset circuit figure of the embodiment of the present invention；
Fig. 4 is the power-on and power-off timing diagram of electrification reset circuit of the embodiment of the present invention.
Specific embodiment
As shown in figure 3, being electrification reset circuit figure of the embodiment of the present invention；Electrification reset circuit of the embodiment of the present invention, comprising:
Start-up circuit 1 and electrification reset main circuit 2.Start-up circuit 1, for providing starting electricity when powering on for the current generating circuit
Stream, the electrification reset main circuit 2 are used to form power-on reset signal.
The electrification reset main circuit 2 includes: the first NMOS tube NM3 and the first PMOS tube PM4.
The source electrode of the first NMOS tube NM3 is grounded GND, the grid of the first NMOS tube NM3 and drain electrode and described
The grid of first PMOS tube PM4, which links together, to be connected to node NET0 and is connected to supply voltage by the first current path
VDD。
The source electrode of the first PMOS tube PM4 is connected to supply voltage VDD by the second current path.
Drain electrode, that is, node NET1 of the first PMOS tube PM4 is grounded GND by third current path；First PMOS
The drain electrode output reset signal RSTB of pipe PM4.
The conducting electric current of the third current path is less than the conducting electric current of second current path.
The grid source electricity that the source electrode of the first PMOS tube PM4 is the first NMOS tube NM3 to the voltage difference between ground GND
The superposition of the gate source voltage of pressure and the first PMOS tube PM4, the gate source voltage and described first of the first NMOS tube NM3
The gate source voltage of PMOS tube PM4 and formed turnover voltage.
In upward and downward electric process, first current path and the third current path are all connected, when the power supply electricity
When VDD being pressed to be less than the turnover voltage, the second current path cut-off, the drain voltage of the first PMOS tube PM4 passes through
The third current path drags down to make the reset signal RSTB low level；Described in being greater than as the supply voltage VDD
When turnover voltage, the second current path conducting, the conducting electric current of the third current path and second current path
It is compared and so that the drain voltage of the first PMOS tube PM4 is drawn high the value of supply voltage VDD and export with supply voltage
The reset signal RSTB of VDD variation.
The electrification reset main circuit 2 further includes current generating circuit, and the current generating circuit provides work when powering on
Make electric current, the conducting electric current of first current path, second current path and the third current path all passes through institute
The operating current mirror image for stating current generating circuit offer obtains.
It is preferably selected as, the current generating circuit includes: the second NMOS tube NM0, third NMOS tube NM1, the 2nd PMOS
Pipe PM0, third PMOS tube PM1 and first resistor R0.
The source electrode of the second PMOS tube PM0 connects supply voltage VDD with the source electrode of the third PMOS tube PM1.
The grid of the grid of the second PMOS tube PM0 and the third PMOS tube PM1 link together.
The drain electrode of the second PMOS tube PM0 connects the drain electrode of the second NMOS tube NM0.
The drain electrode of the third PMOS tube PM1 connects the drain electrode of the third NMOS tube NM1.
The grid of the grid of the second NMOS tube NM0 and the third NMOS tube NM1 link together.
The source electrode of the second NMOS tube NM0 is grounded GND, and the source electrode of the third NMOS tube NM1 passes through first electricity
It hinders R0 and is grounded GND.
The electric current in path is by the second NMOS tube NM0 where the third NMOS tube NM1 of the current generating circuit
Gate source voltage and the difference of gate source voltage of the third NMOS tube NM1 determined divided by the first resistor R0.
The start-up circuit 1 includes:
4th NMOS tube Ncap, the 4th PMOS tube PSTP and the 5th PMOS tube PST.
The source electrode of the 4th PMOS tube PSTP and the source electrode of the 5th PMOS tube PST all connect the supply voltage
VDD。
The grid of the 4th PMOS tube PSTP connects the grid of the second PMOS tube PM0.
The drain electrode of the 4th PMOS tube PSTP, the 5th PMOS tube PST grid and the 4th NMOS tube Ncap
Grid link together.
The source electrode and drain electrode of the 4th NMOS tube Ncap is all grounded GND.
The drain electrode of the 5th PMOS tube PST connects the drain electrode of the second NMOS tube NM0, in upward and downward electric process, institute
It states the 5th PMOS tube PST and is connected and provides the drain electrode of starting current to the second NMOS tube NM0；The current generating circuit opens
After dynamic, the capacitor of the 4th NMOS tube Ncap composition is by the conducting electric current charging of the 4th PMOS tube PSTP until making institute
State the 5th PMOS tube PST cut-off.
First current path is made of the 6th PMOS tube PM2, the source electrode connection power supply electricity of the 6th PMOS tube PM2
VDD is pressed, the grid of the 6th PMOS tube PM2 connects the grid of the third PMOS tube PM1, the 6th PMOS tube PM2's
The conducting electric current on drain electrode output first electric current road.
Second current path is made of the 7th PMOS tube PM3, the source electrode connection power supply electricity of the 7th PMOS tube PM3
VDD is pressed, the grid of the 7th PMOS tube PM3 connects the grid of the third PMOS tube PM1, the 7th PMOS tube PM3's
The conducting electric current on drain electrode output second electric current road.
The third current path is made of the 5th NMOS tube NM2, and the source electrode of the 5th NMOS tube NM2 is grounded GND, institute
The grid for stating the 5th NMOS tube NM2 connects the grid of the second NMOS tube NM0, the drain electrode output of the 5th NMOS tube NM2
The conducting electric current on third electric current road.
The ratio of the breadth length ratio of the channel of the 5th NMOS tube NM2 and the second NMOS tube NM0 is 1:1.Described
The ratio of the breadth length ratio of the channel of three PMOS tube PM1, the 6th PMOS tube PM2 and the 7th PMOS tube PM3 sum is 1:1:
N, N are the integer more than or equal to 2.
The drain electrode of the first PMOS tube PM4 is connected with two concatenated phase inverter INV0 with INV1, the first PMOS
The reset signal RSTB is exported after the reverse phase that the drain electrode of pipe PM4 passes through two phase inverter INV0 and INV1.
The first NMOS tube NM3 is made of a NMOS tube or is formed by multiple NMOS tube parallel connections；First PMOS
Pipe PM4 is made of a PMOS tube or is formed by multiple PMOS tube parallel connections.By the breadth length ratio for adjusting the first NMOS tube NM3
Or number or the breadth length ratio or number of the first PMOS tube PM4 adjust the turnover voltage.
As shown in figure 4, being the power-on and power-off timing diagram of electrification reset circuit of the embodiment of the present invention, wherein curve 101 is power supply
The change curve of voltage VDD, curve 102 are the change curve of reset signal RSTB, the principle of circuit of the embodiment of the present invention are as follows: when
When supply voltage VDD is powered on, current generating circuit generates electric current I 1, I 1=(Vgs_NM0-Vgs_NM1)/R0, wherein Vgs_
NM0 is the gate source voltage of the second NMOS tube NM0, and Vgs_NM1 is the gate source voltage of third NMOS tube NM1, and R0 is first resistor R0
Value；When supply voltage VDD is lower than Vgs_NM3+Vgs_PM4, the first PMOS tube PM4 is closed, and wherein Vgs_NM3 is first
The gate source voltage of NMOS tube NM0, Vgs_PM4 are the gate source voltage of the first PMOS tube PM4, and since the 5th NMOS tube NM2 is to lead
Logical, therefore the 5th NMOS tube NM2 can drag down node NET1, reset signal RSTB is low level at this time；
When supply voltage VDD rises to Vgs_NM3+Vgs_PM4, the first PMOS tube PM4 conducting, due to the 7th PMOS tube
The electric current of PM3 mirror image is greater than the electric current of the 5th NMOS tube NM2 mirror image, and node NET1 is raised, at this time reset signal RSTB be with
The high level signal changed with supply voltage VDD.
In Fig. 4, the coordinate of point M0 is (4.72ms, 943.9mV), and 943.9mV corresponds to Vgs_NM3+Vgs_PM4 upper
Value in lower electric process, 0 into the power up between 4.72ms, reset signal RSTB is low level；In supply voltage VDD
Greater than 943.9mV until during rising to maximum value, reset signal RSTB is the height electricity for the variation for following supply voltage VDD
It is flat that i.e. curve 101 and 102 is overlapped at this time.
The maximum value since supply voltage VDD during lower electricity, the coordinate of point M1 be (15.58ms,
884.3mV), when supply voltage VDD drops to less than 884.3mV, 884.3m V corresponds to Vgs_NM3+Vgs_PM4 in lower electricity
Value in the process, when the time being less than 15.58ms, reset signal RSTB is the high level for following the variation of supply voltage VDD；When
It is low level in reset signal RSTB when time is greater than 15.58ms.
To sum up, low level reset signal RSTB can be generated in supply voltage VDD power up, reset signal RSTB's
Turnover voltage is Vgs_NM3+Vgs_PM4, and the breadth length ratio or number that can adjust the first NMOS tube NM3 and the first PMOS tube PM4 are come
The resetting voltage is adjusted, while can realize that technique follows.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of electrification reset circuit characterized by comprising
First NMOS tube and the first PMOS tube；
The grid of the source electrode ground connection of first NMOS tube, the grid of first NMOS tube and drain electrode and first PMOS tube
Pole links together and is connected to supply voltage by the first current path；
The source electrode of first PMOS tube is connected to supply voltage by the second current path；
The drain electrode of first PMOS tube is grounded by third current path；The drain electrode output of first PMOS tube resets letter
Number；
The conducting electric current of the third current path is less than the conducting electric current of second current path；
The source electrode of first PMOS tube to the voltage difference between ground be first NMOS tube gate source voltage and described first
The sum of the gate source voltage of the superposition of the gate source voltage of PMOS tube, the gate source voltage of first NMOS tube and first PMOS tube
Form turnover voltage；
In upward and downward electric process, first current path and the third current path are all connected, when the supply voltage is small
When the turnover voltage, the drain voltage of the second current path cut-off, first PMOS tube passes through the third electricity
Flow path drags down to make the reset signal low level；When the supply voltage is greater than the turnover voltage, described the
The conducting of two current paths, the conducting electric current of the third current path and second current path are compared and make described the
The drain voltage of one PMOS tube draws high the value of supply voltage and exports the reset signal with mains voltage variations.
2. electrification reset circuit as described in claim 1, which is characterized in that further include:
Current generating circuit, the current generating circuit provide operating current, first current path, described when powering on
The conducting electric current of two current paths and the third current path all passes through the operating current mirror that the current generating circuit provides
As obtaining.
3. electrification reset circuit as claimed in claim 2, which is characterized in that further include: start-up circuit, for being when powering on
The current generating circuit provides starting current.
4. electrification reset circuit as claimed in claim 2, which is characterized in that the current generating circuit includes: the 2nd NMOS
Pipe, third NMOS tube, the second PMOS tube, third PMOS tube and first resistor；
The source electrode of second PMOS tube connects supply voltage with the source electrode of the third PMOS tube；
The grid of second PMOS tube and the grid of the third PMOS tube link together；
The drain electrode of second PMOS tube connects the drain electrode of second NMOS tube；
The drain electrode of the third PMOS tube connects the drain electrode of the third NMOS tube；
The grid of second NMOS tube and the grid of the third NMOS tube link together；
The source electrode of second NMOS tube is grounded, and the source electrode of the third NMOS tube is grounded by the first resistor；
The electric current in path where the third NMOS tube of the current generating circuit by second NMOS tube gate source voltage
It is determined with the difference of the gate source voltage of the third NMOS tube divided by the first resistor.
5. electrification reset circuit as claimed in claim 4, which is characterized in that further include: start-up circuit, for being when powering on
The current generating circuit provides starting current.
6. electrification reset circuit as claimed in claim 5, which is characterized in that the start-up circuit includes:
4th NMOS tube, the 4th PMOS tube and the 5th PMOS tube；
The source electrode of 4th PMOS tube and the source electrode of the 5th PMOS tube all connect the supply voltage；
The grid of 4th PMOS tube connects the grid of second PMOS tube；
Drain electrode, the grid of the 5th PMOS tube and the grid of the 4th NMOS tube of 4th PMOS tube are connected to one
It rises；
The source electrode and drain electrode of 4th NMOS tube is all grounded；
The drain electrode of 5th PMOS tube connects the drain electrode of second NMOS tube, in upward and downward electric process, the 5th PMOS
Pipe is connected and provides the drain electrode of starting current to second NMOS tube；After the current generating circuit starting, the described 4th
The capacitor of NMOS tube composition is by the conducting electric current charging of the 4th PMOS tube until ending the 5th PMOS tube.
7. the electrification reset circuit as described in claim 4 or 5 or 6, it is characterised in that: first current path is by the 6th
PMOS tube composition, the source electrode of the 6th PMOS tube connect supply voltage, and the grid of the 6th PMOS tube connects the third
The grid of PMOS tube, the drain electrode of the 6th PMOS tube export the conducting electric current of first current path.
8. electrification reset circuit as claimed in claim 7, it is characterised in that: the 6th PMOS tube and the third PMOS tube
Channel breadth length ratio ratio be 1:1.
9. the electrification reset circuit as described in claim 4 or 5 or 6, it is characterised in that: second current path is by the 7th
PMOS tube composition, the source electrode of the 7th PMOS tube connect supply voltage, and the grid of the 7th PMOS tube connects the third
The grid of PMOS tube, the conducting electric current on drain electrode output second electric current road of the 7th PMOS tube.
10. electrification reset circuit as claimed in claim 9, it is characterised in that: the 7th PMOS tube and the 3rd PMOS
The ratio of the breadth length ratio of the channel of pipe is N:1, and N is the integer more than or equal to 2.
11. the electrification reset circuit as described in claim 4 or 5 or 6, it is characterised in that: the third current path is by the 5th
NMOS tube composition, the source electrode ground connection of the 5th NMOS tube, the grid of the 5th NMOS tube connect second NMOS tube
Grid, the conducting electric current on the drain electrode output third electric current road of the 5th NMOS tube.
12. electrification reset circuit as claimed in claim 11, it is characterised in that: the 5th NMOS tube and the 2nd NMOS
The ratio of the breadth length ratio of the channel of pipe is 1:1.
13. electrification reset circuit as described in claim 1, it is characterised in that: the drain electrode of first PMOS tube and two strings
The phase inverter of connection connects, and the reset letter is exported after the reverse phase that the drain electrode of first PMOS tube passes through two phase inverters
Number.
14. electrification reset circuit as described in claim 1, it is characterised in that: first NMOS tube is by a NMOS tube group
It is formed at or by multiple NMOS tube parallel connections；First PMOS tube is made of a PMOS tube or by multiple PMOS tube parallel connection shape
At.
15. electrification reset circuit as claimed in claim 14, it is characterised in that: long by the width for adjusting first NMOS tube
Than or the breadth length ratio or number of number or first PMOS tube adjust the turnover voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610330481.1A CN106027006B (en) | 2016-05-18 | 2016-05-18 | Electrification reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610330481.1A CN106027006B (en) | 2016-05-18 | 2016-05-18 | Electrification reset circuit |
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| Publication Number | Publication Date |
|---|---|
| CN106027006A CN106027006A (en) | 2016-10-12 |
| CN106027006B true CN106027006B (en) | 2019-02-05 |
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| CN201610330481.1A Active CN106027006B (en) | 2016-05-18 | 2016-05-18 | Electrification reset circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10312902B2 (en) * | 2016-10-28 | 2019-06-04 | Analog Devices Global | Low-area, low-power, power-on reset circuit |
| CN107066018B (en) * | 2017-06-29 | 2018-09-28 | 英麦科（厦门）微电子科技有限公司 | A kind of accurate por circuit |
| CN107888173B (en) * | 2017-12-27 | 2024-04-02 | 苏州菲达旭微电子有限公司 | Power-on reset circuit |
| JP2021128348A (en) | 2018-04-25 | 2021-09-02 | ソニーセミコンダクタソリューションズ株式会社 | Starting circuit |
| WO2022067739A1 (en) * | 2020-09-30 | 2022-04-07 | 深圳市汇顶科技股份有限公司 | Power-on reset circuit |
| CN112838850B (en) * | 2020-12-30 | 2024-09-10 | 合肥市芯海电子科技有限公司 | Power-on reset circuit, integrated circuit and electronic equipment |
| CN114172500B (en) * | 2021-12-02 | 2025-03-14 | 普冉半导体(上海)股份有限公司 | Integrated circuit power-on reset circuit |
| CN117728810B (en) * | 2023-11-13 | 2025-01-07 | 中科南京智能技术研究院 | Power-on reset circuit and integrated circuit system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4476501B2 (en) * | 2001-01-30 | 2010-06-09 | Ｏｋｉセミコンダクタ株式会社 | Power-on reset circuit |
| KR100614645B1 (en) * | 2004-06-03 | 2006-08-22 | 삼성전자주식회사 | Power-On Reset Circuit |
| JP4504108B2 (en) * | 2004-06-15 | 2010-07-14 | 富士通セミコンダクター株式会社 | Reset circuit |
| JP5225876B2 (en) * | 2009-01-29 | 2013-07-03 | セイコーインスツル株式会社 | Power-on reset circuit |
| JP5978084B2 (en) * | 2012-01-30 | 2016-08-24 | エスアイアイ・セミコンダクタ株式会社 | Power-on reset circuit |
| CN104601151A (en) * | 2015-01-09 | 2015-05-06 | 昆腾微电子股份有限公司 | Power on/off detection reset circuit |
-
2016
- 2016-05-18 CN CN201610330481.1A patent/CN106027006B/en active Active
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| CN106027006A (en) | 2016-10-12 |
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