CN106024908A - Thin film transistor fabrication method and array substrate fabrication method - Google Patents

Abstract

An embodiment of the present invention relates to a method for manufacturing a thin film transistor and an array substrate, wherein the method for manufacturing a thin film transistor includes a process of forming a gate pattern, an active layer pattern, and a source-drain pattern on a substrate, including: Forming the active layer film; forming the pattern of the etching barrier layer on the active layer film; forming the pattern of the source and drain on the pattern of the etching barrier layer; using the pattern of the etching barrier layer and the pattern of the source and drain as a mask The thin film of the active layer is etched to form the pattern of the active layer. In the embodiment of the present invention, no mask is used when forming the active layer, and one mask is used when the source and drain are formed, and etching is performed continuously at the same time. The embodiment of the present invention does not use a semi-transparent mask plate, which reduces the masking process for forming the active layer once and simplifies the process flow.

Description

A method for manufacturing a thin film transistor and a method for manufacturing an array substrate

technical field

The embodiments of the present invention relate to the technical field of semiconductor processing, and in particular to a method for manufacturing a thin film transistor and a method for manufacturing an array substrate.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) has the characteristics of small size, low power consumption, no radiation, and relatively low production cost, and occupies a dominant position in the current flat panel display device market. Examples include LCD TVs, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens, etc.

Generally, a liquid crystal display device includes a housing, a liquid crystal display panel disposed in the housing, and a backlight module disposed in the housing. Among them, the liquid crystal display panel, which is the core component of TFT-LCD, is mainly composed of a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), a color filter substrate (Color Filter, CF) box and a box arranged between the two substrates. The liquid crystal layer (Liquid Crystal Layer) constitutes.

In the field of displays, the oxide semiconductor oxide TFT has a good application prospect because the mobility of the oxide semiconductor oxide TFT is more than 10 times that of the ordinary amorphous silicon semiconductor a_Si TFT. However, although the existing SWC structure is expected to have better results in terms of reliability, it needs to use a semi-transparent mask HTM process, which is complicated and difficult to control, and the TFT size of the thin film transistor is also large.

As shown in Figure 1, in the existing oxide TFT manufacturing process, in steps (a) to (d), when forming the etch barrier layer, a semi-permeable mask is used to control the etch barrier layer and the active layer. layer etching. In steps (e) to (f), etching is performed once when forming the source and drain electrodes, and then the active layer is etched using the pattern of the source and drain electrodes as a mask to form the active layer. The traditional oxide SWC (Side Contact Type) needs to consider the etch stop layer ESL and the source-drain overlap SD overlap size is generally around 2um. The existing oxide SWC TFT has the following disadvantages: traditional SWC needs to use HTM to reduce the mask, and compared with the back channel etching BCE, the process is complicated and difficult to control.

Contents of the invention

The technical problem to be solved is how to simplify the oxide semiconductor manufacturing process.

In view of the defects in the prior art, the embodiments of the present invention provide a thin film transistor manufacturing method and an array substrate manufacturing method, which can simplify the manufacturing process and reduce the manufacturing cost.

In the first aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including a process of forming a gate pattern, an active layer pattern, and a source-drain pattern on a substrate, including:

Forming the active layer thin film;

Forming the pattern of etching barrier layer on the active layer film;

forming a source-drain pattern on the pattern of the etching barrier layer;

The pattern of the active layer is etched to form the pattern of the active layer by using the pattern of the etch barrier layer and the pattern of the source and drain electrodes as a mask.

Optionally, also include:

forming a gate film on the substrate;

Patterning the gate film to form a gate pattern;

Remove remaining photoresist.

Optionally, before forming the active layer thin film on the gate pattern, it also includes:

It also includes the process of forming a gate insulating film on the gate pattern film.

Optionally, the pattern of forming the etch barrier layer on the active layer film includes:

forming an etching stopper film on the active layer film;

Coating photoresist on the etching barrier film;

Exposing and developing the photoresist to form a pattern of an etching barrier layer;

Remove remaining photoresist.

Optionally, the pattern of forming the source and drain electrodes on the active layer film includes:

Forming source and drain thin films on the active layer;

Coating photoresist on the source-drain film;

Exposing and developing the photoresist to form a source-drain pattern;

Remove remaining photoresist.

In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, including a process of manufacturing a thin film transistor according to the above method for manufacturing a thin film transistor.

Optionally, also include:

A process for forming an insulating layer on the thin film transistor.

Optionally, forming an insulating film on the thin film transistor is also included.

Optionally, a process of forming a common electrode on the thin film transistor is also included, including:

forming a common electrode thin film on the thin film via transistor;

Coating photoresist on the common electrode film;

Exposing and developing the photoresist to form a common electrode pattern;

Remove remaining photoresist.

Optionally, a process of forming a planarization layer on the pattern of the common electrode is also included;

It also includes the process of forming a pixel electrode via hole on the planarization layer to expose the drain.

Optionally, a process of forming a pixel electrode on the common electrode layer is also included, including:

forming a pixel electrode film on the common electrode;

Coating photoresist on the pixel electrode film;

Exposing and developing the photoresist to form the pattern of the pixel electrode;

Remove remaining photoresist.

It can be seen from the above technical solutions that the thin film transistor manufacturing method and the array substrate manufacturing method provided by the embodiments of the present invention do not use a mask when forming the active layer, but share a mask when forming the source and drain electrodes, and simultaneously etch continuously . The embodiment of the present invention does not use a semi-transparent mask plate, which reduces the masking process for forming the active layer once and simplifies the process flow. Since the TFT does not consider the alignment accuracy of the source, drain and active layer, the method provided by the embodiment of the present invention can be self-aligned. By using the same mask plate to form the source-drain pattern and the active layer pattern, there will be no residue of the active layer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will give a brief introduction to the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a manufacturing process of a thin film transistor in the prior art;

FIG. 2 is a schematic diagram of a manufacturing process flow of a thin film transistor in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a manufacturing process flow of an array substrate in an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in FIG. 2, an embodiment of the present invention provides a method for manufacturing a thin film transistor, which includes a process of forming a gate pattern 2, an active layer pattern 3, and patterns of source and drain electrodes 5 and 6 on a base substrate, specifically Including: forming the active layer film 30; forming the pattern of the etching barrier layer 4 on the active layer film 30; forming the pattern of the source and drain electrodes 5, 6 on the pattern of the etching barrier layer 4; The patterns of the source and drain electrodes 5 and 6 are used as masks to etch the active layer film 30 to form the active layer pattern 3 . The method for manufacturing the thin film transistor provided by the embodiment of the present invention will be described in detail below.

As shown in FIG. 2 , in step (a) to step (b), when manufacturing a thin film transistor, it is necessary to form a gate film 20 on the base substrate 1 . In the embodiment of the present invention, the gate thin film 20 may be formed by spraying, sputtering and the like. After the gate film 20 is formed, the gate and gate line patterns 2 are formed on the gate film 20 through a patterning process. The remaining photoresist is stripped after forming the gate and gate line pattern 2 .

In one embodiment of the present invention, after step (b) is completed, it is necessary to further form a gate insulating layer film on the grid gate and the gate line pattern, and this gate insulating layer film is used to isolate the gate 2 and the active layer 30 , to avoid a short circuit between the gate pattern and the active layer 30 .

As shown in FIG. 2 , in step (b) to step (c), an active layer film 30 is formed on the gate and gate pattern 2 . In the embodiment of the present invention, the active layer thin film 30 can be formed by spraying, sputtering and other methods.

As shown in FIG. 2 , in step (c) to step (d), after forming the active layer film 30 , it is necessary to form the pattern of the etching stopper layer 4 on the active layer film 30 . Specifically, it includes: forming an etching stopper film 40 on the active layer film 30; in the embodiment of the present invention, forming the active layer film 30 can be formed by spraying, sputtering, and the like. Coating photoresist on the etching stop film 40; exposing and developing the photoresist to form the pattern of the etching stop layer 4; removing the remaining photoresist.

As shown in FIG. 2 , in step (d) to step (e), patterns of source and drain electrodes 5 and 6 need to be formed on the etch stop layer 4 after the pattern 4 of the etch stop layer is formed. Specifically, forming patterns of the source and drain electrodes 5 and 6 on the active layer 3 and the etching barrier layer 4 includes: forming a source and drain film on the active layer 3; coating a photoresist on the source and drain film; Exposing and developing the photoresist to form patterns of source and drain electrodes 5 and 6; removing the remaining photoresist.

As shown in Figure 2, in step (e) to step (f), after forming the pattern of source and drain electrodes 5,6, the pattern of etch barrier layer 4 and the pattern of source and drain electrodes 5,6 are used as mask pairs The active layer film 30 is etched to form the active layer pattern 3 . Alternatively, the active layer film 30 is etched to form the active layer pattern 3 by using the masks of the source and drain electrodes 5 and 6 together with the etch stop layer as a mask. Specifically: the active layer film 30 is etched using the pattern of the etching stopper layer 4 and the pattern of the source and drain electrodes 5 and 6 as a mask, and the pattern of the etching stopper layer 4 and the patterns of the source and drain electrodes 5 and 6 are removed The other active layer thin films form the active layer pattern 3 .

In the embodiment of the present invention, the mask plate is used in the pattern process of forming the gate pattern 2, the pattern of the etch stop layer 4, and the source and drain electrodes 5, 6, and the etching plate is directly used in the process of forming the active layer pattern 3. The pattern of the etch barrier layer 4 and the patterns of the source and drain electrodes 5 and 6 are masks, which saves a mask process for forming the pattern 3 of the active layer, simplifies the manufacturing process of the thin film transistor, and reduces the manufacturing cost.

In order to further embody the superiority of the thin film transistor manufacturing method provided by the embodiment of the present invention, the embodiment of the present invention also provides a method for manufacturing an array substrate, as shown in FIG. 3 , including manufacturing a thin film transistor according to the above thin film transistor manufacturing method process.

As shown in FIG. 3 , in the embodiment of the present invention, the steps of forming a thin film transistor in the forming step (a) to step (f) are basically the same as those in the above embodiment, and will not be repeated here.

As shown in Figure 3, in step (f) to step (g), after forming the pattern of source drain 5,6, form passivation layer film 7 on the pattern of source drain 5,6, this passivation The thin film 7 is used to protect the source and drain electrodes, avoid oxidation of the source and drain electrodes, affect the display effect, and prolong the life of the display panel. In the embodiment of the present invention, the thin film 7 for forming the passivation layer can be formed by spraying, sputtering and the like.

As shown in Figure 3, in step (g) to step (h) or in step (f) to step (h), after forming the pattern of source and drain 5,6 directly on the pattern of source and drain 5,6 The insulating layer 8 is formed on the passivation layer film 7, or the insulating layer 8 is formed on the passivation layer film 7 after step (g) is completed. The insulating layer 8 not only isolates the source electrode 5, the drain electrode 6 and the common electrode, avoids the short circuit between the source electrode 5, the drain electrode 6 and the common electrode, but also can planarize the surface of the array substrate. Specifically, the insulating layer 8 can be formed by spraying, sputtering and the like.

As shown in FIG. 3, in step (h) to step (i), after forming the planarization layer 8, the pattern of the common electrode 9 is formed on the planarization layer 8, specifically, the common electrode film is formed on the insulating layer 8 , coating the photoresist on the common electrode film; exposing and developing the photoresist to form the pattern of the common electrode 9; removing the remaining photoresist. Wherein, the common electrode film can be formed by spraying, sputtering and other methods.

As shown in FIG. 3 , in step (i) to step (j), after the pattern of the common electrode 9 is formed, a planarization layer 10 is formed on the common electrode 9 . Specifically, the planarization layer 10 is formed on the common electrode 9 by spraying or sputtering. A pixel electrode via hole 100 is further formed on the planarization layer 10 to expose the drain electrode 6 . Specifically, a photoresist is coated on the planarization layer 10; the photoresist is exposed and developed, and the planarization layer 10, the insulating layer 8 and the passivation layer 7 corresponding to the via holes are etched away, so that the drain electrode 6 Expose and form a pixel electrode via hole; remove the remaining photoresist. In the embodiment of the present invention, the via hole 100 for the pixel electrode can be formed after forming the planarization layer through one processing process, or it can be formed separately on the pixel electrode while the insulating layer 8, the planarization layer 10 and the passivation layer 7 are formed. The position of the via hole 100 is etched multiple times to form the pixel electrode via hole 100 . Of course, it can be understood that the present invention is not limited thereto, and the present invention can still be realized by other schemes of forming the pixel electrodes, which will not be repeated here.

As shown in FIG. 3 , in step (i) to step (k), the pixel electrode 11 is formed on the pattern 9 of the common electrode after the pattern of the common electrode 9 is formed. Specifically include: forming a pixel electrode film on the common electrode; coating photoresist on the pixel electrode film; exposing and developing the photoresist to form the pattern of the pixel electrode 11; removing the remaining photoresist. Wherein, the pixel electrode film can be formed by spraying, sputtering and other methods.

To sum up, the thin film transistor manufacturing method and the array substrate manufacturing method provided by the embodiment of the present invention do not use a mask when forming the active layer, but share a mask when forming the source and drain electrodes, and simultaneously etch continuously, The embodiment of the present invention does not use a semi-permeable mask plate, which reduces one mask process for forming the active layer. The process flow is simplified. Since the TFT does not consider the alignment accuracy of the source, drain and active layer, the method provided by the embodiment of the present invention can be self-aligned. By using the same mask plate to form the source-drain pattern and the active layer pattern, there will be no residue of the active layer.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. The orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must Having a particular orientation, being constructed and operating in a particular orientation, and therefore not to be construed as limiting the invention. Unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be a direct connection, or an indirect connection through an intermediary, or an internal communication between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the description of the invention, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. Similarly, it should be appreciated that in the above description of exemplary embodiments of the invention, in order to streamline the present disclosure and to facilitate understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together into a single embodiment , figure, or description of it. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. All of them should be covered by the scope of the claims and description of the present invention.

Claims (11)

1. A method for manufacturing a thin film transistor, characterized in that it comprises the flow process of forming a gate pattern, an active layer pattern and a source-drain pattern on a base substrate, including: Forming the active layer thin film; Forming the pattern of etching barrier layer on the active layer film; forming a source-drain pattern on the pattern of the etching barrier layer; The pattern of the active layer is etched to form the pattern of the active layer by using the pattern of the etch barrier layer and the pattern of the source and drain electrodes as a mask. 2. The thin film transistor manufacturing method according to claim 1, further comprising: forming a gate film on the substrate; Patterning the gate film to form a gate pattern; Remove remaining photoresist. 3. The method for manufacturing a thin film transistor according to claim 1, further comprising: It also includes the process of forming a gate insulating film on the gate pattern film. 4. The method for manufacturing a thin film transistor according to claim 1, wherein the pattern of forming an etching stopper layer on the active layer film comprises: forming an etching stopper film on the active layer film; Coating photoresist on the etching barrier film; Exposing and developing the photoresist to form a pattern of an etching barrier layer; Remove remaining photoresist. 5. The method for manufacturing a thin film transistor according to claim 1, wherein the pattern of forming the source and drain electrodes on the active layer film comprises: Forming source and drain thin films on the active layer; Coating photoresist on the source-drain film; Exposing and developing the photoresist to form a source-drain pattern; Remove remaining photoresist. 6. A method for manufacturing an array substrate, comprising a process of manufacturing a thin film transistor according to the method for manufacturing a thin film transistor according to any one of claims 1-5. 7. The method for manufacturing an array substrate according to claim 6, further comprising: A process for forming a passivation layer on the thin film transistor. 8. The method for manufacturing an array substrate according to claim 6 or 7, further comprising forming an insulating film on the thin film transistor. 9. The method for manufacturing an array substrate according to claim 6 or 7, further comprising a process of forming a common electrode on the thin film transistor, including: forming a common electrode thin film on the thin film via transistor; Coating photoresist on the common electrode film; Exposing and developing the photoresist to form a common electrode pattern; Remove remaining photoresist. 10. The method for manufacturing an array substrate according to claim 7, further comprising a process of forming a planarization layer on the pattern of the common electrode; It also includes the process of forming a pixel electrode via hole on the planarization layer to expose the drain. 11. The method for manufacturing an array substrate according to claim 9, further comprising a process of forming a pixel electrode on the common electrode layer, comprising: forming a pixel electrode film on the common electrode; Coating photoresist on the pixel electrode film; Exposing and developing the photoresist to form the pattern of the pixel electrode; Remove remaining photoresist.